STWLC68JRH

STWLC68 Datasheet Qi-compliant inductive wireless power receiver for 5W applications Features • • • • • • • • • • • • Up to 5 W output power Qi 1.2.4 inductive wireless standard communication protocol compliant Integrated 27 V synchronous rectifier with 98% (typ.) efficiency Low drop-out linear regulator with output current and input voltage control loops 3.6 V to 20 V programmable output voltage with 25 mV resolution Up to 80% overall system efficiency 32-bit, 64 MHz ARM Cortex microcontroller core OTP memory for configuration data 8-channels, 10-bit A/D Converter 6 configurable GPIOs Accurate voltage/current measurement for Foreign Object Detection (FOD) Output Over-Voltage clamping protection • • • 400 kHz I2C interface On-chip thermal management and protections (Over-voltage, Over-current) Enhanced power dissipation capability Chip-Scale Package (CSP) Application Product status link STWLC68 • • • • • Smartphones and PDAs Power banks GPS navigators Medical and healthcare equipment Wearable devices Product summary Order code STWLC68JRH Package WLCSP72 Packing Tape and reel Description The STWLC68 is an integrated Wireless Power Receiver suitable for portable applications and capable of managing up to 5 W of output power. The chip has been designed to support Qi 1.2.4 specifications for inductive communication protocol and Base Power Profile (BPP). The STWLC68 shows excellent efficiency performance thanks to the integrated lowloss synchronous rectifier and the low drop-out linear regulator: both elements are dynamically managed by the digital core to minimize the overall power dissipation over a wide range of output load conditions. Through the I2C interface the user can access and modify different configuration parameters, tailoring the operation of the device to the needs of custom applications. The configuration parameters can be saved in the embedded OTP memory and automatically retrieved at power-up, allowing the STWLC68 to operate as standalone device. The STWLC68 is housed in a Chip-Scale Package to fit real-estate solutions in wearable devices. DS13131 - Rev 4 - June 2022 For further information contact your local STMicroelectronics sales office. www.st.com STWLC68 Introduction 1 Introduction STWLC68 is a Wireless Power Receiver that rectifies the AC voltage developed across the receiving coil and provides a regulated DC voltage at the output. The 32-bit core MCU is the supervisor of the whole device and manages all the functional blocks to • establish and maintain communication with the transmitter, • ensure adherence to Qi standard specifications (wherever required), • optimize the efficiency by properly adjusting the operating point • guarantee reliability by monitoring and protecting both the load and the device itself. In order to execute the above mentioned (and many others) task, the MCU core relies on a resident firmware stored in ROM memory. In addition, some configuration parameters (e.g. output voltage, FOD tuning parameters, etc.) can be saved in the internal One-Time Programmable (OTP) memory and retrieved at power-up, allowing the STWLC68 to operate as a fully autonomuous stand-alone chip. Applications in which the host system directly monitors or controls the power transfer, the I2C interface provides full access to the internal registers of the STWLC68. The device is also equipped with six programmable general-purpose I/O pins (GPIOs) to implement specific functions (e.g. driving status LEDs, enabling the output on request, informing the host system about faulty conditions, etc.). Block diagram shows the block diagram of the device with simplified interconnections among the functional blocks. The synchronous rectifier converts the AC voltage from the receiving coil into a DC voltage at the VRECT pin. The four switches of the rectifier (that is basically an H-bridge) are controlled by the digital core in order to minimize both conduction and switching losses as a function of the output voltage and current, both monitored by two channels of the ADC. Two bootstrap capacitors are externally connected to the BOOT1-BOOT2 pins to correctly drive the high-side switches of the rectifier. The output of the rectifier, filtered by an external capacitor, is also the input rail for the main LDO linear regulator and for the auxiliary linear regulators in charge of deriving the 5 V and 1.8 V supply voltages. The digital core has full control of the main LDO linear regulator in order to manage the output voltage, the output current and the drop-out voltage: since the most relevant contribution to the total chip power dissipation is due to the main linear regulator, minimizing its drop-out voltage is a key factor. Of course the minimization of the drop-out voltage requires a closed loop regulation of the voltage at the VRECT pin, i.e. a feedback information that is sent to the transmitter (via ASK modulation) which, in turn, adjusts the delivered power by acting on the supply voltage, the switching frequency or the switching duty-cycle (or a combination of the three) of its own power stage, depending on the adopted technique. This regulation loop involving the transmitter is an essential part of the wireless power transmission and is extensively described in Qi specifications. DS13131 - Rev 4 page 2/32 STWLC68 Block diagram 2 Block diagram Figure 1. Simplified block diagram DS13131 - Rev 4 page 3/32 STWLC68 Device pinout 3 Device pinout Figure 2. Pin assignment (through top view) Table 1. Pin description Pin name Pin location Pin function C4,C5,D3,D4, VSSA D5,E5,F5,F6, Analog ground. Power return for the main LDO and the analog circuitry. G6,G7 DS13131 - Rev 4 VSSD E4, F3, F4, G2, G3, G4, H3, H4, H5, H6, H7 VSSP A1, A8, B1, B8 Power ground. Power return for the synchronous rectifier. AC1 A6, A7, B6, B7 AC power input: input of the synchronous rectifier. Connect to RX series resonant circuit. AC2 A2, A3, B2, B3 AC power input: input of the synchronous rectifier. Connect to RX series resonant circuit. BOOT1 E7 Synchronous rectifier bootstrap capacitor connection: a 47 nF (typ.) ceramic capacitor is connected between this pin and AC1. BOOT2 C1 Synchronous rectifier bootstrap capacitor connection: a 47 nF (typ.) ceramic capacitor is connected between this pin and AC2. BOOT E8 Main LDO power transistor bootstrap capacitor. Connect a 4.7 nF (typ.) ceramic capacitor between this pin and VRECT. Digital ground. Reference for digital input and output signals. page 4/32 STWLC68 Device pinout Pin name Pin location Pin function CLAMP1 C8 CLAMP2 C7 Auxiliary modulation switches connection: capacitors between CLAMP1 and AC1 and between CLAMP2 and AC2 are used to implement additional ASK modulation. These pins are optionally used, in conjunction with COMM1 and COMM2 pins, to modify the ASK modulation index in specific operating conditions. VRECT B5, C3 Synchronous rectifier output and input for the main LDO linear regulator. A suitable capacitor between these pins and VSSP ensures residual AC ripple filtering and energy storage for proper load transient response. VS F1 Reserved: this pin must be left floating. DFT G1 Reserved: this pin must be connected to ground. BOOT_SEL J5 Reserved: this pin must be connected to ground. NTC F8 Coil temperature sensing input: this pin is connected to the center tap of a resistor divider having an NTC in the low-side position. If this function is not used, the pin must be pulled-up to V18 through a 10 kΩ resistor to prevent triggering the coil over-temperature protection. COMM1 D8 COMM2 D7 VOUT DS13131 - Rev 4 A4, A5, B4, D2, E1, E2, E3, F2 Modulation switches connection: capacitors between COMM1 and AC1 pin and between COMM2 and AC2 pin are used to implement ASK modulation. Main LDO linear regulator output voltage. Connect a suitable filtering capacitor between these pins and VSSA to ensure stable operation and proper load transient response in all operating conditions. V1V8 G5, G8 1.8V LDO output and supply rail for the digital core, the ADC and the analog circuitry. Connect a 1 μF filtering capacitor between this pin and ground. V5V0 F7, E6 5V LDO output and supply rail for the auxiliary circuitry. Connect a 1 μF filtering capacitor between this pin and ground. RSTB J6 Chip-reset input. If set low, the internal digital core is reset. This pin is eventually used by the host controller to control the power transfer process. Connect to V1V8 pin if not used. IEXT C2 Internal pull-down switch for resisitive (dissipative) over-voltage protection: a resistor with adequate power dissipation capability must be connected between this pin and VRECT to damp excessive voltage developing at the output of the rectifier. VGATE D1 Gate driver output for the optional VRECT discharging transistor. This pin goes high when the voltage drop across the main LDO (VVRECT – VVOUT) exceeds the programmed threshold. SCL H8 I2C bus, clock line input. A pull-up resistor to the supply rail of the host controller is required to ensure correct digital levels. SDA J8 I2C bus, data line I/O. A pull-up resistor to the supply rail of the host controller is required to ensure correct digital levels. NC C6, D6 GPIO0 H2 GPIO1 H1 GPIO2 J4 GPIO3 J3 GPIO4 J2 GPIO5 J1 INTB J7 Reserved: this pin must be connected to ground or left floating. Programmable general-purpose I/Os: the function of these pins depends on the configuration of the device. Interrupt output (active low). Programmable open-drain output used to generate an interrupt on specific events for the host controller. Also used as auxiliary control signal during OTP flash. page 5/32 STWLC68 Electrical and thermal specifications 4 Electrical and thermal specifications 4.1 Absolute maximum ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other condition above those indicated in Table 2 is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Table 2. Absolute maximum ratings Parameter Pin(s) Min. Max. AC1, AC2, COMM1, COMM2, CLAMP1 and CLAMP2 respect to ground (VSSA, VSSD and VSSP pins) -0.9 27 -0.3 5.5 BOOT1 and BOOT2 respect to ground (VSSA, VSSD and VSSP pins) -0.3 27 BOOT respect to VRECT -0.3 5.5 VRECT, VOUT and IEXT respect to ground (VSSA, VSSD and VSSP pins) -0.7 27 V1V8, NTC, VS and DFT respect to ground (VSSA, VSSD and VSSP pins) -0.3 2 V5V0, VGATE, GPIO0 through GPIO5, INTB, RSTB, SDA, SCL and BOOT_SEL respect to ground (VSSA, VSSD and VSSP pins) -0.7 5.5 Relative voltage between any ground pin (VSSA, VSSD, VSSP) -0.3 0.3 BOOT1 to AC1 BOOT2 to AC2 Pin voltage range HBM ESD susceptibility V 2000 JEDEC JS001-2012 V CDM ESD susceptibility All pins 500 JEDEC JS002-2012 Latch-Up EIA/JESD78E 4.2 Unit -200 200 mA Thermal characteristics Table 3. Thermal characteristics Symbol Parameter Conditions TA,OP(1) Operating ambient temperature -40 85 TJ,OP Operating junction temperature 0 125 RϴJA(2) Junction to ambient thermal resistance TSHDN Thermal shutdown threshold 125 TSHDN,HYST Thermal shutdown hysteresis 10 2s2p Min. Typ. 40 Max. Unit °C °C/W °C 1. TA,OP -40°C to +85°C, limits over the operating range guaranteed by design and characterization, if not otherwise specified. 2. Device mounted on a standard JESD51-5 test board DS13131 - Rev 4 page 6/32 STWLC68 Electrical characteristics 4.3 Electrical characteristics 0 °C < TA < 85 °C; VVRECT = 5 V to 10 V. Typical values are at TJ = 25 °C, if not otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test Conditions Min. Typ. Max. 3.0 3.3 Unit VRECT Under-Voltage Lock-Out upper (turn-on) threshold VRECT pin voltage, rising edge VRECT Under-Voltage Lock-Out lower (turn-off) threshold VRECT pin voltage, falling edge 2.5 VVRECT,MAX VRECT maximum operating supply voltage Voltage on VRECT pin 16 IVOUT,Q VOUT current consumption in shutdown mode RSTB low for more than 1 ms, supply voltage (5 V) applied to VOUT 400 750 RSTB high, supply voltage applied to VRECT 9.7 13 RSTB high, supply voltage applied to VOUT 9.7 13 1.8 1.81 V 5 20 mV 5 5.2 V 2 20 mV 3 3.2 V 10 mA Supply section VVRECT,UVLO IVRECT,OP IVOUT,OP Operating current consumption (not considering the programmed dummyload current) V V μA mA 1.8V supply voltage LDO linear regulator VV1V8 LDO1 output voltage IV1V8 = 5 mA LDO1 load regulation 0 mA < IV1V8 < 10 mA 1.79 5V supply voltage LDO linear regulator VV5V0 LDO2 output voltage IV5V0 = 5 mA, VVRECT = 5.1 V LDO2 load regulation 0 mA