TD351ID

TD351 Advanced IGBT/MOSFET driver Features ■ 1.7 A sink / 1.3 A source (typ) current capability ■ Active Miller clamp feature ■ Two-level turn-off with adjustable level and delay ■ Input compatible with pulse transformer or optocoupler ■ UVLO protection ■ 2 kV ESD protection SO-8 The TD351 is compatible with both pulse transformer and optocoupler signals. Applications ■ 1200 V 3-phase inverters ■ Motor control systems ■ UPS Description This device is an advanced gate driver for IGBT and power MOSFETs. Control and protection functions are included and allow the design of high reliability systems. The innovative active Miller clamp function eliminates the need for negative gate drive in most applications and allows the use of a simple bootstrap supply for the high side driver. The TD351 includes a two-level turn-off feature with adjustable level and delay. This function protects against excessive overvoltage at turn-off in case of overcurrent or short-circuit conditions. The same delay is applied at turn-on to prevent pulse width distortion. Table 1. Device summary Order codes Temperature range Package -40°C, +125°C SO-8 TD351ID Tube TD351IDT June 2011 Packaging Tape and reel Doc ID 10977 Rev 2 1/19 www.st.com 19 Contents TD351 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 Input stage ................................................ 8 5.2 Voltage reference ........................................... 8 5.3 Active Miller clamp .......................................... 8 5.4 Two level turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.5 Minimum input ON-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.6 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.7 Undervoltage protection ...................................... 9 6 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 Doc ID 10977 Rev 2 TD351 Block diagram Figure 1. TD351 block diagram 9 9+ 89/2 ,1 95() &' 9+ /92)) 9UHI 'HOD\ 9+ &RQWURO %ORFN 1 Block diagram 287 9/ &/$03 2II/HYHO 7' !-V Doc ID 10977 Rev 2 3/19 Pin connections 2 TD351 Pin connections Figure 2. Pin connections (top view)  9+  287   9/   &/$03 ,1  95()  7' &' /92)) !-V Table 2. 4/19 Pin description Pin n° Name Type Function 1 IN Analog input Input 2 VREF Analog output +5 V reference voltage 3 CD Timing capacitor Turn on/off delay 4 LVOFF Analog input Turn off level 5 CLAMP Analog output Miller clamp 6 VL Power supply Signal ground 7 OUT Analog output Gate drive output 8 VH Power supply Positive supply Doc ID 10977 Rev 2 TD351 Absolute maximum ratings 3 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit 28 V VHL Maximum supply voltage (VH - VL) Vout Voltage on OUT, CLAMP, LVOFF pins VL-0.3 to VH+0.3 V Vother Voltage on other pins (IN, CD, VREF) -0.3 to 7 V 500 mW -55 to 150 °C Maximum junction temperature 150 °C RthJA Thermal resistance junction-ambient 150 °C/W ESD Electrostatic discharge (HBM) 2 kV Value Unit UVLO to 26 V -40 to 125 °C Pd Power dissipation Tstg Storage temperature Tj Table 4. Symbol VH Toper Operating conditions Parameter Positive supply voltage vs. VL Operating free air temperature range Doc ID 10977 Rev 2 5/19 Electrical characteristics 4 TD351 Electrical characteristics TA = -20 to 125°C, VH = 16 V, unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Test condition Min Typ 0.8 1.0 Max Unit Input Vton IN turn-on threshold voltage Vtoff IN turn-off threshold voltage tonmin Iinp Minimum pulse width IN input current 100 V 4.0 4.2 V 135 220 ns 1 µA 5.15 V IN input voltage < 4.5V Voltage reference (1) Vref Voltage reference Iref Maximum output current T = 25°C 4.85 5.00 10 mA Clamp Vtclamp VCL CLAMP pin voltage threshold Clamp low voltage 2.0 Icsink = 500mA V 2.5 V Delay Vtdel Voltage threshold 2.5 Rdel Discharge resistor I=1mA Iblvoff LVOFF peak input current (sink) LVOFF = 12V Violv Offset voltage LVOFF = 12V Isink Output sink current Isrc V 500 Off Level 90 200 µA -0.3 -0.15 0 V Vout = 6V 1000 1700 mA Output source current Vout = VH-6V 750 1300 mA VOL1 Output low voltage 1 Iosink = 20mA 0.35 V VOL2 Output low voltage 2 Iosink = 500mA 2.5 V VOH1 Output high voltage 1 Iosource = 20mA VH-2.5 V VOH2 Output high voltage 2 Iosource = 500mA VH-4.0 V tr Rise time CL = 1nF, 10% to 90% 100 ns tf Fall time (2) CL = 1nF, 90% to 10% 100 ns Turn on propagation delay 10% OUT change: Rd = 4.7kΩ, no Cd Rd = 10kΩ, Cd = 220 pF 600 2.2 ns µs 550 ns Output tdon tdoff 6/19 Turn off propagation delay (2) 10% OUT change Doc ID 10977 Rev 2 1.8 2.0 TD351 Table 5. Electrical characteristics Electrical characteristics (continued) Symbol ∆tw Parameter Input to output pulse distortion Test condition Min 10% OUT change, ∆tw=Twout-Twin Typ Max Unit 50 100 ns Under voltage lockout (UVLO) UVLOH UVLO top threshold 10 11 12 V UVLOL UVLO bottom threshold 9 10 11 V 0.5 1 Vhyst UVLO hysteresis UVLOH-UVLOL V Supply current Iin Quiescent current OUT = 0V; no load 2.5 mA 1. Recommended capacitor range on VREF pin is 10 nF to 100 nF 2. 2 step turn-off disabled. Doc ID 10977 Rev 2 7/19 Functional description TD351 5 Functional description 5.1 Input stage The TD351 input is compatible with optocouplers or pulse transformers. The input is triggered by the signal edge and allows the use of low-sized, low-cost pulse transformers. Input is active low and output is driven high when input is driven low. The IN input is internally clamped at about 5 V to 7 V. When using an open collector optocoupler, the resistive pull-up resistor can be connected to either VREF or VH. Recommended pull-up resistor value with VH = 16 V is from 4.7 kΩ to 22 kΩ. When driven by a pulse transformer, the input positive and negative pulse widths at the Vton and Vtoff threshold voltages must be larger than the minimum pulse width tonmin (see Figure 6). This feature acts as a filter against invalid input pulses smaller than tonmin. 5.2 Voltage reference A voltage reference is used to create accurate timing for the turn-on delay with external resistor and capacitor. The same circuitry is also used for the two-level turn-off delay. A decoupling capacitor (10 nF to 100 nF) on the VREF pin is required to ensure good noise rejection. 5.3 Active Miller clamp The TD351 offers an alternative solution to the problem of Miller current in IGBT switching applications. Instead of driving the IGBT gate to a negative voltage to increase the safety margin, the TD351 uses a dedicated CLAMP pin to control the Miller current. When the IGBT is off, a low impedance path is established between the IGBT gate and emitter to carry the Miller current, and the voltage spike on the IGBT gate is greatly reduced. During turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage goes below 2 V (relative to VL). The clamp voltage is VL+4V max for a Miller current up to 500 mA. The clamp is disabled when the IN input is triggered again. The CLAMP function does not affect the turn-off characteristic, but only keeps the gate at low level throughout the OFF-time. The main benefit is that negative voltage can be avoided in many cases, allowing a bootstrap technique for the high side driver supply. 5.4 Two-level turn-off During turn-off, the gate voltage can be reduced to a programmable level in order to reduce the IGBT current (in the event of overcurrent). This action prevents both dangerous overvoltages across the IGBT and RBSOA problems, especially at short-circuit turn-off. The turn-off (Ta) delay is programmable through external resistor Rd and capacitor Cd for accurate timing. 8/19 Doc ID 10977 Rev 2 TD351 Functional description Ta is approximately given by (see Figure 5): T a ( µs ) = 0.7 ⋅ R d ( kΩ) ⋅ C d ( nF ) The turn-off delay (Ta) is also used to delay the input signal to prevent distortion of input pulse width. The two-level turn-off sequence can be disabled by connecting the LVOFF pin to VH and connecting the CD pin to VREF with a 4.7 kΩ resistor. 5.5 Minimum input ON-time Input signals with ON-time smaller than Ta are ignored. ON-time signals larger than Ta+2.Rdel.Cd (Rdel is the internal discharge switch resistance, Cd is the external timing capacitor) are transmitted to the output stage after the Ta delay, with minimum width distortion (∆Tw=Twout-Twin). For ON-time input signals close to Ta (between Ta and Ta+2.Rdel.Cd), the two-level duration is slightly reduced and the total output width can be smaller than the input width (see Figure 7). 5.6 Output stage The output stage is able to sink/source 1.7 A/1.3 A (typical) at 25 °C and 1.0 A/0.75 A min. over the full temperature range. This current capability is specified near the usual IGBT Miller plateau. 5.7 Undervoltage protection Undervoltage detection protects the application in the event of a low VH supply voltage (during startup or a fault situation). During undervoltage, the OUT pin is driven low (active pull-down for VH>2V, and passive pull-down for VH