TDA2006V

TDA2006 ® 12W AUDIO AMPLIFIER DESCRIPTION The TDA2006 is a monolithic integrated circuit in Pentawatt package, intended for use as a low frequency class "AB" amplifier. At ±12V, d = 10 % typically it provides 12W output power on a 4Ω load and 8W on a 8Ω . The TDA2006 provides high output current and has very low harmonic and cross-over distortion. Further the device incorporates an original (and patented) short circuit protection system comprising an arrangement for automatically limiting the dissipated power so as to keep the working point of the output transistors within their safe operating area. A conventional thermal shutdown system is also included. The TDA2006 is pin to pin equivalent to the TDA2030. ) (s TYPICAL APPLICATION CIRCUIT ) s ( ct u d o PENTAWATT r P e ORDERING NUMBERS : TDA2006V TDA2006H t e l o s b O t c u d o r P e t e l o s b O September 2003 1/12 TDA2006 SCHEMATIC DIAGRAM ) s ( ct u d o r P e ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vs Supply Voltage Vi Input Voltage Vi Differential Input Voltage Io Output Peak Current (internaly limited) ) (s t e l o s b O Value Unit ± 15 V Vs ± 12 ct V 3 A Ptot Power Dissipation at Tcase = 90 °C 20 W Tstg, Tj Storage and Junction Temperature – 40 to 150 °C u d o r P e THERMAL DATA t e l o Symbol Rth (j-c) s b O PIN CONNECTION 2/12 Parameter Thermal Resistance Junction-case Max Value Unit 3 °C/W TDA2006 ELECTRICAL CHARACTERISTICS (refer to the test circuit ; VS = ± 12V, Tamb = 25oC unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. ±6 Max. Unit ± 15 V Vs Supply Voltage Id Quiescent Drain Current Vs = ± 15V 40 80 mA Ib Input Bias Current Vs = ± 15V 0.2 3 µA VOS Input Offset Voltage Vs = ± 15V ±8 mV IOS Input Offset Current Vs = ± 15V ± 80 nA VOS Output Offset Voltage Vs = ± 15V ± 10 Output Power d = 10%, f = 1kHz RL = 4Ω RL = 8Ω Po Distortion Po = 0.1 to 8W, RL = 4Ω, f = 1kHz Po = 0.1 to 4W, RL = 8Ω, f = 1kHz Vi Input Sensitivity Po = 10W, RL = 4Ω, f = 1kHz Po = 6W, RL = 8Ω, f = 1kHz B Frequency Response (– 3dB) Po = 8W, RL = 4Ω Ri Input Resistance (pin 1) f = 1kHz Gv Voltage Gain (open loop) f = 1kHz Gv Voltage Gain (closed loop) f = 1kHz eN Input Noise Voltage iN Input Noise Current SVR ro Id Drain Current Tj Thermal Shutdown Junction Temperature t e l o P e s b O 0.5 W 0.2 0.1 % % 200 220 mV mV 20Hz to 100kHz 5 MΩ 75 dB 30.5 dB B (– 3dB) = 22Hz to 22kHz, RL = 4Ω 3 10 µV B (– 3dB) = 22Hz to 22kHz, RL = 4Ω 80 200 pA RL = 4Ω, Rg = 22kΩ, fripple = 100Hz (*) Po = 12W, RL = 4Ω Po = 8W, RL = 8Ω 29.5 mV 30 s ( t c du Supply Voltage Rejection )- r P e t e l o ct u d o 6 d 12 8 (s) ± 100 40 50 dB 850 500 mA mA 145 °C (*) Referring to Figure 15, single supply. s b O 3/12 TDA2006 Output Power versus Supply Voltage Figure 1 : Figure 2 : Distortion versus Output Power ) s ( ct Distortion versus Frequency Figure 3 : Figure 4 : u d o r P e Distortion versus Frequency t e l o ) (s s b O t c u d o r o s b O 4/12 P e let Figure 5 : Sensitivity versus Output Power Figure 6 : Sensitivity versus Output Power TDA2006 Figure 7 : Frequency Response with different values of the rolloff Capacitor C8 (see Figure 13) Figure 8 : Value of C8 versus Voltage Gain for different Bandwidths (see Figure 13) ) s ( ct Figure 9 : u d o r P e Quiescent Current versus Supply Voltage Figure 10 : Supply Voltage Rejection versus Voltage Gain t e l o ) (s s b O t c u d o r P e t e l o Figure 11 : Power Dissipation and Efficiency versus Output Power s b O Figure 12 : Maximum Power Dissipation versus Supply Voltage (sine wave operation) 5/12 TDA2006 Figure 13 : Application Circuit with Spilt Power Supply ) s ( ct u d o r P e t e l o Figure 14 : P.C. Board and Components Layout of the Circuit of Figure 13 (1:1 scale) ) (s t c u d o r P e t e l o s b O 6/12 s b O TDA2006 Figure 15 : Application Circuit with Single Power Supply ) s ( ct u d o r P e t e l o Figure 16 : P.C. Board and Components Layout of the Circuit of Figure 15 (1:1 scale) ) (s s b O t c u d o r P e t e l o s b O 7/12 TDA2006 Figure 17 : Bridge Amplifier Configuration with Split Power Supply (PO = 24W, VS = ± 12V) ) s ( ct u d o r P e PRACTICAL CONSIDERATIONS Printed Circuit Board The layout shown in Figure 14 should be adopted by the designers. If different layout are used, the ground points of input 1 and input 2 must be well decoupled from ground of the output on which a rather high current flows. ) (s s b O t c u Assembly Suggestion No electrical isolation is needed between the packTable 1 d o r P e R1 R2 R3 Recommanded Value 22 kΩ 680 Ω 22 kΩ R4 1Ω Closed Loop Gain Setting Closed Loop Gain Setting Non Inverting Input Biasing Frequency Stability R5 3 R2 Upper Frequency Cut-off C1 2.2 µF Input DC Decoupling C2 22 µF C3C4 C5C6 C7 0.1 µF 100 µF 0.22 µF 1 2πBR1 1N4001 Inverting Input DC Decoupling Supply Voltage by Pass Supply Voltage by Pass Frequency Stability Component t e l o s b O C8 D1D2 Purpose Upper Frequency Cut-off age and the heat-sink with single supply voltage configuration. Application Suggestion The recommended values of the components are the ones shown on application circuits of Figure 13. Different values can be used. The table 1 can help the designers. Larger Than Recommanded Value Increase of Gain Decrease of Gain (*) Increase of Input Impedance Danger of Oscillation at High Frequencies with Inductive Loads Poor High Frequencies Attenuation Smaller Than Recommanded Value Decrease of Gain (*) Increase of Gain Decrease of Input Impedance Danger of Oscillation Increase of Low Frequencies Cut-off Increase of Low Frequencies Cut-off Danger of Oscillation Danger of Oscillation Danger of Oscillation Lower Bandwidth To Protect the Device Against Output Voltage Spikes. (*) Closed loop gain must be higher than 24dB. 8/12 t e l o Larger Bandwidth TDA2006 SHORT CIRCUIT PROTECTION The TDA2006 has an original circuit which limits the current of the output transistors. Figure 18 shows that the maximum output current is a function of the collector emitter voltage ; hence the output transistors work within their safe operating area (Figure 19). This function can therefore be considered as being peak power limiting rather than simple current limiting. It reduces the possibility that the device gets damaged during an accidental short circuit from AC output to ground. Figure 19 : Safe Operating Area and Collector Characteristics of the Protected Power Transistor ) s ( ct u d o THERMAL SHUT DOWN The presence of a thermal limiting circuit offers the following advantages : 1) an overload on the output (even if it is permanent), or an above limit ambient temperature can be easily supported since the Tj cannot be higher than 150°C. 2) the heatsink can have a smaller factor of safety compared with that of a conventional circuit. There is no possibility of device damage due to high junction temperature. If for any reason, the junction temperature increases up to 150 °C, the thermal shutdown simply reduces the power dissipation and the current consumption. ) (s r P e Figure 20 : Output Power and Drain Current versus Case Temlperature (RL = 4Ω) t e l o s b O t c u d o r The maximum allowable power dissipation depends upon the size of the external heatsink (i.e. its thermal resistance) ; Figure 22 shows the dissipable power as a function of ambient temperature for different thermal resistances. P e s b O t e l o Figure 18 : Maximum Output Current versus Voltage VCE (sat) accross each Output Transistor Figure 21 : Output Power and Drain Current versus Case Temlperature (RL = 8Ω) 9/12 TDA2006 Figure 22 : Maximum Allowable Power Dissipation versus Ambient Temperature DIMENSION SUGGESTION The following table shows the length of the heatsink in Figure 23 for several values of Ptot and Rth. Ptot (W) Lenght of Heatsink (mm) Rth of Heatsink (°C/W) 12 60 4.2 8 40 6.2 6 30 8.3 Figure 23 : Example of Heatsink ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 10/12 s b O TDA2006 DIM. A C D D1 E E1 F F1 G G1 H2 H3 L L1 L2 L3 L4 L5 L6 L7 L9 L10 M M1 V4 V5 DIA MIN. mm TYP. 2.40 1.20 0.35 0.76 0.80 1.00 3.20 6.60 3.40 6.80 10.05 17.55 15.55 21.2 22.3 17.85 15.75 21.4 22.5 2.60 15.10 6.00 2.10 4.30 4.23 3.75 4.5 4.0 3.65 MAX. MIN. 4.80 1.37 2.80 0.094 1.35 0.047 0.55 0.014 1.19 0.030 1.05 0.031 1.40 0.039 3.60 0.126 7.00 0.260 10.40 10.40 0.395 18.15 0.691 15.95 0.612 21.6 0.831 22.7 0.878 1.29 3.00 0.102 15.80 0.594 6.60 0.236 2.70 0.083 4.80 0.170 4.75 0.167 4.25 0.148 40˚ (Typ.) 90˚ (Typ.) 3.85 0.143 inch TYP. 0.134 0.267 0.703 0.620 0.843 0.886 0.178 0.157 t e l o u d o r P e t e l o s b O Pentawatt V E M1 M D D1 L5 O ) s ( ct L1 C bs Weight: 2.00gr t c u od A OUTLINE AND MECHANICAL DATA ) (s 0.151 L r P e MAX. 0.188 0.054 0.11 0.053 0.022 0.047 0.041 0.055 0.142 0.275 0.41 0.409 0.715 0.628 0.850 0.894 0.051 0.118 0.622 0.260 0.106 0.189 0.187 0.187 V5 L2 H2 L3 F E E1 V4 H3 G G1 Dia. F F1 L9 L4 L10 L7 L6 H2 V4 RESIN BETWEEN LEADS PENTVME 0015981 F 11/12 TDA2006 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. 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