TDA7294S

TDA7294S 100V - 100W DMOS AUDIO AMPLIFIER WITH MUTE/ST-BY 1 ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2 Features Figure 1. Package VERY HIGH OPERATING VOLTAGE RANGE (± 45V) MULTIPOWER BCD TECHNOLOGY DMOS POWER STAGE HIGH OUTPUT POWER (100W @ THD = 10%, RL = 8Ω, VS = ±40V (MUSIC POWER) MUTING/STAND-BY FUNCTIONS NO SWITCH ON/OFF NOISE VERY LOW DISTORTION VERY LOW NOISE SHORT CIRCUIT PROTECTED (WITH NO INPUT SIGNAL APPLIED) THERMAL SHUTDOWN CLIP DETECTOR MODULARITY (MORE DEVICES CAN BE EASILY CONNECTED IN PARALLEL TO DRIVE VERY LOW IMPEDANCES) Multiwatt15 (Vertical) Table 1. Order Codes Package TDA7294S Multiwatt15 (Vertical) c u d ) s t( class AB amplifier in Hi-Fi field applications (Home Stereo, self powered loudspeakers, Top class TV). Thanks to the wide voltage range and to the high out current capability it is able to supply the highest power into both 4Ω and 8Ω loads. The built in muting function with turn on delay simplifies the remote operation avoiding switching on-off noises. e t le o r P Parallel mode is made possible by connecting more device through of pin11. High output power can be delivered to very low impedance loads, so optimizing the thermal dissipation of the system. o s b O - Description The TDA7294S is a monolithic integrated circuit in Multiwatt15 package, intended for use as audio ) s ( ct Part Number Figure 2. Typical Application and Test Circuit +Vs C7 100nF u d o C6 1000µF R3 22K C2 22µF r P e t e l o s b O VMUTE R2 680Ω C1 470nF IN- 2 IN+ 3 BUFFER DRIVER +Vs +PWVs 11 7 13 - R5 10K STBY BOOT LOADER C5 22µF 6 10 5 THERMAL SHUTDOWN MUTE VSTBY 12 4 (**) MUTE OUT + R1 22K SGND 14 9 S/C PROTECTION (*) BOOTSTRAP CLIP DET VCLIP STBY R4 22K C3 10µF C4 10µF 1 8 15 STBY-GND -Vs -PWVs C9 100nF C8 1000µF D97AU805A (*) see Application note (**) for SLAVE function February 2005 -Vs Rev. 2 1/16 TDA7294S Figure 3. Pin Connection (Top view) 15 -VS (POWER) 14 OUT 13 +VS (POWER) 12 BOOTSTRAP LOADER 11 BUFFER DRIVER 10 MUTE 9 STAND-BY 8 -VS (SIGNAL) 7 +VS (SIGNAL) 6 BOOTSTRAP 5 CLIP AND SHORT CIRCUIT DETECTOR 4 SIGNAL GROUND 3 NON INVERTING INPUT 2 INVERTING INPUT 1 STAND-BY GND TAB CONNECTED TO PIN 8 c u d D97AU806 e t le Table 2. Quick Reference Data Symbol so Parameter Test Condition Supply Voltage Operating VS GLOOP Ptot Closed Loop Gain (s) Output Power u d o ct SVR Supply Voltage Rejection b O - ) s t( o r P Min. Typ. Max. Unit ±12 ±45 V 26 45 dB VS = ± 40V; RL = 8Ω; THD = 10% 100 W VS = ± 40V; RL = 8Ω; THD = 10% 100 W 75 dB r P e t e l o s b O Table 3. Thermal Data Symbol Rth j-case 2/16 Parameter Thermal Resistance Junction-case Typ Max Unit 1 1.5 °C/W TDA7294S Table 4. Absolute Maximum Ratings Symbol Parameter Value Unit VS Supply Voltage (No Signal) ±50 V V1 VSTAND-BY GND Voltage Referred to -VS (pin 8) 90 V V2 Input Voltage (inverting) Referred to -VS 90 V V2 - V3 Maximum Differential Inputs ±30 V V3 Input Voltage (non inverting) Referred to -VS 90 V V4 Signal GND Voltage Referred to -VS 90 V V5 Clip Detector Voltage Referred to -VS 100 V V6 Bootstrap Voltage Referred to -VS 100 V V9 Stand-by Voltage Referred to -VS 100 V V10 Mute Voltage Referred to -VS 100 V V11 Buffer Voltage Referred to -VS 100 V V12 Bootstrap Loader Voltage Referred to -VS 90 V Output Peak Current 10 Ptot Power Dissipation Tcase = 70°C 50 Top Operating Ambient Temperature Range IO Tstg, Tj c u d 0 to 70 Storage and Junction Temperature ) s t( A 150 o r P W °C °C Table 5. Electrical Characteristcs (Refer to the Test Circuit VS = ±35V, RL = 8Ω, GV = 30dB; Rg = 50Ω; Tamb = 25°C, f = 1kHz; unless otherwise specified). Symbol Parameter VS Operating Supply Range Iq Quiescent Current Ib Input Bias Current ) s ( ct Input Offset Voltage IOS Input Offset Current PO RMS Continuous Output Power u d o r P e d d = 0.5%: VS = ± 35V, RL = 8Ω VS = ± 32V, RL = 6Ω VS = ± 28V, RL = 4Ω Music Power (RMS) (*) ∆t = 1s d = 0.5%: VS = ± 40V, RL = 8Ω VS = ± 35V, RL = 6Ω VS = ± 30V, RL = 4Ω (***) Total Harmonic Distortion (**) PO = 5W; f = 1kHz PO = 0.1 to 20W; f = 20Hz to 20kHz t e l o s b O o s b O Test Condition VOS e t le Min. 20 60 60 60 Overcurrent Protection Threshold SR Slew Rate GV Open Loop Voltage Gain GV Closed Loop Voltage Gain VS ≤ ± 40V 30 Max. Unit ±45 V 65 mA 500 nA ±10 mV ±100 nA 70 70 70 W W W 100 100 100 W W W 0.005 VS = ± 28V, RL = 4Ω: PO = 5W; f = 1kHz PO = 0.1 to 20W; f = 20Hz to 20kHz IMAX Typ. ±12 0.1 % % 0.1 % % 0.01 6.5 7 A 10 V/µs 80 26 30 dB 45 dB 3/16 TDA7294S Table 5. Electrical Characteristcs (continued) (Refer to the Test Circuit VS = ±35V, RL = 8Ω, GV = 30dB; Rg = 50Ω; Tamb = 25°C, f = 1kHz; unless otherwise specified). Symbol eN Parameter Test Condition Total Input Noise fL, fH Min. A = curve f = 20Hz to 20kHz Frequency Response (-3dB) SVR 5 µV 20Hz to 20kHz f = 100Hz; Vripple = 0.5Vrms 60 Thermal Shutdown TS Unit µV 2 PO = 1W Supply Voltage Rejection Max. 1 Input Resistance Ri Typ. 100 kΩ 75 dB 150 °C STAND-BY FUNCTION (Ref: -VS or GND) VST on Stand-by on Threshold VST off Stand-by off Threshold 3.5 Stand-by Attenuation 70 ATTst-by Iq st-by 1.5 Quiescent Current @ Stand-by V 90 1 dB 3 MUTE FUNCTION (Ref: -VS or GND) VMon Mute on Threshold VMoff Mute off Threshold ATTmute 3.5 r P e t le 60 CLIP DETECTOR Duty uc ) s t( 1.5 Mute Attenuation THD = 1%; RL = 10KΩ to 5V Duty Cycle ( pin 5) THD = 10%; RL = 10KΩ to 5V ICLEAK so PO = 50W b O - 30 V mA V od dB 10 % 80 40 V 50 % 3 µA Note (*): MUSIC POWER CONCEPT MUSIC POWER is the maximal power which the amplifier is capable of producing across the rated load resistance (regardless of non linearity) 1 sec after the application of a sinusoidal input signal of frequency 1KHz. Note (**): Tested with optimized Application Board (see fig. 3) Note (***): Limited by the max. allowable current. Note (***): For supply voltage ≥35V, The device could be demaged in short circuit conditions when the input signal is applied ) s ( ct u d o r P e t e l o s b O 4/16 TDA7294S Figure 4. Typical Application P.C. Board and Component Layout (scale 1:1) c u d e t le 3 ) s t( o r P o s b O - Application Suggestions (see Test and Application Circuits of the Fig. 2) The recommended values of the external components are those shown on the application circuit of Figure 2. Different values can be used; the following table can help the designer. ) s ( ct Table 6. Application Suggestions COMPONENTS SUGGESTED VALUE R1 (*) 22k LARGER THAN SUGGESTED SMALLER THAN SUGGESTED INPUT RESISTANCE INCREASE INPUT IMPEDANCE DECREASE INPUT IMPEDANCE CLOSED LOOP GAIN SET TO 30dB (**) DECREASE OF GAIN INCREASE OF GAIN INCREASE OF GAIN DECREASE OF GAIN 22k ST-BY TIME CONSTANT LARGER ST-BY ON/OFF TIME SMALLER ST-BY ON/ ON/OFF TIME; POP NOISE R5 10k MUTE TIME CONSTANT LARGER MUTE ON/OFF TIME SMALLER MUTE ON/OFF TIME C1 0.47µF INPUT DC DECOUPLING HIGHER LOW FREQUENCY CUTOFF C2 22µF FEEDBACK DC DECOUPLING HIGHER LOW FREQUENCY CUTOFF C3 10µF MUTE TIME CONSTANT r P e R2 R3 (*) t e l o R4 s b O u d o 680Ω 22k PURPOSE LARGER MUTE ON/OFF TIME SMALLER MUTE ON/OFF TIME 5/16 TDA7294S Table 6. Application Suggestions (continued) COMPONENTS SUGGESTED VALUE C4 PURPOSE LARGER THAN SUGGESTED SMALLER THAN SUGGESTED 10µF ST-BY TIME CONSTANT LARGER ST-BY ON/OFF TIME SMALLER ST-BY ON/ ON/OFF TIME; POP NOISE C5 22µFXN (***) BOOTSTRAPPING C6, C8 1000µF SUPPLY VOLTAGE BYPASS C7, C9 0.1µF SUPPLY VOLTAGE BYPASS SIGNAL DEGRADATION AT LOW FREQUENCY DANGER OF OSCILLATION (*) R1 = R3 for pop optimization (**) Closed Loop Gain has to be ≥ 26dB (***) Multiply this value for the number of modular part connected Figure 5. Slave function: pin 4 (Ref to pin 8 -VS) -VS +3V -VS +1V -VS Note: ) s ( ct c u d MASTER UNDEFINED e t le ) s t( o r P o s b O SLAVE D98AU821 If in the application, the speakers are connected via long wires, it is a good rule to add between the output and GND, a Boucherot Cell, in order to avoid dangerous spurious oscillations when the speakers terminal are shorted. The suggested Boucherot Resistor is 3.9Ω/2W and the capacitor is 1µF. 4 Introduction u d o r P e In consumer electronics, an increasing demand has arisen for very high power monolithic audio amplifiers able to match, with a low cost, the performance obtained from the best discrete designs. t e l o The task of realizing this linear integrated circuit in conventional bipolar technology is made extremely difficult by the occurence of 2nd breakdown phoenomenon. It limits the safe operating area (SOA) of the power devices, and, as a consequence, the maximum attainable output power, especially in presence of highly reactive loads. Moreover, full exploitation of the SOA translates into a substantial increase in circuit and layout complexity due to the need of sophisticated protection circuits. s b O To overcome these substantial drawbacks, the use of power MOS devices, which are immune from secondary breakdown is highly desirable. The device described has therefore been developed in a mixed bipolar-MOS high voltage technology called BCDII 100. 4.1 Output Stage The main design task in developping a power operational amplifier, independently of the technology used, is that of realization of the output stage. The solution shown as a principle shematic by Fig.5 represents the DMOS unity - gain output buffer of the TDA7294S. 6/16 TDA7294S This large-signal, high-power buffer must be capable of handling extremely high current and voltage levels while maintaining acceptably low harmonic distortion and good behaviour over frequency response; moreover, an accurate control of quiescent current is required. A local linearizing feedback, provided by differential amplifier A, is used to fullfil the above requirements, allowing a simple and effective quiescent current setting. Proper biasing of the power output transistors alone is however not enough to guarantee the absence of crossover distortion. While a linearization of the DC transfer characteristic of the stage is obtained, the dynamic be-haviour of the system must be taken into account. A significant aid in keeping the distortion contributed by the final stage as low as possible is provided by the compensation scheme, which exploits the direct connection of the Miller capacitor at the amplifier’s output to introduce a local AC feedback path enclosing the output stage itself. 4.2 Protections In designing a power IC, particular attention must be reserved to the circuits devoted to protection of the device from short circuit or overload conditions. Due to the absence of the 2nd breakdown phenomenon, the SOA of the power DMOS transistors is delimited only by a maximum dissipation curve dependent on the duration of the applied stimulus. c u d ) s t( In order to fully exploit the capabilities of the power transistors, the protection scheme implemented in this device combines a conventional SOA protection circuit with a novel local temperature sensing technique which " dynamically" controls the maximum dissipation. Figure 6. Principle Schematic of a DMOS unity-gain buffer. e t le +VDD I ref o s b O M1 MR c u d Vi o r P e (t s) + - A o r P Vo M2 -VSS t e l o s b O 7/16 TDA7294S Figure 7. Turn ON/OFF Suggested Sequence +Vs (V) +40 -40 -Vs VIN (mV) VST-BY PIN #9 (V) VMUTE PIN #10 (V) c u d 5V e t le 5V ) s ( ct IQ (mA) u d o VOUT (V) o r P o s b O - OFF r P e ST-BY t e l o PLAY ST-BY MUTE MUTE D98AU817 s b O Figure 8. Single Signal ST-BY/MUTE Control Circuit MUTE MUTE/ ST-BY STBY 20K 10K 30K 1N4148 10µF 10µF D93AU014 8/16 OFF ) s t( TDA7294S In addition to the overload protection described above, the device features a thermal shutdown circuit which initially puts the device into a muting state (@ Tj = 150°C) and then into stand-by (@ Tj = 160°C). Full protection against electrostatic discharges on every pin is included. 4.3 Other Features The device is provided with both stand-by and mute functions, independently driven by two CMOS logic compatible input pins. The circuits dedicated to the switching on and off of the amplifier have been carefully optimized to avoid any kind of uncontrolled audible transient at the output. The sequence that we recommend during the ON/OFF transients is shown by Figure 7. The application of figure 5 shows the possibility of using only one command for both st-by and mute functions. On both the pins, the maximum applicable range corresponds to the operating supply voltage. 5 Application Information ) s t( 5.1 HIGH-EFFICIENCY Constraints of implementing high power solutions are the power dissipation and the size of the power supply. These are both due to the low efficiency of conventional AB class amplifier approaches. c u d Here below (figure 9) is described a circuit proposal for a high efficiency amplifier which can be adopted for both HI-FI and CAR-RADIO applications. o r P The TDA7294S is a monolithic MOS power amplifier which can be operated at 90V supply voltage (100V with no signal applied) while delivering output currents up to ±6.5 A. e t le This allows the use of this device as a very high power amplifier (up to 100W as peak power with T.H.D.=10 % and Rl = 4 Ohm); the only drawback is the power dissipation, hardly manageable in the above power range. o s b O - The typical junction-to-case thermal resistance of the TDA7294S is 1 °C/W (max= 1.5 °C/W). To avoid that, in worst case conditions, the chip temperature exceedes 150°C, the thermal resistance of the heatsink must be 0.038 °C/W (@ max ambient temperature of 50 °C). ) s ( ct As the above value is pratically unreachable; a high efficiency system is needed in those cases where the continuous RMS output power is higher than 50-60 W. The TDA7294S was designed to work also in higher efficiency way. u d o For this reason there are four power supply pins: two intended for the signal part and two for the power part. r P e T1 and T2 are two power transistors that only operate when the output power reaches a certain threshold (e.g. 20 W). If the output power increases, these transistors are switched on during the portion of the signal where more output voltage swing is needed, thus "bootstrapping" the power supply pins (#13 and #15). t e l o The current generators formed by T4, T7, zener diodes Z1, Z2 and resistors R7,R8 define the minimum drop across the power MOS transistors of the TDA7294S. L1, L2, L3 and the snubbers C9, R1 and C10, R2 stabilize the loops formed by the "bootstrap" circuits and the output stage of the TDA7294S. s b O By considering again a maximum average output power (music signal) of 20W, in case of the high efficiency application, the thermal resistance value needed from the heatsink is 2.2°C/W (Vs = ±45V and Rl= 8Ohm). All components (TDA7294S and power transistors T1 and T2) can be placed on a 1.5°C/W heatsink, with the power darlingtons electrically insulated from the heatsink. Since the total power dissipation is less than that of a usual class AB amplifier, additional cost savings can be obtained while optimizing the power supply, even with a high heatsink . 9/16 TDA7294S 5.2 BRIDGE APPLICATION Another application suggestion is the BRIDGE configuration, where two TDA7294S are used. In this application, the value of the load must not be lower than 8Ohm for dissipation and current capability reasons. A suitable field of application includes HI-FI/TV subwoofers realizations. The main advantages offered by this solution are: – High power performances with limited supply voltage level. – Considerably high output power even with high load values (i.e. 16 Ohm). With Rl= 8 Ohm, Vs = ±25V the maximum output power obtainable is 150W, while with Rl=16 Ohm, Vs = ±40V the maximum Pout is 200W (Music Power). 6 APPLICATION NOTE: (ref. fig. 10) 6.1 Modular Application (more Devices in Parallel) The use of the modular application lets very high power be delivered to very low impedance loads. The modular application implies one device to act as a master and the others as slaves. ) s t( The slave power stages are driven by the master device and work in parallel all together, while the input and the gain stages of the slave device are disabled, the figure below shows the connections required to configure two devices to work together. ■ ■ ■ ■ ■ ■ c u d The master chip connections are the same as the normal single ones. The outputs can be connected together without the need of any ballast resistance. The slave SGND pin must be tied to the negative supply. The slave ST-BY pin must be connected to ST-BY pin. The bootstrap lines must be connected together and the bootstrap capacitor must be increased: for N devices the boostrap capacitor must be 22µF times N. The slave Mute and IN-pins must be grounded. e t le o r P o s b O - 6.2 THE BOOTSTRAP CAPACITOR For compatibility purpose with the previous devices of the family, the boostrap capacitor can be connected both between the bootstrap pin (6) and the output pin (14) or between the boostrap pin (6) and the bootstrap loader pin (12). ) s ( ct When the bootcap is connected between pin 6 and 14, the maximum supply voltage in presence of output signal is limited to 80V, due the bootstrap capacitor overvoltage. u d o When the bootcap is connected between pins 6 and 12 the maximum supply voltage extend to the full voltage that the technology can stand: 100V. This is accomplished by the clamp introduced at the bootstrap loader pin (12): this pin follows the output voltage up to 100V and remains clamped at 100V. This feature lets the output voltage swing up to a gate-source voltage from the positive supply (VS -3 to 6V) r P e t e l o s b O 10/16 TDA7294S Figure 9. High Efficiency Application Circuit +50V D6 1N4001 T3 BC394 T1 BDX53A R4 270 D1 BYW98100 +25V T4 BC393 R17 270 L1 1µH D3 1N4148 C12 330nF R20 20K C1 1000µF 63V C3 100nF C5 1000µF 35V C7 100nF R22 10K C9 330nF IN 3 13 R16 13K C2 1000µF 63V C4 100nF C6 1000µF 35V R2 2 C10 330nF 6 R13 20K R14 30K D5 1N4148 1 R15 10K 10 C11 22µF R7 3.3K L3 5µH C16 1.8nF OUT R18 270 C15 22µF R8 3.3K 12 8 15 Z2 3.9V C14 10µF D2 BYW98100 L2 1µH D4 1N4148 T2 BDX54A D7 1N4001 -50V e t le c u d T7 BC394 R19 270 -25V R9 270 o r P T6 BC393 R10 270 Pot C17 1.8nF ) s t( T8 BC394 R11 20K D97AU807C o s b O - Figure 10. PCB and Component Layout of the fig. 9 ) s ( ct R6 20K 14 9 R23 10K C8 100nF R3 680 2 C13 10µF ST-BY R21 20K 7 4 PLAY GND T5 BC393 Z1 3.9V R12 13K R1 2 R5 270 u d o r P e t e l o s b O 11/16 TDA7294S Figure 11. PCB and Component Layout of the fig. 9 c u d e t le Figure 12. Modular Application Circuit so +Vs C7 100nF R3 22K MASTER R2 680Ω C1 470nF R5 10K r P e O IN+ 3 SGND 4 MUTE 10 STBY R4 22K bs 2 od VSTBY t e l o IN- 9 C4 10µF - (s) + 13 14 OUT 12 BOOT LOADER 6 MUTE THERMAL SHUTDOWN STBY S/C PROTECTION 1 8 15 STBY-GND -Vs -PWVs C9 100nF C3 10µF 5 C10 100nF R7 2Ω C5 47µF BOOTSTRAP CLIP DET C8 1000µF -Vs +Vs C7 100nF C6 1000µF BUFFER DRIVER +Vs IN- 2 IN+ 3 7 +PWVs 13 11 - SGND 4 MUTE 10 STBY 14 OUT 12 BOOT LOADER + SLAVE 9 6 MUTE THERMAL SHUTDOWN STBY S/C PROTECTION 1 8 15 STBY-GND -Vs -PWVs C9 100nF C8 1000µF -Vs 12/16 C6 1000µF +PWVs 11 7 t c u R1 22K VMUTE b O BUFFER DRIVER +Vs C2 22µF o r P 5 BOOTSTRAP D97AU808C ) s t( TDA7294S Figure 13. Modular Application P.C. Board and Component Layout (Component SIDE) c u d e t le ) s t( o r P o s b O - Figure 14. Modular Application P.C. Board and Component Layout (Solder SIDE) ) s ( ct u d o r P e t e l o s b O 13/16 TDA7294S 7 Package Information Figure 15. Multiwatt15 (Vertical) Mechanical Data & Package Dimensions DIM. mm MIN. inch TYP. MAX. MIN. TYP. A5 MAX. 0.197 B 2.65 C 1.6 D OUTLINE AND MECHANICAL DATA 0.104 0.063 1 0.039 E 0.49 0.55 0.019 0.022 F 0.66 0.75 0.026 0.030 G 1.02 1.27 1.52 0.040 0.050 0.060 G1 17.53 17.78 18.03 0.690 0.700 0.710 H1 19.6 0.772 H2 20.2 0.795 L 21.9 22.2 22.5 0.862 0.874 0.886 L1 21.7 22.1 22.5 0.854 0.87 0.886 L2 17.65 18.1 0.695 L3 17.25 17.5 17.75 0.679 0.689 0.699 L4 10.3 10.7 10.9 0.406 0.421 0.429 0.191 c u d 0.713 L7 2.65 2.9 0.104 M 4.25 4.55 4.85 0.167 0.179 0.114 M1 4.73 5.08 5.43 0.186 0.200 S 1.9 2.6 0.075 0.102 S1 1.9 2.6 0.075 0.102 Dia1 3.65 3.85 0.144 0.152 e t le 0.214 ) s ( ct ) s t( o r P Multiwatt15 (Vertical) o s b O - u d o r P e t e l o s b O 0016036 J 14/16 TDA7294S 8 Revision History Table 7. Revision History Date Revision Description of Changes January 2003 1 First Issue in EDOCS (migrated from ST-Press DMS). February 2005 2 Added “Clip Detector Electrical Characteristics” in the Table 5 (page 6). c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 15/16 TDA7294S c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. s b O The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 16/16