TDA7303TR

TDA7303 Digital controlled stereo audio processor with loudness Features ■ Input multiplexer: – 3 stereo inputs – Selectable input gain for optimal adaptation to different sources ■ Volume control in 1.25 dB steps ■ Loudness function ■ Treble and bass controL ■ Four speaker attenuators: – 4 independent speakers control in 1.25d B steps for balance and fader facilities – Independent mute function ■ SO-28 All functions programmable via serial I2C bus Description The TDA7303 is a volume, tone (bass and treble) balance (left/right) and fader (front/rear) processor for quality audio applications in car radio, Hi-Fi and portable systems. Table 1. Selectable input gain and external loudness function are provided. Control is accomplished by serial I2C bus microprocessor interface. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used bipolar/CMOS technology, low distortion, low noise and low DC stepping are obtained. Device summary Order code Package Packing TDA7303 SO-28 Tray TDA7303TR SO-28 Tape and reel September 2013 Rev 4 1/20 1 Contents TDA7303 Contents 1 2 3 4 Block, test and pin diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 Data bytes (detailed description) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 TDA7303 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Speaker attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Audio switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bass and treble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3/20 List of figures TDA7303 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. 4/20 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Loudness vs. volume attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Loudness vs. frequency (CLOUD = 100 nF) vs. volume attenuation . . . . . . . . . . . . . . . . . 10 Loudness vs. external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Noise vs. volume/gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Signal to noise ratio vs. volume setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Distortion and noise vs. frequency (VIN = 1 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Distortion and noise vs. frequency (VIN = 250 mV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Distortion vs. load resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Channel separation (L Æ R) vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Input separation (L1 Æ L2, L3) vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Supply voltage rejection vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output clipping level vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Quiescent current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Supply current vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bass resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical tone response (with the external components indicated in the test circuit) . . . . . . 12 Data validity on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timing diagram of S-bus and I2C bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Acknowledge on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SO-28 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 R3 R2 R1 C4 C5 C6 VS 11 10 2 AGND 3 SUPPLY R1 R2 OUT(R) 22μF C7 7 CREF 1 INPUT SELECTOR + GAIN C8 2.2μF 6 IN(R) 8 21 100nF C10 100nF C12 LOUD(R) VOL + LOUD TREBLE TREBLE(L) 5.6K R1 BOUT(R) 20 RB BASS 100nF C13 BIN(R) 5 2.7nF C16 TREBLE(R) TREBLE SERIAL BUS DECODER + LATCHES BASS 4 SPKR ATT MUTE D98AU888 SPKR ATT MUTE SPKR ATT MUTE MUTE SPKR ATT 22 24 26 27 28 23 25 OUT RIGHT REAR OUT RIGHT FRONT DIGGND SDA SCL OUT LEFT REAR OUT LEFT FRONT BUS Block diagram R3 L3 VOL + LOUD 18 RB BOUT(L) 19 1.1 3x 2.2μF 13 L3 C3 L2 12 IN(L) 100nF C15 BIN(L) C17 2.7nF Block, test and pin diagrams 9 14 L2 C2 L1 16 R2 1 RIGHT INPUTS LEFT INPUTS 15 3x 2.2μF C1 L1 17 5.6K C11 100nF 100nF C14 LOUD(L) Figure 1. OUT(L) C9 2.2μF TDA7303 Block, test and pin diagrams Block diagram 5/20 Block, test and pin diagrams 1.2 Test circuit Figure 2. 1.3 Pin connection Figure 3. 6/20 Test circuit Pin connection (top view) TDA7303 TDA7303 Electrical specifications 2 Electrical specifications 2.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol VS 2.2 Parameter Value Unit 10.0 V -40 to 85 °C -55 to +150 °C Min. Typ. Max. Unit 9 10 V Operating supply voltage Tamb Ambient temperature Tstg Storage temperature range Quick reference data Table 3. Quick reference data Symbol Parameter VS Supply voltage 6 VCL Max. input signal handling 2 THD Total harmonic distortion V = 1 Vrms; f = 1 kHz 0.01 % S/N Signal to noise ratio 106 dB SC Channel separation f = 1 kHz 103 dB Volume control 1.25d B step -78.75 0 dB -14 +14 dB -38.75 0 dB 0 11.25 dB Bass and treble control 2 dB step Fader and balance control 1.25 dB step Input gain 3.75 dB step1.25 dB step Mute attenuation 2.3 Vrms 100 dB Thermal data Table 4. Symbol Rth j-pins Thermal data Parameter Thermal resistance junction to pins Max. Value Unit 85 °C/W 7/20 Electrical specifications TDA7303 2.4 Electrical characteristics Table 5. Electrical characteristics (Tamb = 25 °C, VS = 9 V, RL = 10 k, RG = 600 , all control flat (G = 0), f = 1 kHz unless otherwise specified) Symbol Parameter Test condition Min. Typ. Max. Unit 6 9 10 V 8 11 mA Supply VS Supply voltage IS Supply current SVR Ripple rejection 60 80 dB 50 k 2 2.5 Vrms 80 100 dB Input selectors RII Input resistance VCL Clipping level Input 1, 2, 3, 4 (2) SIN Input separation RL Output load resistance pin 7, 17 2 k GINmin Min. input gain GINmax Max. input gain 11.25 dB GSTEP Step resolution 3.75 dB 2 µV 33 k eIN Input noise -1 G = 11.25 dB 0 1 dB Volume control RIN Input resistance CRANGE Control range 70 75 80 dB AVMIN Min. attenuation -1 0 1 dB AVMAX Max. attenuation 70 75 80 dB ASTEP Step resolution 0.5 1.25 1.75 dB -1.25 0 1.25 dB 2 dB 2 dB EA Attenuation set error ET Tracking error AV = 0 to -20 dB AV = -20 to -60 dB -3 Speaker attenuators Crange Control range 35 37.5 40 dB SSTEP Step resolution 0.5 1.25 1.75 dB 1.5 dB EA AMUTE Attenuation set error Output mute attenuation 80 100 dB ±12 ±14 ±16 dB 1 2 3 dB Bass control(1) Gb BSTEP 8/20 Control range Step resolution Max. Boost/cut TDA7303 Electrical specifications Table 5. Electrical characteristics (continued) (Tamb = 25 °C, VS = 9 V, RL = 10 k, RG = 600 , all control flat (G = 0), f = 1 kHz unless otherwise specified) Symbol RB Parameter Test condition Min. Internal feedback resistance Typ. Max. 44 Unit k Treble control (1) Gt TSTEP Control range Max. Boost/cut Step Resolution ±13 ±14 ±15 dB 1 2 3 dB 2 2.5 Audio outputs VOCL Clipping level RL Output load resistance CL Output load capacitance ROUT Output resistance VOUT DC voltage level d = 0.3 % Vrms 2 k 10  75 4.2 4.5 nF 4.8 V General eNO Output noise(2) BW = 20-20 kHz, flat output muted all gains = 0 dB 2.5 5 µV µV 3 µV all gains = 0 dB; VO = 1 Vrms 106 dB AV = 0; VIN = 1 Vrms 0.01 % AV = -20 dB, VIN = 1 Vrms 0.09 AV = -20 dB, VIN = 0.3 Vrms 0.04 % 103 dB A curve all gains = 0 dB S/N d Sc Signal to noise ratio Distortion Channel separation left/right Total tracking error 80 0.3 % AV = 0 to -20 dB 0 1 dB -20 to -60 dB 0 2 dB 1 V Bus inputs VIL Input low voltage VIH Input high voltage 3 IIN Input current -5 VO Output voltage SDA acknowledge IO = 1.6 mA V +5 µA 0.4 V 1. Bass and treble response see attached diagram (Figure 19). The center frequency and quality of the resonance behavior can be chosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network 2. The selected input is grounded through the 2.2 µF capacitor. 9/20 Electrical specifications TDA7303 2.5 Electrical characteristics curves Figure 4. Loudness vs. volume attenuation Figure 5. Loudness vs. frequency (CLOUD = 100 nF) vs. volume attenuation Figure 6. Loudness vs. external capacitors Figure 7. Noise vs. volume/gain setting Figure 8. Signal to noise ratio vs. volume setting Figure 9. Distortion and noise vs. frequency (VIN = 1 V) 10/20 TDA7303 Electrical specifications Figure 10. Distortion and noise vs. frequency (VIN = 250 mV) Figure 11. Distortion vs. load resistance Figure 12. Channel separation (L  R) vs. frequency Figure 13. Input separation (L1  L2, L3) vs. frequency Figure 14. Supply voltage rejection vs. frequency Figure 15. Output clipping level vs. supply voltage 11/20 Electrical specifications TDA7303 Figure 16. Quiescent current vs. supply voltage Figure 17. Supply current vs. temperature Figure 18. Bass resistance vs. temperature Figure 19. Typical tone response (with the external components indicated in the test circuit) 12/20 I2C bus interface TDA7303 3 I2C bus interface Data transmission from microprocessor to the TDA7303 and viceversa takes place through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data validity As shown in Figure 20, the data on the SDA line must be stable during the high period of the clock. The high and low state of the data line can only change when the clock signal on the SCL line is lOW. 3.2 Start and stop conditions As shown in Figure 21 a start condition is a high to low transition of the SDA line while SCL is high. The stop condition is a low to high transition of the SDA line while SCL is high. 3.3 Byte format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 22). The peripheral (audioprocessor) that acknowledges has to pull-down (low) the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the high level during the ninth clock pulse time. In this case the master transmitter can generate the stop information in order to abort the transfer. 3.5 Transmission without acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misreading and decreases the noise immunity. 13/20 I2C bus interface TDA7303 Figure 20. Data validity on the I2C bus SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 21. Timing diagram of S-bus and I2C bus SCL I2CBUS SDA D99AU1032 START STOP Figure 22. Acknowledge on the I2C bus SCL 1 2 3 7 8 9 SDA MSB START Patent note: 14/20 D99AU1033 ACKNOWLEDGMENT FROM RECEIVER Purchase of I2C Components of STMicrolectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. TDA7303 Software specification 4 Software specification 4.1 Interface protocol The interface protocol comprises: ● A start condition (s) ● A chip address byte, containing the TDA7303 address (the 8th bit of the byte must be 0). The TDA7303 must always acknowledge at the end of each transmitted byte. ● A sequence of data (N-bytes + acknowledge) ● A stop condition (P) Figure 23. Interface protocol ACK = Acknowledge S = Start P = Stop Max. clock speed 400 kbits/s 4.2 Subaddress (receive mode) Table 6. Chip address MSB 1 Table 7. LSB 0 0 0 1 0 0 Data bytes MSB 0 0 0 B2 LSB Function Volume control B1 B0 A2 A1 A0 1 1 0 B1 B0 A2 A1 A0 Speaker ATT LR 1 1 1 B1 B0 A2 A1 A0 Speaker ATT RR 1 0 0 B1 B0 A2 A1 A0 Speaker ATT LF 1 0 1 B1 B0 A2 A1 A0 Speaker ATT RF 0 1 0 G1 G0 S2 S1 S0 Audio switch 0 1 1 0 C3 C2 C1 C0 Bass control 0 1 1 1 C3 C2 C1 C0 Treble control Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Gx = 3.75dB steps 15/20 Software specification 4.3 TDA7303 Data bytes (detailed description) Table 8. Volume MSB 0 0 B2 B1 B0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 LSB Function A0 0 1 0 1 0 1 0 1 Volume 1.25 dB steps 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 Volume 10 dB steps 0 -10 -20 -30 -40 -50 -60 -70 For example a volume of -45 dB is given by: 0 0 1 0 0 1 0 0 Table 9. Speaker attenuators MSB 1 1 1 1 0 0 1 1 0 1 0 1 B1 B1 B1 B1 B0 B0 B0 B0 0 0 1 1 1 0 1 0 1 1 LSB Function A2 A2 A2 A2 0 0 0 0 1 1 1 1 A1 A1 A1 A1 0 0 1 1 0 0 1 1 A0 A0 A0 A0 0 1 0 1 0 1 0 1 1 1 1 Speaker LF Speaker RF Speaker LR Speaker RR 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 -10 -20 -30 Mute For example attenuation of 25 dB on speaker RF is given by: 1 0 1 1 0 1 0 0 16/20 TDA7303 Software specification Table 10. Audio switch MSB 0 1 0 G1 G0 S2 LSB Function S1 S0 Audio Switch 0 0 Stereo 1 0 1 Stereo 2 1 0 Stereo 3 1 1 Not allowed 0 Loudness ON 1 Loudness OFF 0 0 +11.25 dB 0 1 +7.5 dB 1 0 +3.75d B 1 1 0 dB For example to select the stereo 2 input with a gain of +7.5dB LOUDNESS ON the 8bit string is: 0 1 0 0 1 0 0 1 Table 11. Bass and treble MSB LSB Function 0 1 1 0 C3 C2 C1 C0 Bass 0 1 1 1 C3 C2 C1 C0 Treble 0 0 0 0 -14 0 0 0 1 -12 0 0 1 0 -10 0 0 1 1 -8 0 1 0 0 -6 0 1 0 1 -4 0 1 1 0 -2 0 1 1 1 0 1 1 1 1 0 1 1 1 0 2 1 1 0 1 4 1 1 0 0 6 1 0 1 1 8 1 0 1 0 10 1 0 0 1 12 1 0 0 0 14 C3 = Sign For example Bass at -10dB is obtained by the following 8 bit string: 0 1 1 0 0 0 1 0 17/20 Package information 5 TDA7303 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 24. SO-28 mechanical data and package dimensions mm DIM. MIN. TYP. A MAX. MIN. TYP. 2.65 MAX. 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 0.5 c1 0.020 45° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S OUTLINE AND MECHANICAL DATA 0.104 a1 C 18/20 inch 8 ° (max.) SO-28 TDA7303 6 Revision history Revision history Table 12. Document revision history Date Revision Changes 04-Aug-2006 1 Initial release. 13-Mar-2009 2 Updated “distortion” parameter in the Table 5: Electrical characteristics on the page 9. Modified the max. clock speed value in Section 4.1: Interface protocol on page 15. Updated Section 5: Package information on page 18. 18-Mar-2009 3 Modified the test condition of the parameter “distortion” in the Table 5: Electrical characteristics on the page 9. 17-Sep-2013 4 Updated Disclaimer 19/20 TDA7303 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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