TDA7319

TDA7319 ® 3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR ONE STEREO INPUT ONE STEREO OUTPUT TWO INDEPENDENT VOLUME CONTROL IN 1.0dB STEPS TREBLE, MIDDLE AND BASS CONTROL IN 1.0dB STEPS ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2 CBUS DIP20 DESCRIPTION The TDA7319 is a volume and tone (bass , middle and treble) processor for quality audio application in car radio and Hi-Fi system. Control is accomplished by serial I2C bus microprocessor interface. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. c u d ) s ( ct C1 2.2µF o r P e 2 L s b O e t le o s b O C5 15nF MOUT(L) 5 C9 100nF BIN(L) 6 C10 100nF BOUT(L) 7 2nd VOL TREBLE BASS MIDDLE 8 10 SERIAL BUS DECODE & LATCHES 2nd VOL TREBLE 9 BASS MIDDLE 13 OUT L SCL SDA I2C BUS DIGGND OUT R SUPPLY 12 AGND CREF 20 18 TREBLE(R) CREF 10µF C4 5.6nF MIN(R) 17 16 MOUT(R) C7 15nF 15 14 BIN(L) C8 22nF R2 2.7K September 2003 C6 22nF R3 5.6K 1st VOL R 1 R1 2.7K 11 19 VS 4 du o r P Thanks to the used BIPOLAR/MOS Technology, Low Distortion, Low Noise and Low Dc stepping are obtained. 1st VOL t e l o C2 2.2µF MIN(L) 3 ) s t( ORDERING NUMBERS: TDA7319 (DIP20) TDA7319D (SO20) BLOCK DIAGRAM AND APPLICATION CIRCUIT C3 5.6nF TREBLE(L) SO20 BOUT(R) C11 100nF D93AU042E C12 100nF R4 5.6K 1/16 TDA7319 ABSOLUTE MAXIMUM RATINGS Symbol VS Tamb Tstg Parameter Value Unit 10.5 V Operating Ambient Temperature -40 to 85 °C Storage Temperature Range -55 to 150 °C Operating Supply Voltage PIN CONNECTION VS 1 20 CREF IN L 2 19 IN R TREBLE L 3 18 TREBLE R M IN L 4 17 M IN R M OUT L 5 16 M OUT R B IN L 6 15 B IN R B OUT L 7 14 B OUT R OUT L 8 13 OUT R SDA 9 12 SCL 10 11 o s b O - e t le GND c u d ) s t( o r P DIG GND D93AU041A ) s ( ct THERMAL DATA Symbol Rth j-amb Parameter DIP20 SO20 Unit 150 150 °C/W Thermal Resistance Junction-pins u d o r P e QUICK REFERENCE DATA Symbol VCL THD S/N s b O SC Min. Typ. Max. Supply Voltage 6 9 10.5 Max. input signal handling 2 Unit V Vrms Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio 0.01 106 Channel Separation f = 1KHz 100 0.08 % dB dB 1st and 2nd Volume Control 1dB step -47 0 dB Bass, Middle and Treble Control 1dB step -14 +14 dB Mute Attenuation 2/16 Parameter t e l o VS 100 dB TDA7319 ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10KΩ; f = 1KHz; all control = flat (G = 0); Tamb = 25°C Refer to the test circuit, unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit 35 50 65 KΩ 45 45 0.5 -1.0 -1.5 47 47 1.0 49 49 1.5 1.0 1.5 1 2 80 100 0 0.5 dB dB dB dB dB dB dB dB mV mV INPUT Rin Input Resistance 1st VOLUME CONTROL CRANGE AVMAX Astep EA Et Control Range Maximum Attenuation Step Resolution Attenuation Set Error G = 0 to -24dB G = -24 to -47dB G = 0 to -24dB G = 24 to -47dB Tracking Error Amute VDC Mute Attenuation DC Steps Adiacent Attenuation Steps From 0dB to AVMAX 2nd VOLUME CONTROL 3 5 CRANGE AVMAX Astep EA Et Control Range Maximum Attenuation Step Resolution Attenuation Set Error 100 0 0.5 3 5 32 ±11.5 0.5 44 ±14 1 56 ±16 1.5 KΩ dB dB 18 ±11.5 0.5 25 ±14 1 32 ±16 1.5 KΩ dB dB Control Range Step Resolution ±13 0.5 ±14 1 ±15 1.5 dB dB Supply Voltage (note1) Supply Current Ripple Rejection 6 4 60 9 7 90 10.5 10 V mA dB 2 2 100 2.6 Tracking Error AMUTE VDC Mute Attenuation DC Steps Rb CRANGE (t s) Internal Feedback Resistance Control Range Step Resolution MIDDLE o r P e c u d Internal Feedback Resistance Control Range Step Resolution t e l o Astep TREBLE s b O CRANGE Astep 80 Adiacent Attenuation Steps From 0dB to AVMAX BASS Rb CRANGE Astep b O - d o r P e let so 47 47 1.0 uc dB dB dB dB dB dB dB dB mV mV G = 0 to -24dB G = -24 to -47dB G = 0 to -24dB G = 24 to -47dB 45 45 0.5 -1.0 -1.5 ) s t( 49 49 1.5 1.0 1.5 1 2 SUPPLY VS IS SVR AUDIO OUTPUT Vclip ROl RO VDC Clipping Level Output Load Resistance Output Impedance DC Voltage Level d = 0.3% 180 3.8 300 Vrms KΩ Ω V 3/16 TDA7319 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit 5 0 0 106 100 0.01 15 1 2 µV dB dB dB dB % GENERAL eNO Et Output Noise Total Tracking Error S/N SC d Signal to Noise Ratio Channel Separation Distortion All Gains 0dB (B = 20 to 20kHz flat) AV = 0 to -24dB AV = -24 to -47dB All Gains = 0dB; VO = 1Vrms 80 AV = 0; Vin = 1Vrms 0.08 BUS INPUTS Vil Vih Iin VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge 1 3 -5 Vin = 0.4V IO = 1.6mA 5 0.8 0.4 Note 1: the device is functionally good at Vs = 5V. A step down, on VS, to 4V does’t reset the device. APPLICATION SUGGESTIONS The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) with a 1dB step. The very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7319 audioprocessor provides 3 bands tones control. t c u d o r P e t e l o Figure 1. bs O ) s t( The fig.1 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed as follows: e t le FC = o s b O - Bass, Middle Stages The Bass and the middle cells have the same structure. The Bass cell has an internal resistor Ri = 44KΩ typical. The Middle cell has an internal resistor Ri = 25KΩ typical. Several filter types can be implemented, connecting external components to the Bass/Middle IN and OUT pins. (s) c u d V V µA V AV = o r P 1  Ri, R2, C1, C2 2 ⋅ π ⋅√ R2 C2 + R2 C1 + Ri C1 R2 C1 + R2 C2 Q= √   Ri R2 + C1 C2 R2 C1 + R2 C2 Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be: C1 = AV − 1 2 ⋅ π ⋅ Ri ⋅ Q R2 = C2 = Q2 ⋅ C1 AV − 1 Q2 AV − 1 − Q2 2 ⋅ π ⋅ C1 ⋅ FC ⋅ (AV − 1) ⋅Q Ri internal IN OUT C1 C2 Treble Stage The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and an external capacitor connected between treble pins and ground Typical responses are reported in Figg. 10 to 13. R2 D95AU313 4/16 CREF The suggested 10µF reference capacitor (CREF) value can be reduced to 4.7µF if the application requires faster power ON. TDA7319 Figure 2: Noise vs. volume setting Figure 3: SVRR vs. frequency Figure 4: THD vs. frequency Figure 5: THD vs. RLOAD e t le ) s ( ct u d o r P e Figure 6: Channel separation vs. frequency c u d ) s t( o r P o s b O - Figure 7: Output clip level vs. Supply voltage t e l o s b O 5/16 TDA7319 Figure 8: Quiescent current vs. supply voltage Figure 9: Quiescent current vs. temperature Figure 10: Bass response Figure 11: Middle response Ri = 44kΩ C9 = C10 = 100nF (Bout, Bin) R3 = 5.6kΩ ) s ( ct u d o r P e Figure 12: Treble response t e l o s b O 6/16 CTREBLE = 5.6nF Ri = 25kΩ C9 = 15nF (MIN) C6 - 22nF (MOUT) R1 = 2.7kΩ e t le c u d o r P o s b O - Figure 13: Typical tone response ) s t( TDA7319 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7319 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier transmission: simply it generates the 9th clock pulse without checking the slave acknowledging, and then sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. c u d Data Validity on the I2CBUS e t le ) s ( ct 2 Timing Diagram of I CBUS ) s t( o r P o s b O - u d o r P e t e l o s b O Acknowledge on the I2CBUS 7/16 TDA7319 SDA, SCL I2CBUS TIMING Symbol Parameter Min. Typ. Max. Unit 400 kHz fSCL SCL clock frequency tBUF Bus free time between a STOP and START condition 1.3 µs Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tHD:STA 0 0.6 µs 0.300 µs Data set-up time 100 ns tR Rise time of both SDA and SCL signals 20 300 ns (*) tF Fall time of both SDA and SCL signals 20 300 ns (*) Set-up time for STOP condition 0.6 tSU:STA Set-up time for a repeated START condition tHD:DA Data hold time tSU:DAT tSU:STO µs All values referred to VIH min. and VIL max. levels (*) Must be guaranteed by the I2C BUS master. c u d Definition of timing on the I2C-bus e t le SDA tBUF tR tF u d o tLOW r P e P S P = STOP S = START t e l o s b O 8/16 tHD;STA tHIGH ) s ( ct SCL tHD;DAT o s b O tF ) s t( o r P tHD;STA tSP tSU;STO tSU;STA tSU;DAT Sr D95AU314 P TDA7319 address (the 8th bit of the byte must be 0). The TDA7319 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P) SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7319 TDA7319 ADDRESS first byte MSB S 1 0 0 0 LSB 0 1 A MSB LSB DATA 0 ACK MSB LSB DATA ACK ACK P Data Transferred (N-bytes + Acknowledge) ACK = Acknowledge S = Start P = Stop c u d MAX CLOCK SPEED 400kbits/s e t le SOFTWARE SPECIFICATION Chip address 1 MSB 0 0 0 0 1 0 LSB ) s ( ct u d o FUNCTION CODES o r P o s b O - MSB F6 F5 F4 F3 F2 F1 LSB 0 0 F6 F6 F5 F5 F4 F4 F3 F3 F2 F2 F1 F1 0 1 TREBLE MIDDLE 1 1 0 0 0 1 F4 F4 F3 F3 F2 F2 F1 F1 F0 F0 BASS 1 1 0 F4 F3 F2 F1 F0 MUTMUX 1 1 1 F4 F3 F2 F1 F0 r P e 1st VOLUME 2nd VOLUME t e l o s b O 1 ) s t( POWER ON RESET: 1st volume = 2nd volume = Mute Treble = Middle = Bass = -14dB Mutmux = Active Input 9/16 TDA7319 1st VOLUME CODES MSB F6 F5 F4 F3 F2 F1 0 step 1dB 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB 0 MSB 0 0 0dB 0 0 1 -8dB 0 1 0 -16dB 0 1 1 -24dB 1 1 0 0 0 1 -32dB -40dB 1 1 1 F6 c u d MUTE F5 F4 F3 0 0 0 (t s) 0 uc 0 d o r P e t e l o 0 0 bs step 8dB 0 e t le 2nd VOLUME CODES 10/16 FUNCTION 0 0 0 O LSB F2 so 0 o r P LSB FUNCTION 1 0 step 1dB 0dB 0 1 -1dB b O - F1 ) s t( 1 0 -2dB 0 1 1 -3dB 1 1 0 0 0 1 -4dB -5dB 1 1 0 -6dB 1 1 1 1 -7dB step 8dB 0 0 0 1 0dB -8dB 0 1 0 -16dB 0 1 1 -24dB 1 1 0 0 0 1 -32dB -40dB 1 1 1 MUTE TDA7319 TREBLE CODES MSB F6 F5 1 0 0 1 0 F4 F3 F2 F1 LSB 0 0 0 0 0 0dB 0 0 0 0 1 1dB 0 0 0 1 0 2dB 0 0 0 1 1 3dB 0 0 1 0 0 4dB 0 0 1 0 1 5dB 0 0 1 1 0 6dB 0 0 1 1 1 7dB 0 1 0 0 0 8dB 0 0 1 1 0 0 0 1 1 0 9dB 10dB 0 1 0 1 1 11dB 0 1 1 0 0 12dB 0 1 1 0 1 13dB 0 1 1 1 0 14dB 0 1 1 1 1 0 c u d 14dB ) s t( TREBLE CUT 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 1 1 0 1 -4dB 0 1 1 -5dB 1 0 1 so 0 1 1 0 -6dB 1 0 1 1 1 -7dB 0 0 0 0 0 1 -8dB -9dB 1 1 0 0 1 1 0 1 -10dB -11dB 1 1 0 0 -12dB 1 1 1 1 1 1 0 1 1 0 -13dB -14dB 1 1 1 1 1 -14dB 1 1 ) s ( ct u d o 1 r P e o r P 1 1 1 t e l o FUNCTION TREBLE BOOST 1 1 b O - 0 0 e t le 0 1 0dB -1dB -2dB -3dB s b O 11/16 TDA7319 MIDDLE CODES MSB F6 F5 1 0 1 1 0 F4 F3 LSB 0 0 0 0 0dB 0 0 0 0 1 1dB 0 0 0 1 0 2dB 0 0 0 1 1 3dB 0 0 1 0 0 4dB 0 0 1 0 1 5dB 0 0 1 1 0 6dB 0 0 1 1 1 7dB 0 1 0 0 0 8dB 0 0 1 1 0 0 0 1 1 0 9dB 10dB 0 1 0 1 1 11dB 0 1 1 0 0 12dB 0 1 1 0 1 13dB 0 1 1 1 0 14dB 0 1 1 1 1 1 c u d 14dB ) s t( MIDDLE CUT 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 1 1 0 1 -4dB 0 1 1 -5dB 1 0 1 so 0 1 1 0 -6dB 1 0 1 1 1 -7dB 0 0 0 0 0 1 -8dB -9dB 1 1 0 0 1 1 0 1 -10dB -11dB 1 1 0 0 -12dB 1 1 1 1 1 1 0 1 1 0 -13dB -14dB 1 1 1 1 1 -14dB 1 r P e o r P 1 ) s ( ct u d o t e l o FUNCTION 0 1 1 12/16 F1 MIDDLE BOOST 1 1 s b O F2 1 1 b O - 0 0 e t le 0 1 0dB -1dB -2dB -3dB TDA7319 BASS CODES MSB F6 F5 1 1 0 1 1 F4 F3 F1 LSB 0 0 0 0 0 0dB 0 0 0 0 1 1dB 0 0 0 1 0 2dB 0 0 0 1 1 3dB 0 0 1 0 0 4dB 0 0 1 0 1 5dB 0 0 1 1 0 6dB 0 0 1 1 1 7dB 0 1 0 0 0 8dB 0 0 1 1 0 0 0 1 1 0 9dB 10dB 0 1 0 1 1 11dB 0 1 1 0 0 12dB 0 1 1 0 1 13dB 0 1 1 1 0 14dB 0 1 1 1 1 0 o r P BASS CUT 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 1 1 0 1 -4dB 0 1 1 -5dB 1 0 1 so 0 1 1 0 -6dB 1 0 1 1 1 -7dB 0 0 0 0 0 1 -8dB -9dB 1 1 0 0 1 1 0 1 -10dB -11dB 1 1 0 0 -12dB 1 1 1 1 1 1 0 1 1 0 -13dB -14dB 1 1 1 1 1 -14dB F4 F3 F2 F1 LSB FUNCTION X X X 0 0 INPUTS NOT ALLOWED X X X 0 1 NOT ALLOWED X X X 1 X 1 1 1 0 1 NOT ALLOWED IN ) s ( ct u d o 1 r P e c u d 14dB ) s t( 1 1 1 t e l o FUNCTION BASS BOOST 1 1 s b O F2 1 1 b O - 0 0 e t le 0 1 0dB -1dB -2dB -3dB MUTMUX CODES MSB F6 F5 1 1 1 13/16 TDA7319 mm inch OUTLINE AND MECHANICAL DATA DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.6 13 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 K c u d e t le 0˚ (min.)8˚ (max.) o s b O - L ) s ( ct u d o B r P e t e l o s b O o r P SO20 h x 45˚ A e A1 K H D 20 11 E 1 0 1 SO20MEC 14/16 ) s t( C TDA7319 mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. OUTLINE AND MECHANICAL DATA 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L 3.3 Z c u d 0.130 1.34 e t le 0.053 ) s ( ct ) s t( o r P DIP20 o s b O - u d o r P e t e l o s b O 15/16 TDA7319 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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