TDA7332D

TDA7332 RDS FILTER 1 FEATURES Figure 1. Package ■ HIGH PERFORMANCE, STABLE 57KHz FILTER ■ HIGH SELECTIVITY ■ FLAT GROUP DELAY ■ HIGH PERFORMANCE LIMITER ■ VERY FEW EXTERNAL COMPONENTS ■ 4.332MHz CLOCK OSCILLATOR (8.664MHz OPTIONAL) 2 SO14 Table 1. Order Codes Part Number Package TDA7332D SO14 TDA7332D013TR Tape & Reel c u d TDA7332DIE1 DESCRIPTION ) s t( Chip on wafer The TDA7332 is an RDS filter, realized in switched capacitor technique. Optionally a 8.664MHz xtal can be used. The 4 biquad stage architecture is working with 4.332MHz clock. The filter has a center frequency of 57KHz and a bandwidth of 3KHz. Input 2nd order antialiasing filter and output smoothing filter are provided. Block Diagram ) s ( ct e t le o r P o s b O - u d o r P e t e l o s b O September 2004 Rev. 2 1/6 TDA7332 Figure 2. Absolute Maximum Ratings Symbol Parameter Value Unit 7 V VS Supply Voltage Top Operating Temperature Range -40 to 85 °C Tstg Storage Temperature -40 to 150 °C Table 2. Thermal Data Symbol Rth j-case Parameter Thermal Resistance Junction-case Value Unit 200 °C Figure 3. Pin Connection (Top view) c u d e t le ) s ( ct Figure 4. Bonding Pad Locations (Top view) ) s t( o r P o s b O - u d o r P e t e l o s b O Table 3. Electrical Characteristcs (VCC = 5V, Tamb = 25°C; fosc = 4.332MHz; VIN = 20mVrms unless 2/6 TDA7332 otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY SECTION VCC Supply Voltage 4.5 5 5.5 V IS Supply Current 6 9 14 mA 56.5 57 57.5 KHz KHz FILTER FC Center Frequency BW 2.5 3 3.5 G Gain 3dB Bandwidth f = 57KHz 18 20 22 A Attenuation ∆f = ±4KHz 18 22 dB f = 38KHz; Vi = 500mVrms 50 80 dB f = 67KHz; Vi = 250mVrms 35 50 dB ∆Ph Phase non linearity Ri A (see note1) 0.5 5 B (see note1) 1 7.5 DEG C (see note1) 2 10 DEG 100 160 200 KΩ 30 40 Input Impedance Signal to Noise Ratio V Vi Input Signal f = 19KHz; T3 < –40dB (see note2) R Load Impedance S/N i = 3mVrms f = 57KHz (RDS + ARI) L Pin 12 e t le LIMITER RA Resistance pin 8-12 VOL Comp. Output LOW IO = +0.5mA Comp. Output HIGH IO = –0.5mA Duty Cycle Vi = 1mVrms VOH OSCILLATOR FOSC Oscillator Frequency c u d Output Amplitude VCLL Clock Input Level LOW VOLH Clock Input Level HIGH o r P e dB so b O - uc DEG ) s t( dB 1 Vrms 50 mVrms 100 od 15 21 28 KΩ 1 V Pr KΩ 4 V 50 % FSEL = Open 4.332 MHz FSEL = Closed to Ground 8.664 MHz 4.5 VPP (t s) 1 4 V V CRYSTAL TYPE = EURO QUARTZ t e l o Note (1): The phase non linearity is defined as: DPh = | -2 ff2 + ff1 + ff3 | where ffx is the input-output phase difference at the frequency fx (x = 1,2,3) s b O Table 4. Measure f1 (KHz) f2 (KHz) f3 (KHz) ∆Ph max A 56.5 57 57.5