TDA7348
Digitally controlled audio processor
Features
●
Input multiplexer
–
Three stereo and one mono inputs
–
Selectable input gain for optimal
adaptation to different sources
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Volume control in 0.3db steps including gain
up to 20dB
●
Zero crossing mute and direct mute
●
Pause detector with programmable threshold
●
Soft mute controlled by software or hardware
PIN
●
Bass and treble control
●
Four speaker attenuators
–
Four independent speakers control in
1.25dB steps for balance and fader
facilities
●
Independent mute function
All functions programmable via serial I2C bus
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Description
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Thanks to the used BIPOLAR/CMOS technology,
very low distortion, low noise and DC-stepping
are obtained. Due to a highly linear signal
processing, using CMOS-switching techniques
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SO-28
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instead of standard bipolar multipliers, very low
distortion and very low noise are obtained Several
new features like softmute, zero-crossing mute
and pause detector are implemented.
The Soft Mute function can be activated in two
ways, either via the serial bus (bit D0, Mute Byte),
or directly on pin 22 through an I/O line of the
microcontroller
The TDA7348 is an upgrade of the TDA7318
audioprocessor.
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Very low DC stepping is obtained by use of a
BICMOS technology.
Order codes
Part number
Package
Packing
TDA7348D
SO-28
Tube
SO-28
Tape and reel
SO-28
Tube
SO-28
Tape and reel
TDA7348D013TR
E-TDA7348D
(1)
E-TDA7348D013TR
(1)
1. This device is Pb-free Ecopack , see Chapter 5 Package information.
January 2007
Rev 3
1/20
www.st.com
1
Contents
TDA7348
Contents
1
Block diagram and PIN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
I2C BUS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
3.1
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5
Transmission without acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . 10
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Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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4.1
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
Transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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TDA7348
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Speaker attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bass/Treble. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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List of figures
TDA7348
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Data validity on the I2C BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing diagram of I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Acknowledge on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SO-28 mechanical, data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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TDA7348
Block diagram and PIN connections
1
Block diagram and PIN connections
Figure 1.
Block diagram
R2
4.7K
C10 2.2μF
3x
1μF
C1
LEFT
INPUTS
C2
OUT(L)
IN(L)
17
16
C14
100nF
SM BOUT(L)
BIN(L)
19
18
22
C16
2.7nF
TREBLE(L)
C15
100nF
4
SPKR
ATT
RB
L1
14
26
L1
L2
13
L2
L3
12
L3
C3
MUTE
ZERO
CROSS +
MUTE
VOL
1, 2
BASS
TREBLE
SPKR
ATT
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L4
24
MUTE
C4
3x
1μF
C7
RIGHT
INPUTS
C6
INPUT
SELECTOR
+ GAIN
11
SERIAL BUS DECODER + LATCHES
R4
R3
8
R2
9
R1
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R3
ZERO
CROSS +
MUTE
R2
VOL
1, 2
BASS
R1
C5
VS
2
bs
SUPPLY
3
1
7
6
AGND
CREF
OUT(R)
IN(R)
C8
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10μF
-O
15
CSM
C9 2.2μF
CSM
47nF
21
TREBLE
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27
SCL
BUS
SDA
SPKR
ATT
25
MUTE
OUT
RIGHT FRONT
SPKR
ATT
23
RB
BOUT(R)
28
OUT
LEFT REAR
MUTE
OUT
RIGHT REAR
5
BIN(R)
TREBLE(R)
D93AU100B
C11
100nF
C12
100nF
C13
2.7nF
R1
4.7K
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Figure 2.
PIN connections
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SOFT
MUTE
OUT
LEFT FRONT
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CREF
1
28
SCL
VS
2
27
SDA
GND
3
26
OUT LF
L
4
25
OUT RF
R
5
24
OUT LR
IN(R)
6
23
OUT RR
OUT(R)
7
22
SM
IN R3
8
21
BOUT(R)
IN R2
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BIN(R)
IN R1
10
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BOUT(L)
AM MONO
11
18
BIN(L)
IN L3
12
17
OUT(L)
IN L2
13
16
IN(L)
IN L1
14
15
CSM
TREBLE
BUS
INPUTS
BASS
D94AU099
5/20
Electrical characteristics
2
TDA7348
Electrical characteristics
Table 1.
Electrical characteristics
VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all controls flat (G = 0.3dB step
0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
70
100
130
KΩ
2.1
2.6
Input selector
RI
VCL
Input resistance
d ≤ 0.3%
Clipping level
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Input separation
80
100
RL
Output load resistance
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KΩ
3.75
GI MIN
Minimum input gain
GI MAX
Maximum input gain
Gstep
eN
VDC
-0.75
P
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Step resolution
Input noise
dB
10.25 11.25 12.25
dB
2.75
dB
let
0
20Hz to 20 KHz unweighted
2.3
Adiacent gain steps
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DC steps
GIMIN to GIMAX
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dB
0.75
ro
Volume control (1 + 2)
4.75
μV
10
mV
3
mV
35
50
KΩ
18.75
20
RI
Input resistance
GMAX
Maximum gain
AMAX
Maximum attenuation
ASTEPC
Step resolution coarse
attenuation
0.5
1.25
2.0
dB
ASTEPF
Step resolution fine
attenuation
0.11
0.31
0.51
dB
G = 20 to -20dB
-1.25
0
1.25
dB
EA
Attenuation set error
G = -20 to -58dB
-3
2
dB
Et
Tracking error
2
dB
0
3
mV
From 0dB to AMAX
0.5
5
mV
WIN = 11
20
mV
WIN = 10
40
mV
WIN = 01
80
mV
WIN = 00
160
mV
100
dB
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Adiacent attenuation steps
VDC
21.25
78.45
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VRMS
-3
dB
dB
DC steps
Zero crossing mute
VTH
AMUTE
VDC
6/20
Zero crossing threshold
Mute attenuation
DC step
80
0dB to Mute
0
3
mV
TDA7348
Electrical characteristics
Table 1.
Electrical characteristics (continued)
VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all controls flat (G = 0.3dB step
0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
45
60
CCSM = 22nF; 0 to -20dB; I =
IMAX
0.7
1
1.7
ms
CCSM = 22nF; 0 to -20dB; I =
IMIN
20
35
55
ms
VCSM = 0V; I = IMAX
25
50
75
Soft mute
AMUTE
Mute attenuation
TDON
ON delay time
TDOFF
OFF delay time
VTHSM
Soft mute threshold
VCSM = 0V; I = IMIN
RINT
Pull-up resistor (pin 22)
VSMH
(pin 22) level high
VSML
(pin 22) level low
BBOOST
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μA
3.5
V
65
KΩ
3.5
V
1
V
18
20
dB
-8.5
-10
-11.5
dB
1
2
3
dB
45
65
85
KΩ
±13
±14
±15
dB
1
2
3
dB
Control range
35
37.5
40
dB
Step resolution
0.5
1.25
2.0
dB
80
100
Astep
Step resolution
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Internal feedback resistance
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Treble control
Astep
P
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Soft Mute active
50
μA
15
Max bass cut
CRANGE
ro
35
Max bass boost
BCUT
Rg
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2.5
(s)
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1
1.5
Bass control
dB
Control range
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Step resolution
Speaker attenuators
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CRANGE
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Astep
AMUTE
Output mute attenuation
EA
Attenuation set error
VDC
DC steps
Data word = XXX11111
Adjacent attenuation steps
0
dB
1.25
dB
3
mV
Audio output
Vclip
Clipping level
RL
Output load resistance
RO
Output impedance
VDC
DC voltage level
d = 0.3%
2.1
2.6
Vrms
2
KΩ
30
100
W
3.5
3.8
4.1
V
6
9
10.2
V
General
VCC
Supply voltage
7/20
Electrical characteristics
Table 1.
Electrical characteristics (continued)
VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all controls flat (G = 0.3dB step
0dB); f = 1KHz. Refer to the test circuit, unless otherwise specified.
Symbol
ICC
TDA7348
Parameter
Test Condition
Min.
Typ.
Max.
Unit
5
10
15
mA
60
80
dB
B = 20 to 20kHz "A" weighted
65
dB
Output Muted (B = 20 to
20kHz flat)
2.5
μV
All Gains 0dB (B = 20 to
20kHz flat)
5
AV= 0 to -20dB
0
Supply current
f = 1KHz
PSRR
Power supply rejection ratio
Output noise
eNO
Et
Total tracking error
S/N
Signal to noise ratio
SC
Channel separation
d
All Gains = 0dB; VO= 1Vrms
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Vin = 1V
Bus inputs
Input low voltage
VlN
Input high voltage
IlN
Input current
VO
Output voltage SDA
acknowledge
Table 2.
VS
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Tamb
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Tstg
Table 3.
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VIN = 0.4V
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Pr
2
dB
dB
100
dB
0.01
0.08
%
1
V
3
V
-5
IO = 1.6mA
0.4
Parameter
5
μA
0.8
V
Unit
10.5
V
Operating ambient temperature
-40 to 85
°C
Storage temperature range
-55 to 150
°C
SO28
Unit
65
°C/W
Operating supply voltage
Thermal data
Parameter
Rth j-amb Thermal Resistance Junction pins
Quick reference data
Symbol
8/20
dB
Value
Symbol
Table 4.
1
Absolute maximum ratings
Pr
Symbol
106
80
Distortion
VIL
0
μV
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AV= -20 to -60dB
15
Parameter
VS
Supply voltage
VCL
Max. input signal handling
Min.
Typ.
Max.
Unit
6
9
10.2
V
2.1
2.6
THD
Total harmonic distortion V = 1Vrms f = 1KHz
0.01
S/N
Signal to noise ratio
106
Vrms
0.08
%
dB
TDA7348
Electrical characteristics
Table 4.
Quick reference data (continued)
Symbol
SC
Parameter
Min.
Channel separation f = 1KHz
Typ.
Max.
100
Unit
dB
78.45
20
dB
Treble control 2dB step
-14
+14
dB
Bass control 2dB step
-10
+18
dB
38.75
0
dB
0
11.2
5
dB
Volume control
Fader and balance control 1.25dB step
Input gain 3.75dB step
Mute attenuation
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100
dB
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I2C BUS interface
TDA7348
I2C BUS interface
3
Data transmission from microprocessor to the TDA7348 and vice-versa takes place through
the 2 wires of the I2C BUS interface, consisting of the two lines SDA and SCL (pull-up
resistors to the positive supply voltage must be externally connected).
3.1
Data validity
As shown in Figure 3., the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
3.2
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Start and stop conditions
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As shown in Figure 4. a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH.
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A STOP conditions must be sent before each START condition.
3.3
Byte format
)
(s
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Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
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3.4
Acknowledge
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The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 5.). The peripheral (audioprocessor) that
acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during this clock pulse.
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3.5
The audioprocessor which has been addressed has to generate an acknowledge after the
reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case the master transmitter can generate the STOP information in
order to abort the transfer.
Transmission without acknowledgement
The microprocessor can use a simpler transmission, if it avoids detection of the
acknowledgement from the audio processor. It simply waits one clock pulse without
checking the slave acknowledgment, and sends the new data.
This approach of course is less protected from errors, increases the possibility of
interference, and decreases the immunity to noise.
10/20
I2C BUS interface
TDA7348
Figure 3.
Data validity on the I2C BUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
Figure 4.
CHANGE
DATA
ALLOWED
D99AU1031
Timing diagram of I2C BUS
SCL
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I2CBUS
SDA
Figure 5.
)-
1
s
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SDA
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START
2
STOP
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Acknowledge on the I2C BUS
SCL
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D99AU1032
START
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3
7
8
9
MSB
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
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Software specification
TDA7348
4
Software specification
4.1
Interface protocol
The interface protocol comprises:
●
A start condition (s)
●
A chip address byte, (the LSB bit determines read/write transmission)
●
A subaddress byte.
●
A sequence of data (N-bytes + acknowledge)
●
A stop condition (P)
Chip address
Subaddress
MSB
S
1
LSB
MSB
0 0 0 1 0 0 R/W ACK
X
LSB
X X
S = Start
I = Auto Increment
X = Not used
)
(s
Max clock speed 500kbits/s
LSB
Pr
DATA
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ACK = Acknowledge
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MSB
I A3 A2 A1 A0 ACK
P = Stop
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Data 1 to data n
ACK P
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4.2
Auto increment
If bit I in the subaddress byte is set to "1", the auto-increment of the subaddress is enabled
Table 5.
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MSB
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12/20
X
X
Subaddress (receive mode)
X
LSB
I
Function
A3
A2
A1
A0
0
0
0
0
Input selector
0
0
0
1
Loudness
0
0
1
0
Volume
0
0
1
1
Bass, Treble
0
1
0
0
Speaker attenuator LF
0
1
0
1
Speaker attenuator LR
0
1
1
0
Speaker attenuator RF
0
1
1
1
Speaker attenuator RR
1
0
0
0
Mute
TDA7348
4.3
Software specification
Transmitted data
Table 6.
Send mode
MSB
LSB
X
X
X
X
X
SM
ZM
X
ZM = Zero crossing muted (HIGH active)
SM = Soft mute activated (HIGH active)
X = Not used
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chip address.
4.4
)
s
(
ct
Data byte specification
u
d
o
X = not relevant; set to "1" during testing
Table 7.
let
LSB
D1
D0
0
0
0
not used
0
0
1
IN 2
0
1
0
IN 1
0
1
1
AM mono
1
0
0
not used
1
0
1
IN 3
MSB
D7
D6
D5
X
X
1
X
X
1
X
X
1
X
X
1
X
X
1
X
X
1
X
D4
)
s
(
ct
-O
u
d
o
Pr
o
s
b
D3
D2
Function
X
1
1
1
0
not allowed
X
1
1
1
1
not allowed
X
X
1
0
0
11.25dB gain
X
X
1
0
1
7.5dB gain
X
X
1
1
0
3.75dB gain
X
X
1
1
1
0dB gain
X
e
t
e
ol
s
b
O
r
P
e
Input Selector
For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1
Table 8.
Loudness
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
1
0
0
0
0
0dB
X
X
X
1
0
0
0
1
-1.25dB
X
X
X
1
0
0
1
0
-2.5dB
13/20
Software specification
Table 8.
TDA7348
Loudness (continued)
MSB
LSB
Function
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
1
0
0
1
1
-3.75dB
X
X
X
1
0
1
0
0
-5dB
X
X
X
1
0
1
0
1
-6.25dB
X
X
X
1
0
1
1
0
-7.5dB
X
X
X
1
0
1
1
1
-8.75dB
X
X
X
1
1
0
0
0
-10dB
X
X
X
1
1
0
0
1
-11.25dB
X
X
X
1
1
0
1
0
-12.5dB
X
X
X
1
1
0
1
1
-13.75dB
X
X
X
1
1
1
0
X
X
X
1
1
1
0
X
X
X
1
1
1
X
X
X
1
1
1
r
P
e
let
1
o
s
b
1
)
s
(
ct
u
d
o
0
-15dB
1
-16.25dB
0
-17.5dB
1
-18.75dB
For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0
Table 9.
O
)
Mute
s
(
t
c
MSB
D7
e
t
e
ol
D6
D5
u
d
o
D3
D2
Pr
1
s
b
O
14/20
D4
LSB
Function
D1
D0
1
Soft mute on
0
1
Soft mute with fast slope (I = IMAX)
1
1
Soft mute with slow slope (I = IMIN)
Direct mute
0
1
Zero crossing mute on
0
0
Zero crossing mute off
(delayed until next zerocrossing)
1
Zero crossing mute and pause detector
reset
0
0
160mV ZC window threshold (WIN = 00)
0
1
80mV ZC window threshold (WIN = 01)
1
0
40mV ZC window threshold (WIN = 10)
1
1
20mV ZC window threshold (WIN = 11)
0
Non-symmetrical Bass Cut
1
Symmetrical Bass Cut
TDA7348
Software specification
An additional direct mute function is included in the speaker attenuators.
Note:
Bass cut for very low frequencies should not be used at +16 & +18dB bass boost (DC gain)
Table 10.
Speaker attenuators
MSB
LSB
Speaker attenuator LF, LR, RF, RR
D7
D5
D6
D4
D3
D2
D1
D0
1.25dB step
X
X
X
0
0
0
0dB
X
X
X
0
0
1
-1.25dB
X
X
X
0
1
0
-2.5dB
X
X
X
0
1
1
-3.75dB
X
X
X
1
0
0
X
X
X
1
0
1
X
X
X
1
1
0
u
d
o
X
X
X
1
1
X
X
X
0
0
X
X
X
0
1
X
X
X
1
0
X
X
X
1
X
X
X
ct
1
u
d
o
)
(s
1
1
1
e
t
e
ol
1
-5dB
Pr
-7.5dB
-8.75dB
10dB step
0dB
s
b
O
1
-6.25dB
)
s
(
ct
-10dB
-20dB
-30dB
1
Speaker mute
For example an attenuation of 25dB on a selected output is given by: X X X1 0 1 0 0
Pr
Table 11.
MSB
e
t
e
l
D7
O
o
s
b
D6
Bass/Treble
LSB
Function
D5
D4
D3
D2
D1
D0
Treble step
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
15/20
Software specification
Table 11.
TDA7348
Bass/Treble (continued)
MSB
LSB
Function
D7
D5
D6
D4
D3
D2
D1
D0
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
)
s
(
ct
BASS STEPS
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
0
1
0
1
1
0
1
1
e
t
e
l
0
o
s
b
O
16/20
0
-10dB
u
d
o
-8dB
r
P
e
-6dB
-4dB
let
o
s
b
-2dB
-0dB
-0dB
O
)
2dB
4dB
1
8dB
1
s
(
t
c
0
10dB
Pr
0
1
12dB
0
0
14dB
0
0
1
146B
0
0
0
18dB
0
0
u
d
o
0
6dB
For example 12dB Treble and -8dB Bass give the following DATA BYTE: 0 0 1 1 1 0 0 1
TDA7348
Software specification
Table 12.
Volume
MSB
LSB
Function
D7
D5
D6
D4
D3
D2
D1
D0
0.31dB Fine attenuation steps
0
0
0dB
0
1
-0.31dB
1
0
-0.62dB
1
1
-0.94dB
1.25dB Coarse attenuation steps
0
0
0
0
0
1
0
1
0
0
1
1
b
O
0
0dB
0
0
1
-1.25dB
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
)
s
(
ct
1
let
r
P
e
o
s
b
-O
-3.75dB
-5dB
-6.25dB
-7.5dB
-8.75dB
10dB Gain / attenuation steps
20dB
10dB
0dB
-10dB
-20dB
0
1
-30dB
1
1
0
-40dB
1
1
1
-50dB
e
t
e
l
)
s
(
ct
u
d
o
-2.5dB
0
1
so
0
u
d
o
Pr
0
0
For example to select -47.81dB volume the data byte is: 1 1 0 1 1 0 0 1
Power on RESET: All bytes set to 1 1 1 1 1 1 1 0
17/20
Package information
5
TDA7348
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 6.
SO-28 mechanical, data and package dimensions
mm
DIM.
MIN.
TYP.
A
TYP.
0.104
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
0.5
17.7
18.1
0.697
E
10
10.65
0.394
e
1.27
16.51
F
7.4
L
0.4
d
o
r
0.419
)
(s
0.65
t
c
u
s
b
O
0.713
0.050
7.6
0.291
0.299
1.27
0.016
0.050
8 ° (max.)
r
P
e
t
e
l
o
0.020
D
P
e
u
d
o
45° (typ.)
e3
)
s
(
ct
OUTLINE AND
MECHANICAL DATA
MAX.
0.1
S
18/20
MIN.
a1
c1
s
b
O
MAX.
2.65
C
t
e
l
o
inch
SO-28
TDA7348
6
Revision history
Revision history
Table 13.
Document revision history
Date
Revision
Changes
14-Jan-2004
1
Initial release.
21-Jun-2004
2
Technical migration from ST-PRESS to EDOCS DMS
26-Jan-2007
3
DIP28 package removed, block diagram changed, layout modified.
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
19/20
TDA7348
)
s
(
ct
Please Read Carefully:
u
d
o
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
r
P
e
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
t
e
l
o
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
)
(s
s
b
O
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
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WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
t
c
u
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
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d
o
r
P
e
t
e
l
o
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
s
b
O
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
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20/20
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