TDA7401013TR

TDA7401 ® DIGITALLY CONTROLLED AUDIO PROCESSOR WITH LOUDSPEAKERS EQUALIZER FOUR HIGH PASS CHANNELS ONE STEREO LOW PASS CHANNEL WITH GAIN CONTROL DIRECT MUTE PIN FULLY PROGRAMMABLE VIA I2C BUS DESCRIPTION The TDA7401 is an upgrade of the TDA7435 audioprocessor. Due to a highly linear signal processing, using CMOS-switching techniques very low distortion and very low noise are obtained. Second order high pass and low pass filters with programmable corner frequencies provide the loudspeaker equalization. SO28 ORDERING NUMBER: TDA7401D Very low DC stepping is obtained by using a BICMOS technology. BLOCK DIAGRAM MUTE HP FL 1 HP FL 2 HP FR 1 HP FR 2 HP RL 1 HP RL 2 HP RR 1 HP RR 2 3 22 21 HP FILTER SDA SCL DGND AGND CREF 27 26 25 24 I2C BUS 19 17 12 11 MUTE 13 HP FILTER 16 15 28 10 HP FILTER 18 23 SUPPLY 20 VCC 14 HP FILTER 9 MUX AUX 1 IN L AUX 1 IN R HP FL OUT HP FR OUT HP RL OUT HP RR OUT AUX 2 OUT L AUX 2 OUT R 1 2 GAIN +20/-79dB 4 5 CR1 CL1 January 1999 8 OUT REF 7 CR2 6 CL2 D98AU822A 1/10 TDA7401 ABSOLUTE MAXIMUM RATINGS Symbol VS Tamb Tstg Parameter Value Unit Operating Supply Voltage Operating Ambient Temperature 10.5 -40 to 85 V °C Storage Temperature Range -55 to 150 °C PIN CONNECTION AUX 1 IN L 1 28 VCC AUX 1 IN R 2 27 SDA MUTE 3 26 SCL CR1 4 25 DGND CL1 5 24 AGND CL2 6 23 CREF CR2 7 22 HP FL 1 AUX 2 OUT R 8 21 HP FL 2 AUX 2 OUT L 9 20 HP FR 1 HP FL OUT 10 19 HP FR 2 HP FR OUT 11 18 HP RL 1 OUT REF 12 17 HP RL 2 HP RL OUT 13 16 HP RR 1 HP RR OUT 14 15 HP RR 2 D98AU823A THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction-pins Value Unit 65 °C/W QUICK REFERENCE DATA Symbol Parameter VS VCL Supply Voltage Max. input signal handling THD S/N Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio SC VREF Channel Separation f = 1KHz Reference Voltage Output (pin 12) 2/10 Min. Typ. Max. Unit 6 2.1 9 2.6 10.2 V Vrms 0.01 106 0.08 % dB -80 4.2 100 4.5 4.8 dB V TDA7401 ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10KΩ; Rg = 50Ω; Tamb = 25°C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit 37.5 2.1 80 50 2.6 100 62.5 KΩ VRMS dB INPUT STAGE: AUX1 RI VCL SI Input Resistance Clipping Level Input Separation d ≤ 0.3% GAIN CONTROL G MAX AMAX ASTEP EA ET VDC Maximum Input Gain Maximum Attenuation Step Resolution Attenuation Set Error Tracking Error DC Steps G = -20 to +20dB G = -60 to -20dB 1.5 +1.25 3 2 3 5 dB dB dB dB dB dB mV mV 30 4.5 100 4.8 Vrms KΩ Ω V 127.5 1 2.1 170 212.5 2.6 KΩ MΩ Vrms 80 100 dB 0.5 -1.25 -4 Adiacent Attenuation Steps From 0dB to GMIN 20 79 1 0 0.1 0.5 AUDIO OUTPUT (Pin 8 - 9, 10 - 14) Vclip RL RO VDC Clipping Level Output Load Resistance Output Impedance DC Voltage Level d = 0.3% AC coupled 2.1 2 4.2 2.6 STAGE: HP FILTER R1 R2 VCL Resistance at pin HP1 Resistance at pin HP2 Clipping Level HIGHPASS BYTE = XXXX1000 d ≤ 0.3% MUTE AMUTE Mute Attenuation VTHM Mute Threshold 1.2 1.7 2.2 V RINT Pullup Resistor (pin 3) 37.5 50 62.5 KΩ (note 1) GENERAL VCC Supply Voltage 6 9 10.2 V ICC Supply Current 7 8 9 mA 60 70 3.5 15 dB µV 5 15 µV 0.08 dB dB % 0.8 V PSRR eNO S/N SC d Power Supply Rejection Ratio Output Noise Signal to Noise Ratio Channel Separation Distortion f = 1KHz Non Inverting Output Muted (B = 20 to 20kHz flat) All Gains 0dB (B = 20 to 20kHz flat) All Gains = 0dB; VO = 1Vrms 80 VIN =1V 106 100 0.01 BUS INPUTS VIL Input Low Voltage VlH Input High Voltage IlN VO Input Current Output Voltage SDA Acknowledge 2.5 VIN = 0.4V IO = 1.6mA -5 0.1 V 5 0.4 µA V Note 1: Internal pullup resistor to 3.3V; "LOW" = mute active 3/10 TDA7401 Figure 1. HP Filter 56.5K 18.7K 9.4K 7.7K 56K 4.4K 3.6K 12.5K 100nF HP2 100nF + HP1 6.2K 3.5K 2.1K 3.8K 4.7K 9.4K 28K 28K R1 = EQUIVALENT RESISTANCE AT PIN HP1 R2 = EQUIVALENT RESISTANCE AT PIN HP2 D98AU836 Figure 2. Application Circuit µP HP FL IN 100nF 100nF HP FR IN 100nF 100nF HP FR 1 20 HP FR 2 19 18 HP RL 2 17 100nF 100nF HP RR 1 16 HP RR 2 15 HP FILTER 26 25 I2C BUS CREF 21 27 AGND 22 HP FL 2 HP RL 1 HP RL IN HP RR IN HP FL 1 SDA 3 DGND MUTE 100nF 100nF SCL 10µF 24 23 SUPPLY HP FILTER MUTE HP FILTER HP FILTER MUX 220nF AUX L IN AUX R IN 220nF AUX 1 IN L 1 AUX 1 IN R 2 VCC 4 100nF 5 7 CL1 CR2 100 100 nF nF 12 OUT REF 10 HP FL OUT 11 HP FR OUT 13 HP RL OUT 14 HP RR OUT 9 AUX L OUT 8 AUX R OUT 6 CL2 100nF 10µF 28 GAIN +20/-79dB CR1 4/10 VCC 100nF D98AU835 OUT REF HP FL OUT HP FR OUT HP RL OUT HP RR OUT AUX L OUT AUX R OUT TDA7401 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7401 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). Data Validity As shown in fig. 2, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.3 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions must be sent before each START condition. Byte Format Every byte transferred to the SDA line must con- tain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 4). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Figure 3. Data Validity on the I2CBUS Figure 4. Timing Diagram of I2CBUS Figure 5. Acknowledge on the I2CBUS 5/10 TDA7401 SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte,(the LSB bit determines CHIP ADDRESS MSB S 1 SUBADDRESS LSB 0 0 0 1 0 read/write transmission) A subaddress byte. A sequence of data (N-bytes + acknowledge) A stop condition (P) MSB 1 R/W ACK X X DATA 1 to DATA n LSB X I MSB X A2 A1 A0 ACK LSB DATA ACK = Acknowledge S = Start P = Stop I = Auto Increment X = Not used AUTO INCREMENT If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled SUBADDRESS (receive mode) MSB X 6/10 LSB X X I X FUNCTION D2 D1 D0 0 0 0 0 0 1 Not used Mode 0 0 1 1 1 0 0 1 0 Gain AUX 1 L Gain AUX 1 R High Pass Filter FL 1 1 1 0 1 1 1 0 1 High Pass Filter FR High Pass Filter RL High Pass Filter RR ACK P TDA7401 MODE MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 0 X 1 FUNCTION High Pass Mute ON High Pass Mute OFF 0 AUX1 Input Mute ON 1 AUX1 Input Mute OFF AUX2 Inverted Output 0 1 AUX2 Non Inv. Output AUX 2 Output Selection 0 0 High Pass Filter Front 0 1 High Pass Filter Rear 1 1 0 1 Aux 1 Input Mute AUX1 Low Pass Filter (C1 = C2 = 100nF) 0 0 0 1 Flat 120Hz 1 1 0 1 80Hz 50Hz GAIN AUX1L, AUX1R MSB LSB GAIN AUX1L, R D7 D6 D5 D4 D3 D2 D1 D0 1 : 1 1 1 : 1 1 0 0 : 0 0 : 0 0 0 : 0 0 0 : 0 0 0 0 : 0 0 : 1 1 0 : 0 0 0 : 0 0 0 0 : 0 0 : 0 0 1 : 1 1 0 : 0 0 0 0 : 0 1 : 0 0 1 : 0 0 1 : 0 0 0 0 : 1 0 : 1 1 1 : 0 0 1 : 0 0 0 0 : 1 0 : 1 1 1 : 0 0 1 : 0 0 0 0 : 1 0 : 1 1 1 : 1 0 1 : 1 0 0 1 : 1 0 : 0 1 +31dB : +17dB +16dB +15dB : +1dB 0dB 0dB -1dB : -15dB -16dB : -78dB -79dB X 1 1 X X X X X Mute Note: Is is not recommended to use a gain more than 20dB for system performance reason. In general, the max. gain should be limited by software to the maximum value, which is needed for the system. 7/10 TDA7401 HIGH PASS FILTERS MSB D7 LSB D6 D5 D4 D3 D2 D1 FL, FR, RL, RR D0 2nd order HP Filter Mode (C1 = C2 = 100nF) X X X X 0 0 0 0 fc = 40Hz 0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 0 fc = 60Hz fc = 80Hz fc = 100Hz 0 0 1 1 0 1 1 0 fc = 150Hz fc = 180Hz 0 1 1 1 fc = 220Hz fc = 120Hz First order HP Flat Mode 1 8/10 0 0 0 fc = 9Hz TDA7401 mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 2.65 MAX. 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 c1 0.020 45° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S OUTLINE AND MECHANICAL DATA SO28 8 ° (max.) 9/10 TDA7401 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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