TDA7429L
3 BAND EQUALIZER AUDIO PROCESSOR
WITH SUBWOOFER CONTR
1
FEATURES
■
3 STEREO INPUTS
■
AUXILIARY MONO INPUT
■
INPUT ATTENUATION CONTROL IN 0.5dB
STEP
■
TREBLE MIDDLE AND BASS CONTROL
–
Figure 1. Package
SDIP42
Table 1. Order Codes
FOUR SPEAKERS ATTENUATORS:
- 4 INDEPENDENT SPEAKERS CONTROL
IN 1dB STEPS FOR BALANCE FACILITY
- INDEPENDENT MUTE FUNCTION
■
SUBWOOFER OUTPUT (L+R) CONTROLLED
IN 1dB STEP INPUTS
■
ALL FUNCTIONS PROGRAMMABLE VIA
SERIAL BUS
2
DESCRIPTION
)
s
(
ct
2.2µF
BASSO_R
VAR_R
14
u
d
o
L+R OUTPUT
9
N.C.
1
N.C.
2
r
P
e
N.C.
t
e
l
o
bs
O
100nF
c
u
d
e
t
le
13
VAR_L
12
0.47µF
0.47µF
MONO INPUT
R_IN3
11
R_IN2
40
10
39
36
35
3
34
5
33
MIDDLE_LO
2.7K
L_IN3
MIDDLE_RO
MIDDLE_RI
0.47µF
0.47µF
0.47µF
10µF
100nF
22µF
41
24
CREF
220nF
HP2
37
15
19
100nF
BASS_LO
100nF
16
20
17
21
BASS_LI
BASS_RO
5.6K
100nF
100nF
22
18
32
31
30
AUXOUT_L AUXOUT_R L_OUT
June 2004
L_IN2
23
22nF
18nF
L_IN1
VS
18nF
MIDDLE_LI
0.47µF
MONITOR_L
8
MONITOR_R
2.7K
R_IN1
42
6
100nF
22nF
38
4
TREBLE_L
o
r
P
0.47µF
7
TREBLE_R
)
s
t(
o
s
b
O
-
N.C.
LP1
5.6nF
BASSO_L
SDIP42
N.C.
LP
100nF
2.2µF
Package
TDA7429L
applications in TV and Hi-Fi systems, providing also
an additional subwoofer control.
The AC signal setting is obtained by resistor networks
and switches combined with operational amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are obtained.
The TDA7429L is volume tone (bass middle and treble) balance (Left/Right) processors for quality audio
Figure 2. Test Circuit
Part Number
29
28
27
26
R_OUT
DIG_GND
SCL
SDA
25
AGND
BASS_RI
5.6K
D99AU1029
REV. 2
1/17
TDA7429L
Table 2. Absolute Maximum Ratings
Symbol
VS
Parameter
Operating Supply Voltage
Tamb
Operating Ambient Temperature
Tstg
Storage Temperature Range
Value
Unit
5.5
V
0 to 70
°C
-55 to 150
°C
Figure 3. Pin Description
N.C.
N.C.
N.C.
N.C.
LP
LP1
N.C.
HP2
L+R OUTPUT
MONO INPUT
VAR_L
BASSO_L
VAR_R
BASSO_R
BASS_LO
BASS_LI
BASS_RO
BASS_RI
MIDDLE_LO
MIDDLE_LI
MIDDLE_RO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Symbol
(t s)
Parameter
c
u
d
e
t
le
o
s
b
O
D99AU1028
Table 3. Quick Reference Data
VS
CREF
R_IN3
R_IN2
R_IN1
MONITOR_R
MONITOR_L
L_IN1
L_IN2
L_IN3
AUXOUT_L
AUXOUT_R
L_OUT
R_OUT
DIG_GND
SCL
SDA
AGND
TREBLE_L
TREBLE_R
MIDDLE_RI
c
u
d
)
s
t(
o
r
P
Min.
Typ.
Max.
Unit
7
9
10.2
V
VS
Supply Voltage
VCL
Max Input Signal Handling
THD
Total Harmonic Distortion V = 0.1Vrms f = 1KHz
0.01
S/N
Signal to Noise Ratio Vout = 1Vrms (mode = OFF)
106
dB
90
dB
o
r
P
e
t
e
l
o
SC
bs
O
2
Channel Separation f = 1KHz
VRMS
0.1
%
Treble Control (2dB step)
-14
14
dB
Middle Control (2dB step)
-14
14
dB
Bass Control (2dB step)
-14
14
dB
Balance Control 1dB step (LCH, RCH)
-79
0
dB
Mute Attenuation
100
dB
Table 4. Thermal Data
Symbol
Rth j-pin
2/17
Parameter
Thermal Resistance Junction-pins
Value
Unit
85
°C/W
R_IN3
0.47µF
R_IN2
0.47µF
R_IN1
0.47µF
L_IN3
0.47µF
L_IN2
0.47µF
L_IN1
50K
50K
50K
50K
50K
50K
37
MONITOR_R
42
31.5dB
control
31.5dB
control
VS
41
25
SUPPLY
+
HP2
22µF
8
Vref
6
LP1
LPF 1
5
100nF
LP
LPF 2
THE SWITCHES POSITION MATCHES THE RESET CONDITION
40
39
38
33
34
35
36
AGND
MONITOR_L
CREF
OFF
10
0.47µF
L+R OUTPUT
9
L+R
CONTROL
OFF
TREBLE
TREBLE
24
TREBLE_L
5.6nF
20
MIDDLE
MIDDLE
23
5.6nF
TREBLE_R
50K
OFF
22
2.7K
18nF
22nF
21
RM
REAR
SURR
3BAND
FIX
RB
17
SURR
REAR
FIX
3BAND
5.6K
100nF
c
u
d
100nF
BASSO_R
79dB CONTROL
MUTE
REC
ATT
MUTE
REC
ATT
12
BASSO_L
79dB CONTROL
I2C BUS DECODER + LATCHES
BASS
18
RB
15
BASS_LO
100nF
BASS_LI
BASS
16
5.6K
22nF 100nF
19
RM
2.7K
18nF
MIDDLE_LI
MIDDLE_RI
0.47µF
REARIN
MIDDLE_LO
o
r
P
BASS_RI
t
e
l
o
o
s
b
O
e
t
le
MIDDLE_RO
s
b
O
)
s
(
ct
BASS_RO
2.2µF
14
VAR_R
30K
FIX
VAR
30K
VAR_L
13
VAR
FIX
11
2.2µF
-
r
P
e
u
d
o
-
+
+
100nF
79dB CONTROL
MUTE
31
29
28
26
27
30
AUXOUT_R
R_OUT
DIG GND
SDA
SCL
L_OUT
AUXOUT_L
D99AU1030
SPKR
ATT
MUTE
SPKR
ATT
79dB CONTROL
32
TDA7429L
Figure 4. Block Diagram
)
s
t(
3/17
TDA7429L
Table 5. Electrical Characteristcs (refer to the test circuit Tamb = 25°C, VS = 9V, R L = 10KΩ,Vin = 1Vrms;
RG = 600Ω, all controls flat (G = 0dB), L+R CTRL = +4dB, MODE = OFF; f = 1KHz unless otherwise
specified).
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
VS
Supply Voltage
7
9
10.2
V
IS
Supply Current
10
18
26
mA
60
80
35
50
2
2.5
Vrms
31.5
dB
SVR
Ripple Rejection
LCH / RCH out, Mode = OFF
dB
INPUT STAGE
RIN
Input Resistance
VCL
Clipping Level
CRANGE
Control Range
THD = 0.3%
AVMIN
Min. Attenuation
-1
0
AVMAX
Max. Attenuation
31
31.5
ASTEP
Step Resolution
r
P
e
t
le
BASS CONTROL
Gb
Control Range
BSTEP
Step Resolution
RB
Max. Boost/cut
Internal Feedback Resistance
MIDDLE CONTROL
Gm
Control Range
MSTEP
Step Resolution
RM
Max. Boost/cut
du
Internal Feedback Resistance
o
r
P
e
TREBLE CONTROL
Gt
Control Range
Max. Boost/cut
t
e
l
o
TSTEP
Step Resolution
CONTROL L+R
bs
CRANGE
O
)
s
(
ct
o
s
b
O
-
SSTEP
65
1
od
uc
0.5
KΩ
)
s
t(
dB
32
dB
1
dB
±11.5
±14.0
±16.0
dB
1
2
3
dB
32
44
56
KΩ
±11.5
±14.0
±16.0
dB
1
2
3
dB
17.5
25
32.5
KΩ
±13.0
±14.0
±15.0
dB
1
2
3
dB
±4
dB
1.5
dB
Control Range
±11.5
Step Resolution
0.5
1
SPEAKER & AUX ATTENUATORS
CRANGE
Control Range
SSTEP
Step Resolution
EA
Attenuation set error
79
Av = 0 to -20dB
Av = -20 to -79dB
4/17
dB
-0.5
1
1.5
dB
-1.5
0
1.5
dB
-3
0
2
dB
TDA7429L
Table 5. Electrical Characteristcs (continued)
Symbol
VDC
Parameter
Test Condition
Min.
Typ.
Max.
Unit
-3
0
3
mV
Output Mute Condition
+70
100
Input Impedance
21
30
DC Steps
AMUTE
RVEA
adjacent att. steps
dB
39
KΩ
AUDIO OUTPUTS
NO(OFF)
d
SC
Output Noise (OFF)
Output Mute, Flat
BW = 20Hz to 20KHz
Distorsion
Av = 0 ; Vin = 1Vrms
0.01
Channel Separation
VOCL
Clipping Level
ROUT
Output Resistance
VOUT
DC Voltage Level
d = 0.3%
SC
Distorsion
Av = 0 ; Vin = 1Vrms
VOCL
Clipping Level
dB
2
2.5
Vrms
20
40
70
Ω
3.8
uc
V
ROUT
Output Resistance
VOUT
DC Voltage Level
70
d = 0.3%
so
BUS INPUTS
3
VIL
Input Low Voltage
VIH
Input High Voltage
IIN
Input Current
VO
Output Voltage SDA
Acknowledge
r
P
e
od
uc
(t s)
d
o
r
0.01
)
s
t(
0.1
%
90
dB
2
2.5
Vrms
20
50
b
O
-
85
4.5
Ω
V
1
3
-5
IO = 1.6mA
%
90
P
e
let
Channel Separation
0.1
70
MONITOR OUTPUTS
d
µVrms
µVrms
4
5
V
V
+5
mA
0.4
V
t
e
l
o
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7429L and viceversa takes place through the 2 wires I2C
BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be
connected).
s
b
O
3.1 Data Validity
As shown in fig. 5, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
3.2 Start and Stop Conditions
As shown in fig.6 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
5/17
TDA7429L
3.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
3.4 Acknowledge
The master (mP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 7).
The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock
pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the reception of each
byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.
3.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 5. Data validity on the I2C bus
c
u
d
SDA
SCL
DATA LINE
STABLE, DATA
VALID
Figure 6. Timing Diagram of I2C bus
)
s
(
ct
SCL
o
r
P
e
SDA
t
e
l
o
CHANGE
DATA
ALLOWED
o
r
P
e
t
le
so
D99AU1031
b
O
-
du
I2CBUS
D99AU1032
START
)
s
t(
STOP
Figure 7. Acknowledge on the I2C bus
s
b
O
SCL
1
2
3
7
8
9
SDA
MSB
START
6/17
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
TDA7429L
4
SOFTWARE SPECIFICATION
4.1 Interface Protocol
The interface protocol comprises:
■
A start condition (S)
■
A chip address byte, containing the TDA7429L address
■
A subaddress bytes
■
A sequence of data (N byte + achnowledge)
■
A stop condition (P)
Figure 8.
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
0
0
0
0
0
A
0
MSB
ACK
DATA 1 to DATA n
LSB
DATA
B
MSB
LSB
ACK
DATA
D95AU226A
5
c
u
d
EXAMPLES
)
s
t(
ACK
P
o
r
P
5.1 No Incremental Bus
The TDA7429L receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no incremental bus), N-datas (all these datas concern the subaddress selected), a stop condition.
e
t
le
Figure 9.
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
0
0
0
0
0
o
s
b
O
-
A
0
D95AU306
(s)
MSB
ct
ACK
0
u
d
o
X
X
LSB
DATA
MSB
X D3 D2 D1 D0 ACK
LSB
DATA
ACK
P
r
P
e
5.2 Incremental Bus
The TDA7429L receives a start condition, the correct chip address, a subaddress with the MSB = 1 (incremental
bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from
"1XXX1010" to "1XXX1111" of DATA are ignored.The DATA 1 concern thesubaddress sent, and the DATA 2
concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
t
e
l
o
s
b
O
Figure 10.
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
0
0
0
0
0
A
0
MSB
ACK
1
DATA 1 to DATA n
LSB
X
X
X D3 D2 D1 D0 ACK
MSB
LSB
DATA
ACK
P
D95AU307
7/17
TDA7429L
Table 6. Function Selection
The first byte (subaddress)
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
B1
X2
X
X
0
0
0
0
INPUT ATTENUATION
B
X
X
X
0
0
0
1
CONTROL OUT L+R &
SUBWOOFER
B
X
X
X
0
0
1
0
NOT USED
B
X
X
X
0
0
1
1
BASS & NATURAL BASE
B
X
X
X
0
1
0
0
MIDDLE & TREBLE
B
X
X
X
0
1
0
1
SPEAKER ATTENUATION "L“
B
X
X
X
0
1
1
1
AUX ATTENUATION "L”
B
X
X
X
1
0
0
0
AUX ATTENUATION"R”
X
X
X
1
0
0
1
INPUT MULTIPLEXER, & AUX OUT
B
B = 1 incremental bus; active
B = 0 no incremental bus;
X = indifferent 0,1
c
u
d
Table 7. Input Attenuation Selection
MSB
D7
LSB
D6
D5
D4
D3
e
t
le
o
r
P
INPUT ATTENUATION
D2
D1
D0
X
0
0
0
X
0
0
1
-0.5
X
0
1
0
-1
X
o
s
b
O
-
0
0
1
1
-1.5
1
0
0
-2
1
0
1
-2.5
1
1
0
-3
1
1
1
-3.5
(s)
X
ct
X
X
o
r
P
e
X
X
du
0.5 dB STEPS
4 dB STEPS
0
0
0
0
0
0
1
-4
0
1
0
-8
0
1
1
-12
X
1
0
0
-16
X
1
0
1
-20
X
1
1
0
-24
X
1
1
1
-28
t
e
l
o
X
X
s
b
O
X
)
s
t(
INPUT ATTENUATION = 0 ~ -31.5dB
D7
D6
X
0
8/17
D5
D4
D3
D2
D1
D0
L+R OUTPUT SWITCH
(L+R) OUTPUT PIN ACTIVE
TDA7429L
Table 8. Out & (L+R) & Subwoofer Selection
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
SUBWOOFER CONTROL
X
0
0
SUBWOOFER ON
X
0
1
NOT ALLOWED
X
1
0
SUBWOOFER OFF
X
1
1
NOT ALLOWED
OUT
X
0
X
1
VAR
FIX
L+R CONTROL
X
0
0
0
0
+4
X
0
0
0
1
+3
X
0
0
1
0
+2
X
0
0
1
1
+1
X
0
1
0
0
0
X
0
1
0
1
-1
X
0
1
1
0
X
0
1
1
1
X
1
0
0
0
X
1
0
0
1
X
1
0
1
0
X
1
0
1
1
X
1
1
0
0
X
1
1
0
1
X
1
1
1
0
X
1
1
1
1
)
s
(
ct
Table 9. Bass Selection
MSB
-7
-8
--9
-10
-11
BASS
D0
2 dB STEPS
0
0
0
0
-14
1
0
0
0
1
-12
1
0
0
1
0
-10
X
1
0
0
1
1
-8
X
1
0
1
0
0
-6
X
X
X
1
X
X
X
X
X
X
o
r
P
e
X
X
du
X
1
0
1
0
1
-4
bs
X
X
1
0
1
1
0
-2
X
X
1
0
1
1
1
0
X
X
X
1
1
1
1
1
0
X
X
X
1
1
1
1
0
2
X
X
X
1
1
1
0
1
4
X
X
X
1
1
1
0
0
6
X
X
X
1
1
0
1
1
8
X
X
X
1
1
0
1
0
10
X
X
X
1
1
0
0
1
12
X
X
X
1
1
0
0
0
14
X
O
X
X
-6
LSB
D4
X
o
s
b
O
-
-5
D1
D5
t
e
l
o
e
t
le
o
r
P
-4
D2
D6
X
-3
D3
D7
X
c
u
d
-2
)
s
t(
9/17
TDA7429L
Table 10. Speaker/Aux Att. R & L Selection
MSB
D7
D6
D5
D4
D3
LSB
SPEAKER/AUX ATT
D2
D1
D0
1 dB STEPS
X
0
0
0
0
X
0
0
1
-1
X
0
1
0
-2
X
0
1
1
-3
X
1
0
0
-4
X
1
0
1
-5
X
1
1
0
-6
X
1
1
1
-7
c
u
d
)
s
t(
8 dB STEPS
X
0
0
0
0
X
0
0
0
1
X
0
0
1
0
X
0
0
1
1
X
0
1
0
0
X
0
1
0
1
X
0
1
1
0
X
0
1
1
X
1
0
X
1
bs
X
10/17
-24
-32
-40
-48
0
0
-64
0
1
-72
u
d
o
-56
0
1
X
1
1
X
X
MUTE
Notes: 1. X = INDIFFERENT 0.1
2. SPAEAKER/AUX ATTENUATION = 0dB to 79dB
O
-16
1
1
0
-8
ct
r
P
e
t
e
l
o
X
(s)
o
s
b
O
-
e
t
le
o
r
P
0
TDA7429L
Table 11. Middle & Treble Selection
MSB
D7
D6
D5
D4
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
1
0
1
du
0
1
o
r
P
e
MIDDLE
D3
D2
D1
D0
2 dB STEPS
0
0
0
0
-14
0
0
0
1
-12
0
0
1
0
-10
0
0
1
1
-8
0
1
0
0
-6
0
1
0
1
-4
0
1
1
0
-2
0
1
1
1
0
1
1
1
1
0
1
1
1
0
2
1
1
0
1
4
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
0
0
ct
(s)
o
s
b
O
-
0
ro
10
12
14
TREBLE
2 dB STEPS
-14
-12
-10
-8
-6
-4
0
-2
1
1
0
1
1
0
1
1
0
2
1
0
1
4
1
1
0
0
6
1
0
1
1
8
1
0
1
0
10
1
0
0
1
12
1
0
0
0
14
t
e
l
o
1
s
b
O
1
1
1
)
s
t(
8
P
e
let
1
c
u
d
6
1
1
0
0
LSB
11/17
TDA7429L
Table 12. Input/recout L & R Selection
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
INPUT MULTIPLEXER
X
1
1
0
IN1
X
0
0
0
IN2
X
0
1
0
IN3
AUX OUT "L”
X
0
0
0
VAR 1 (3BAND)
X
0
1
0
NOT ALLOWED
X
1
0
0
VAR 3 (REAR)
X
1
1
0
FIX
)
s
t(
AUX OUT "R”
X
0
0
0
VAR 1 (3BAND)
X
0
1
0
NOT ALLOWED
X
1
0
0
X
1
1
0
e
t
le
)
s
(
ct
Table 13. Power on reset
BASS & MIDDLE
TREBLE
o
r
P
e
du
o
r
P
VAR 3 (REAR)
o
s
b
O
2dB
0dB
SURROUND & OUT CONTROL + (L+R) CONTROL
OFF + FIX + MAX. ATTENUATION
SPEAKER/AUX ATTENUATION L & R
MUTE
t
e
l
o
INPUT ATTENUATION + (L+R) SWITCH
MAX. ATTENUATION + ON
NATURAL BASE
OFF
bs
INPUT
O
12/17
IN1
c
u
d
FIX
TDA7429L
Figure 11. Pin: TREBLE-L, TREBLE-R
Figure 14. Pin: CREF
VS
VS
20µA
20µA
20K
42K
25K
20K
GND
D95AU336
GND
D95AU309
Figure 12. Pin: VOUT REF
Figure 15. Pin: VAR-L, VAR-R
VS
c
u
d
VS
20µA
e
t
le
o
r
P
)
s
t(
20µA
SW
GND
D95AU233A
10K
)
s
(
ct
GND
Figure 13. Pin: L-IN, R-IN, L-IN2, R-IN2, L-IN3,
R-IN3, L-IN4, R-IN4
u
d
o
r
P
e
VS
t
e
l
o
s
b
O
o
s
b
O
-
30K
GND Vref
D95AU227
Figure 16. Pin: LP1, LP
VS
20µA
20µA
10K
50K
GND
GND
VREF
D94AU200
HP1
D94AU211
13/17
TDA7429L
Figure 20. Pin: BASS-LI, BASS-RI, MIDDLE-LI,
MIDDLE-R
Figure 17. Pin: SCL, SDA
VS
20µA
20µA
45K : Bass
or
25K : MIDDLE
GND
GND
BASS-LO
D94AU205
BASS-RO,MIDDLE-LO,MIDDLE-RO
Figure 18. Pin: MONO INPUT
D95AU231A
)
s
t(
Figure 21. Pin: BASS-LO, BASS-RO, MIDDLELO,MIDDLE-RO
c
u
d
VS
20µA
VS
e
t
le
SW
50K
GND Vref
D95AU229
)
s
(
ct
o
s
b
O
-
Figure 19. Pin: L-OUT, R-OUT, MONITOR-L,
MONITOR-R, LTR OUTPUT, BASSO-L,
BASSO-R, AUXOUT_L, AUXOUT_R
u
d
o
VS
t
e
l
o
r
P
e
s
b
O
20µA
GND
D95AU230
14/17
o
r
P
20µA
(*)
GND
BASS-LI,BASS-RI,MIDDLE-LI,MIDDLE-RI
(*) 45K : Bass
25K : MIDDLE
D95AU232
TDA7429L
Figure 22. SDIP42 Mechanical Data & Package Dimensions
mm
TYP.
MAX.
A
MIN.
TYP.
5.08
0.20
A1
0.51
A2
3.05
3.81
4.57
0.120
B
0.38
0.46
0.56
0.0149 0.0181 0.0220
B1
0.89
1.02
1.14
0.035
c
0.23
0.25
0.38
0.0090 0.0098 0.0150
D
36.58
36.83
37.08
1.440
E
15.24
16.00
0.60
E1
12.70
14.48
0.50
0.020
13.72
0.150
0.040
1.450
0.180
0.045
1.460
0.629
0.540
e
1.778
0.070
e1
15.24
0.60
0.570
e2
18.54
0.730
e3
1.52
0.060
L
2.54
3.30
3.56
0.10
0.130
s
b
O
42
o
r
P
o
s
b
O
-
E
E1
L
r
P
e
e
t
le
)
s
t(
SDIP42 (0.600")
A1
u
d
o
c
u
d
0.140
)
s
(
ct
t
e
l
o
OUTLINE AND
MECHANICAL DATA
MAX.
A2
MIN.
inch
A
DIM.
B
B1
e
e1
e2
D
c
E
22
.015
0,38
Gage Plane
1
e3
21
e2
SDIP42
15/17
TDA7429L
Table 14. Revision History
Date
Revision
Description of Changes
January 2004
2
First Issue in EDOCS DMS
June 2004
3
Changed the Style-sheet in compliance to the new “Corporate Technical
Pubblications Design Guide”
c
u
d
e
t
le
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
s
b
O
16/17
o
s
b
O
-
o
r
P
)
s
t(
TDA7429L
c
u
d
e
t
le
)
s
(
ct
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
s
b
O
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All other names are the property of their respective owners
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