TDA7429S

TDA7429 DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX 1 FEATURES ■ 3 STEREO INPUTS ■ INPUT ATTENUATION CONTROL IN 0.5dB STEP Figure 1. Package ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( 2 DESCRIPTION s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O ■ TREBLE MIDDLE AND BASS CONTROL ■ THREE SURROUND MODES ARE AVAILABLE SDIP42 Table 1. Order Codes – MUSIC: 4 SELECTABLE RESPONSES – MOVIE AND SIMULATED: 256 SELECTABLE RESPONSES ■ FOUR SPEAKERS ATTENUATORS: – 4 INDEPENDENT SPEAKERS CONTROL IN 1dB STEPS FOR BALANCE FACILITY Part Number Package TDA7429S SDIP42 TDA7429T TQFP44 TDA7429T13TR Tape & Reel It reproduces surround sound by using programmable phase shifters and a signal matrix. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained. – INDEPENDENT MUTE FUNCTION ■ TQFP44 ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS The TDA7429 is volume tone (bass middle and treble) balance (Left/Right) processors for quality audio applications in TV and Hi-Fi systems. June 2004 CREF R_IN4 R_IN3 R_IN2 R_IN1 42 VS PS2 43 PS3 PS1 44 PS4 LP Figure 2. Pin Connection (TQFP44) 41 40 39 38 37 36 35 34 30 L_IN2 5 29 L_IN3 VAR_L 6 28 L_IN4 BASSO_L 7 27 AUXOUT_L VAR_R 8 26 AUXOUT_R BASSO_R 9 25 L_OUT BASS_LO 10 24 R_OUT BASS_LI 11 23 DIG_GND 12 13 14 15 16 17 18 19 20 21 22 SCL 4 REARIN SDA REAROUT AGND L_IN1 TREBLE_L 31 TREBLE_R 3 MIDDLE_RI MONITOR_L HP2. MIDDLE_RO 32 MIDDLE_LI 2 MIDDLE_LO 33 HP1 BASS_RI 1 BASS_RO LP1 MONITOR_R D96AU532 REV. 6 1/22 TDA7429 Figure 3. PIN CONNECTION (SDIP42) PS4 PS3 PS2 PS1 LP LP1 HP1 HP2 REAROUT REARIN VAR_L BASSO_L VAR_R BASSO_R BASS_LO BASS_LI BASS_RO BASS_RI MIDDLE_LO MIDDLE_LI MIDDLE_RO 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 VS CREF R_IN3 R_IN2 R_IN1 MONITOR_R MONITOR_L L_IN1 L_IN2 L_IN3 AUXOUT_L AUXOUT_R L_OUT R_OUT DIG_GND SCL SDA AGND TREBLE_L TREBLE_R MIDDLE_RI ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O D97AU623 Table 2. Absolute Maximum Ratings Symbol VS Parameter Operating Supply Voltage Tamb Operating Ambient Temperature Tstg Storage Temperature Range Value Unit 11 V 0 to 70 °C -55 to 150 °C Table 3. Quick Reference Data Symbol Parameter Min. Typ. Max. Unit 9 10.2 V VS Supply Voltage 7 VCL Max Input Signal Handling 2 THD Total Harmonic Distortion V = 0.1Vrms f = 1KHz 0.01 S/N Signal to Noise Ratio Vout = 1Vrms (mode = OFF) 106 dB SC Channel Separation f = 1KHz 90 dB VRMS 0.1 % Treble Control (2dB step) -14 14 dB Middle Control (2dB step) -14 14 dB Bass Control (2dB step) -14 14 dB Balance Control 1dB step (LCH, RCH) -79 0 dB Mute Attenuation 100 dB Table 4. Thermal Data Symbol Rth j-pin 2/22 Parameter Thermal Resistance Junction-pins Value Unit 85 °C/W TDA7429 Figure 4. TEST CIRCUIT (TDA7429S) 2.2µF 2.2µF 2.2µF 0.47µF 0.47µF BASSO_R 22nF PS4 22nF PS3 4.7nF PS2 100nF PS1 1.2nF LP 5.6nF LP1 VAR_R 14 BASSO_L 13 VAR_L 12 REAROUT 9 11 R_IN2 R_IN3 REARIN 10 39 40 1 36 2 MONITOR_L 0.47µF L_IN3 33 5 0.47µF L_IN2 34 4 0.47µF L_IN1 35 3 0.47µF R_IN1 38 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 5.6nF TREBLE_R 5.6nF TREBLE_L 6 VS 42 23 10µF 24 MONITOR_R 22nF MIDDLE_LO 220nF 37 100nF 15 MIDDLE_LI 100nF 16 20 22nF 18nF MIDDLE_RO MIDDLE_RI 2.7K BASS_LO 19 18nF 2.7K CREF 41 100nF 100nF 22µF BASS_LI BASS_RO 17 21 5.6K 100nF 100nF 22 18 32 31 30 AUXOUT_L AUXOUT_R L_OUT 29 28 27 26 R_OUT DIG_GND SCL SDA 8 25 AGND HP2 BASS_RI 7 5.6K HP1 D97AU626 680nF Figure 5. TEST CIRCUIT (TDA7429T) 2.2µF BASSO-R 22nF PS4 22nF PS3 4.7nF PS2 100nF PS1 1.2nF LP 5.6nF LP1 5.6nF TREBLE-R 5.6nF TREBLE-L 2.2µF VAR-R 9 BASSO-L 8 2.2µF VAR-L 7 REAROUT 4 6 0.47µF 0.47µF R-IN4 R-IN3 REARIN 5 37 0.47µF R-IN2 36 35 40 34 32 41 31 42 30 43 29 44 28 1 22nF MIDDLE-LO MIDDLE-LI 2.7K MIDDLE-RO MIDDLE-RI L-IN1 L-IN2 L-IN3 L-IN4 0.47µF 0.47µF 0.47µF 0.47µF 10µF 19 38 CREF 100nF 22µF 220nF 33 100nF 10 14 BASS-LO 100nF 11 15 22nF 18nF MONITOR_L 39 18 18nF 2.7K 0.47µF VS 100nF MONITOR_R R-IN1 12 16 BASS-LI BASS-RO 5.6K 100nF 100nF 17 13 27 26 25 24 23 22 21 AUXOUT-L AUXOUT-R L-OUT R-OUT DIG-GND SCL SDA 3 20 AGND HP2 2 BASS-RI 5.6K HP1 D96AU533 680nF 3/22 L-IN1 R-IN4 0.47µF R-IN3 0.47µF R-IN2 0.47µF R-IN1 0.47µF L-IN4 0.47µF L-IN3 0.47µF L-IN2 0.47µF 37 36 35 34 28 29 30 31 33 MONITOR R 31.5dB control 31.5dB 1 control 3 2 + 39 VS RLP1 RHP1 HP1 LP1 20 38 SUPPLY + - R6 R5 HP2 THE SWITCHES POSITION MATCHES THE RESET CONDITION 50K 50K 50K 50K 50K 50K 50K 50K 32 MONITOR L AGND 0.47µF Vref L-R 22µF + - + - CREF LP 44 MOVIE/ MUSIC SIM 1.2nF 5 2.2µF 4 MOVIE/SIM 50K MIXING AMP 5.6nF 18 MIDDLE TREBLE 5.6nF 2.7K 18nF 22nF 16 REAR SURR 3BAND FIX RB 5.6K 100nF REAR 100nF 12 SURR FIX 3BAND BASSO-R 79dB CONTROL MUTE REC ATT MUTE REC ATT 7 BASSO-L 79dB CONTROL I2C BUS DECODER + LATCHES BASS 13 RB 10 BASS-LO 100nF BASS-LI BASS 11 5.6K 22nF 100nF 14 RM MIDDLE 17 15 RM 2.7K 18nF TREBLE TREBLE-R SURR SURR 19 TREBLE-L OFF OFF 40 MIXING AMP PS4 400Hz PS4 PS3 400Hz 41 RPS4 PS3 22nF RPS3 MUSIC 42 EFFECT CONTROL OFF PS2 4KHz PS1 90Hz PS2 RPS2 LPF 9KHz 43 RPS1 PS1 22nF REAROUT 4.7nF REARIN MIDDLE-LI MIDDLE-RI 100nF BASS-RI MIDDLE-LO MIDDLE-RO 680nF BASS-RO 2.2µF 9 30K FIX VAR 30K VAR-L VAR-R 8 VAR FIX 6 2.2µF - 4/22 - + + ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 5.6nF 79dB CONTROL MUTE SPKR ATT MUTE SPKR ATT 79dB CONTROL AUXOUT-R R-OUT DIG GND SDA SCL L-OUT AUXOUT-L D96AU513 26 24 23 21 22 25 27 TDA7429 Figure 6. Block Diagram (TDA7429T) R_IN3 0.47µF R_IN2 0.47µF R_IN1 0.47µF L_IN3 0.47µF L_IN2 0.47µF L_IN1 40 39 38 33 34 35 37 MONITOR_R 31.5dB control 31.5dB control + 42 25 8 7 VS 41 SUPPLY + - R6 R5 HP2 HP1 RLP1 RHP1 6 LP1 THE SWITCHES POSITION MATCHES THE RESET CONDITION 50K 50K 50K 50K 50K 50K 36 MONITOR_L Vref L-R 22µF + - + - CREF 0.47µF AGND LP 5 MOVIE/ MUSIC SIM 1.2nF 10 2.2µF 9 MOVIE/SIM 50K MIXING AMP 5.6nF 23 MIDDLE TREBLE 5.6nF 2.7K 18nF 22nF 21 REAR SURR 3BAND FIX RB 5.6K 100nF REAR 100nF 17 SURR FIX 3BAND BASSO_R 79dB CONTROL MUTE REC ATT MUTE REC ATT 12 BASSO_L 79dB CONTROL I2C BUS DECODER + LATCHES BASS 18 RB 15 BASS_LO 100nF BASS_LI BASS 16 5.6K 22nF 100nF 19 RM MIDDLE 22 20 RM 2.7K 18nF TREBLE TREBLE_R SURR SURR 24 TREBLE_L OFF OFF 1 MIXING AMP PS4 400Hz PS4 PS3 400Hz 2 RPS4 PS3 22nF RPS3 MUSIC 3 EFFECT CONTROL OFF PS2 4KHz PS1 90Hz PS2 RPS2 LPF 9KHz 4 RPS1 PS1 22nF REAROUT 4.7nF REARIN MIDDLE_LI MIDDLE_RI 100nF BASS_RI MIDDLE_LO MIDDLE_RO 680nF BASS_RO 2.2µF 14 VAR_R 30K FIX VAR 30K VAR_L 13 VAR FIX 11 2.2µF - + + ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 5.6nF 79dB CONTROL MUTE 31 29 28 26 27 30 AUXOUT_R R_OUT DIG GND SDA SCL L_OUT AUXOUT_L D97AU624A SPKR ATT MUTE SPKR ATT 79dB CONTROL 32 TDA7429 Figure 7. Block Diagram (TDA7429S) 5/22 TDA7429 Table 5. Electrical Characteristcs (refer to the test circuit Tamb = 25°C, VS = 9V, R L = 10KΩ, Vin = 1Vrms; RG = 600Ω, all controls flat (G = 0dB), L+R CTRL = +4dB, MODE = OFF; f = 1KHz unless otherwise specified). Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VS Supply Voltage 7 9 10.2 V IS Supply Current 10 18 26 mA 60 80 35 50 2 2.5 SVR Ripple Rejection LCH / RCH out, Mode = OFF dB INPUT STAGE RIN Input Resistance VCL Clipping Level CRANGE Control Range AVMIN Min. Attenuation AVMAX Max. Attenuation ASTEP Step Resolution THD = 0.3% Pr 31 uc od 31.5 -1 ) s ( t 65 0 31.5 1 e t e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O uc 0.5 BASS CONTROL Gb Control Range BSTEP RB Max. Boost/cut KΩ Vrms dB ) s t( dB 32 dB 1 dB ±11.5 ±14.0 ±16.0 dB Step Resolution 1 2 3 dB Internal Feedback Resistance 32 44 56 KΩ ±11.5 ±14.0 ±16.0 dB 1 2 3 dB 17.5 25 32.5 KΩ ±13.0 ±14.0 ±15.0 dB 1 2 3 dB -6 dB MIDDLE CONTROL Gm Control Range MSTEP Step Resolution RM Max. Boost/cut Internal Feedback Resistance TREBLE CONTROL Gt Control Range TSTEP Step Resolution Max. Boost/cut EFFECT CONTROL CRANGE Control Range -21 SSTEP Step Resolution 0.5 1 1.5 dB SURROUBND SOUBND MATRIX PHASE RPS10 Phase Shifter 1: D1 = 0, D0 = 0 8.3 11.8 15.2 KΩ RPS11 Phase Shifter 1: D1 = 0, D0 = 1 10 14.1 18.3 KΩ RPS12 Phase Shifter 1: D1 = 1, D0 = 0 12.6 17.9 23.3 KΩ RPS13 Phase Shifter 1: D1 = 1, D0 = 1 26.4 37.3 48.85 KΩ RPS20 Phase Shifter 2: D3 = 0, D2 = 0 4 5.6 7.2 KΩ 6/22 TDA7429 Symbol Parameter Test Condition Min. Typ. Max. Unit SURROUND SOUND MATRIX TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1 RPS21 Phase Shifter 2: D3 = 0, D2 = 1 4.8 6.8 8.7 KΩ RPS22 Phase Shifter 2: D3 = 1, D2 = 0 6 8.4 10.9 KΩ RPS23 Phase Shifter 2: D3 = 1, D2 = 1 12.9 18.3 23.7 KΩ RPS30 Phase Shifter 3: D5 = 0, D4 = 0 8.5 12.1 15.6 KΩ RPS31 Phase Shifter 3: D5 = 0, D4 = 1 10.2 14.5 18.7 KΩ ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O RPS32 Phase Shifter 3: D5 = 1, D4 = 0 12.7 18.1 23.3 KΩ RPS33 Phase Shifter 3: D5 = 1, D4 = 1 27.4 39.1 50.75 KΩ RPS40 Phase Shifter 4: D7 = 0, D6 = 0 8.5 12.1 15.6 KΩ RPS41 Phase Shifter 4: D7 = 0, D6 = 1 10.2 14.5 18.7 KΩ RPS42 Phase Shifter 4: D7 = 1, D6 = 0 12.7 18.1 23.3 KΩ RPS43 Phase Shifter 4: D7 = 1, D6 = 1 27.4 39.1 50.75 KΩ GOFF In-phase Gain (OFF) Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin → Rout , Lin → Lout -1 0 1 dB DGOFF LR In-phase Gain Difference (OFF) Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin → Rout , Lin → Lout -1 0 1 dB GMOV In-phase Gain (Movie) Movie mode, Effect Ctrl = -6dB 1kHz, 1.4 Vp-p, Rin → Rout , Lin → Lout 8 dB DGMOV LR In-phase Gain Difference (Movie) Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) - (Lin → Lout) 0 dB GMUS In-phase Gain (Music) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) , (Lin → Lout) 7 dB DGMUS LR In-phase Gain Difference (Music) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) , (Lin → Lout) 0 dB LMON1 Simulated L Output 1 Simulated Mode, Effect Ctrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin → Lout 4.5 dB LMON2 Simulated L Output 2 Simulated Mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin → Lout –4.0 dB LMON3 Simulated L Output 3 Simulated Mode, Effect Ctrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin → Lout 7.0 dB RMON1 Simulated R Output 1 Simulated Mode, Effect Ctrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin → Rout – 4.5 dB 7/22 TDA7429 Symbol Parameter Test Condition Min. Typ. Max. Unit RMON2 Simulated R Output 2 Simulated Mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin → Rout 3.8 dB RMON3 Simulated R Output 3 Simulated Mode, Effect Ctrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin → Rout – 20 dB RLP1 Low Pass Filter Resistance 7 10 13 KΩ RHPI High Pass Filter Resistance 42 60 78 KΩ RLPF LP Pin Impedance 7 10 13 KΩ ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O SPEAKER & AUX ATTENUATORS CRANGE Control Range SSTEP Step Resolution EA VDC AMUTE RVEA 79 dB -0.5 1 1.5 dB -1.5 0 1.5 dB Av = -20 to -79dB -3 0 2 dB adjacent att. steps -3 0 3 mV Output Mute Condition +70 100 Input Impedance 21 30 Attenuation set error DC Steps Av = 0 to -20dB dB 39 KΩ AUDIO OUTPUTS NO(OFF) Output Noise (OFF) Output Mute, Flat BW = 20Hz to 20KHz 4 5 µVrms µVrms NO(MOV) Output Noise (Movie) Mode = Movie BW = 20Hz to 20KHz 30 µVrms NO(Mus) Output Noise (Music) Mode = Music BW = 20Hz to 20KHz 30 µVrms Mode Simulated BW = 20Hz to 20KHz 30 µVrms NO(MON) Output Noise (Simulated) d SC Distorsion Av = 0 ; Vin = 1Vrms Channel Separation VOCL Clipping Level ROUT Output Resistance VOUT DC Voltage Level d = 0.3% 0.01 0.1 % 70 90 dB 2 2.5 Vrms 25 50 85 3.8 Ω V MONITOR OUTPUTS d SC Distorsion Channel Separation VOCL Clipping Level ROUT Output Resistance VOUT DC Voltage Level 8/22 Av = 0 ; Vin = 1Vrms d = 0.3% 0.01 0.1 % 70 90 dB 2 2.5 Vrms 20 50 4.5 85 Ω V TDA7429 Symbol Parameter Test Condition Min. Typ. Max. Unit 1 V BUS INPUTS 3 VIL Input Low Voltage VIH Input High Voltage 3 IIN Input Current -5 VO Output Voltage SDA Acknowledge IO = 1.6mA V +5 mA 0.4 V I2C BUS INTERFACE ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Data transmission from microprocessor to the TDA7429 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data Validity As shown in fig. 8, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and Stop Conditions As shown in fig.9 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 3.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The master (mP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 10). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 3.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. 9/22 TDA7429 Figure 8. Data validity on the I2C bus SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 9. Timing Diagram of I2C bus ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s ( 4 SOFTWAREP SPECIFICATION t c e t u e l d o o r s P b O e t e l o s b O SCL I2CBUS SDA D99AU1032 START STOP Figure 10. Acknowledge on the I2C bus SCL 1 2 3 7 8 9 SDA MSB START ACKNOWLEDGMENT FROM RECEIVER D99AU1033 4.1 Interface Protocol The interface protocol comprises: ■ A start condition (S) ■ A chip address byte, containing the TDA7429 address ■ A subaddress bytes ■ A sequence of data (N byte + achnowledge) ■ A stop condition (P) Figure 11. CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 D95AU226A 10/22 0 0 A 0 MSB ACK B DATA 1 to DATA n LSB DATA MSB ACK LSB DATA ACK P TDA7429 5 EXAMPLES 5.1 No Incremental Bus The TDA7429 receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no incremental bus), N-datas (all these datas concern the subaddress selected), a stop condition. Figure 12. SUBADDRESS CHIP ADDRESS MSB S 1 LSB 0 0 0 0 0 A 0 MSB ACK 0 DATA LSB X X MSB X D3 D2 D1 D0 ACK LSB DATA ACK ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c 6 DATA BYTES u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O P D95AU306 5.2 Incremental Bus The TDA7429 receives a start condition, the correct chip address, a subaddress with the MSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "1XXX1010" to "1XXX1111" of DATA are ignored.The DATA 1 concern thesubaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. Figure 13. CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 0 0 A 0 MSB ACK 1 DATA 1 to DATA n LSB X X MSB X D3 D2 D1 D0 ACK LSB DATA ACK P D95AU307 Address = 80(HEX) 6.1 Function Selection Table 6. The first byte (Subaddress) MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 B X X X 0 0 0 D0 0 INPUT ATTENUATION B X X X 0 0 0 1 SURROUND & OUT & EFFECT CONTROL B X X X 0 0 1 0 PHASE RESISTOR B X X X 0 0 1 1 BASS & NATURAL BASE B X X X 0 1 0 0 MIDDLE & TREBLE B X X X 0 1 0 1 SPEAKER ATTENUATION "L" B X X X 0 1 1 0 SPEAKER ATTENUATION "R" B X X X 0 1 1 1 AUX ATTENUATION "L" B X X X 1 0 0 0 AUX ATTENUATION"R" B X X X 1 0 0 1 INPUT MULTIPLEXER, & AUX OUT B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1 11/22 TDA7429 Table 7. INPUT ATTENUATION SELECTION MSB D7 D6 D5 D4 D3 LSB INPUT ATTENUATION D2 D1 D0 0.5 dB STEPS X 0 0 0 0 X 0 0 1 -0.5 X 0 1 0 -1 X 0 1 1 -1.5 X 1 0 0 -2 X 1 0 1 -2.5 X 1 1 0 -3 X 1 1 1 -3.5 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 4 dB STEPS X 0 0 0 0 X 0 0 1 -4 X 0 1 0 -8 X 0 1 1 -12 X 1 0 0 -16 X 1 0 1 -20 X 1 1 0 -24 X 1 1 1 -28 D4 D3 INPUT ATTENUATION = 0 ~ -31.5dB Table 8. D7 D6 X 0 D5 D2 D1 D0 REAR SWITCH REARIN, REAROUT PIN ACTIVE X 12/22 1 NO REARIN, REAROUT PIN TDA7429 Table 9. SURROUND SELECTION MSB D7 X X X X D6 D5 D4 D3 X X D2 D1 0 0 1 1 LSB D0 0 1 0 1 0 1 SURROUND MODE SIMULATED MUSIC OFF MOVIE OUT VAR FIX EFFECT CONTROL -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Table 10. PHASE RESISTOR SELECTION MSB D7 LSB D6 D5 0 0 1 1 0 0 1 1 0 1 0 1 D4 0 1 0 1 D3 D2 0 0 1 1 0 1 0 1 D1 0 0 1 1 D0 0 1 0 1 SURROUND PHASE RESISTOR PHASE SHIFT 1 (KΩ) 12 14 18 37 PHASE SHIFT 2 (KΩ) 6 7 8 18 PHASE SHIFT 3 (KΩ) 12 14 18 39 PHASE SHIFT 4 (KΩ) 12 14 18 39 13/22 TDA7429 Table 11. BASS SELECTION MSB D7 X X X X X X X X X X X X X X X X LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 BASS 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 LSB SPEAKER/AUX ATT D0 0 1 dB STEPS 0 0 1 -1 1 0 -2 0 1 1 0 1 0 -3 -4 X 1 0 1 -5 X X 1 1 1 1 0 1 -6 -7 D6 X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X D4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 D2 0 D1 0 X 0 X 0 X X ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Table 12. SPEAKER/AUX ATT. R & L SELECTION MSB D7 X D6 D5 D4 D3 8 dB STEPS X X 0 0 0 0 0 0 0 1 0 -8 X 0 0 1 0 -16 X X 0 0 0 1 1 0 1 0 -24 -32 X 0 1 0 1 -40 X 0 1 1 0 -48 X X 0 1 1 0 1 0 1 0 -56 -64 X 1 0 0 1 -72 X 1 0 1 X X 1 1 X X MUTE X = INDIFFERENT 0,1 SPEAKER/AUX ATTENUATION = 0dB ~ -79dB 14/22 TDA7429 Table 13. MIDDLE & TREBLE SELECTION MSB D7 D6 D5 D4 LSB MIDDLE D3 D2 D1 D0 2 dB STEPS 0 0 0 0 -14 0 0 0 1 -12 0 0 1 0 -10 0 0 1 1 -8 0 1 0 0 -6 0 1 0 1 -4 0 1 1 0 -2 0 1 1 1 0 1 1 1 1 0 1 1 1 0 2 1 1 0 1 4 1 1 0 0 6 1 0 1 1 8 1 0 1 0 10 1 0 0 1 12 1 0 0 0 14 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O TREBLE 2 dB STEPS 0 0 0 0 -14 0 0 0 1 -12 0 0 1 0 -10 0 0 1 1 -8 0 1 0 0 -6 0 1 0 1 -4 0 1 1 0 -2 0 1 1 1 0 1 1 1 1 0 1 1 1 0 2 1 1 0 1 4 1 1 0 0 6 1 0 1 1 8 1 0 1 0 10 1 0 0 1 12 1 0 0 0 14 15/22 TDA7429 Table 14. INPUT/RECOUT L & R SELECTION MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 INPUT MULTIPLEXER X 0 0 0 IN2 X 0 1 0 IN3 X 1 0 0 IN4 X 1 1 0 IN1 AUX OUT "L" X 0 0 0 VER 1 (3BAND) X 0 1 0 VER 2 (SURR) X 1 0 0 VER 3 (REAR) X 1 1 0 FIX ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O AUX OUT "R" X 0 0 0 VER 1 (3BAND) X 0 1 0 VER 2 (SURR) X 1 0 0 VER 3 (REAR) X 1 1 0 FIX Table 15. POWER ON RESET BASS & MIDDLE 2dB TREBLE 0dB SURROUND & OUT CONTROL+ EFFECT CONTROL OFF + FIX + MAX ATTENUATION SPEAKER/AUX ATTENUATION L &R MUTE INPUT ATTENUATION + REAR SWITCH MAX ATTENUATION + ON NATURAL BASE OFF INPUT IN1 Figure 14. PIN: VOUT REF Figure 15. PIN: TREBLE-L, TREBLE-R VS VS 20µA 20µA 25K GND GND D95AU233A 10K GND D95AU309 16/22 TDA7429 Figure 16. PIN: HP1 LP1 Figure 19. PIN: L-IN, R-IN, L-IN2, R-IN2, L-IN3, R-IN3, L-IN4, R-IN4, VS VS 10K 20µA 60K 50K ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O GND HP2 GND D94AU198 VREF D94AU200 Figure 20. PIN: LP1 Figure 17. PIN: HP2 VS VS 20µA 20µA 5.5K 60K 10K HP1 GND 5.5K GND D94AU199 HP1 D94AU211 Figure 21. PIN: CREF Figure 18. PIN: VAR-L, VAR-R, VS VS 20µA 20K 42K SW 20K 30K GND Vref 20µA D95AU227 D95AU336 GND 17/22 TDA7429 Figure 25. PIN: L-OUT, R-OUT, MONITOR-L, MONITOR-R REAROUT, BASSO-L, BASSO-R, AUXOUT_L, AUXOUT_R Figure 22. PIN: SCL, SDA VS 20µA 20µA ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O GND D94AU205 GND D95AU230 Figure 23. PIN: PS1, PS2, PS3, PS4, LP Figure 26. PIN: BASS-LI, BASS-RI, MIDDLE-LI, MIDDLE-RI, VS VS 20µA 20µA 45K : Bass or 25K : MIDDLE GND BASS-LO GND D95AU308 BASS-RO,MIDDLE-LO,MIDDLE-RO D95AU231A Figure 27. PIN: BASS-LO, BASS-RO, MIDDLELO, MIDDLE-RO, Figure 24. PIN: REARIN VS VS 20µA 20µA SW (*) GND 50K BASS-LI,BASS-RI,MIDDLE-LI,MIDDLE-RI GND Vref 18/22 D95AU229 (*) 45K : Bass 25K : MIDDLE D95AU232 TDA7429 Figure 28. TQFP44 (10 x 10) Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. A MAX. MIN. TYP. 1.60 A1 0.05 A2 1.35 B 0.30 C 0.09 D 11.80 D1 9.80 OUTLINE AND MECHANICAL DATA MAX. 0.063 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.37 0.45 0.012 0.015 0.018 0.20 0.004 12.00 12.20 0.464 0.472 0.480 10.00 10.20 0.386 0.394 0.401 0.008 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O D3 8.00 0.315 E 11.80 12.00 12.20 0.464 0.472 0.480 E1 9.80 10.00 10.20 0.386 0.394 0.401 E3 8.00 0.315 e 0.80 0.031 L 0.45 0.60 L1 0.75 0.018 1.00 k 0.024 0.030 TQFP44 (10 x 10 x 1.4mm) 0.039 0˚(min.), 3.5˚(typ.), 7˚(max.) D D1 A A2 A1 23 33 34 22 0.10mm .004 B E B E1 Seating Plane 12 44 11 1 C L e K TQFP4410 0076922 D 19/22 TDA7429 Figure 29. SDIP42 Mechanical Data & Package Dimensions mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 5.08 OUTLINE AND MECHANICAL DATA MAX. 0.20 A1 0.51 0.020 A2 3.05 3.81 4.57 0.120 B 0.38 0.46 0.56 0.0149 0.0181 0.0220 0.150 0.180 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s b SDIP42P (0.600") e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O B1 0.89 1.02 1.14 0.035 c 0.23 0.25 0.38 0.0090 0.0098 0.0150 D 36.58 36.83 37.08 1.440 E 15.24 16.00 0.60 E1 12.70 14.48 0.50 13.72 0.040 1.450 0.045 1.460 0.629 0.540 e 1.778 0.070 e1 15.24 0.60 0.570 e2 18.54 0.730 e3 1.52 0.060 L 2.54 3.30 3.56 0.10 0.130 0.140 E A2 A L A1 E1 B B1 e e1 e2 D c E 42 22 .015 0,38 Gage Plane 1 e3 21 e2 SDIP42 20/22 TDA7429 Table 16. Revision History Date Revision Description of Changes January 2004 5 First Issue in EDOCS DMS June 2004 6 Changed the Style-sheet in compliance to the new “Corporate Technical Pubblications Design Guide” ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 21/22 TDA7429 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. 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