TDA7430TR

TDA7430 TDA7431 DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX AND VOICE CANCELLER 1 FEATURES Figure 1. Package ■ 1 STEREO (4STEREO) INPUT + 1 MIXER INPUT ■ INPUT ATTENUATION CONTROL IN 0.5dB STEP ■ VOICE CANCELLER IS AVAILABLE ■ TREBLE MIDDLE AND BASS CONTROL ■ THREE SURROUND MODES ARE AVAILABLE SDIP42 Part Number 2 2 SPEAKERS AND 2 RECORD ATTENUATORS: ) s ( ct l o s TQFP44 Tape & Reel DESCRIPTION b O - They reproduce surround sound by using programmable phase shifters and a signal matrix. – AVAILABILITY OF LOUDSPEAKER EQUALIZATION FIXED BY EXTERNAL COMPONENTS u d o Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, r P e – INDEPENDENT MUTE FUNCTION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS t e l o s b O e t e The TDA7430/TDA7431 is volume tone (bass middle and treble) balance (Left/Right) processors voice canceller for quality audio applications in car radio and Hi-Fi systems. – 2 INDEPENDENT SPEAKERS AND 2 INDEPENDENT RECORD CONTROL IN 1dB STEP FOR BALANCE FACILITY ■ SDIP42 TDA7430 TDA7430TR o r P Package TDA7431S – MOVIE AND SIMULATED: 256 SELECTABLE RESPONSES ■ c u d Table 1. Order Codes – MUSIC: 4 SELECTABLE RESPONSES ) s t( TQFP44 Low Distortion, Low Noise and DC stepping are obtained. June 2004 R_IN3 R_IN2 LPVC 41 R_IN4 PS3 42 CREF PS2 43 PS4 PS1 44 VS LP Figure 2. Pin Connection (TDA7430) 40 39 38 37 36 35 34 L_IN2 REARIN 5 29 L_IN3 VAR_L 6 28 L_IN4 BASSO_L 7 27 RECOUT_L VAR_R 8 26 RECOUT_R BASSO_R 9 25 L_OUT BASS_LO 10 24 R_OUT BASS_LI 11 23 DIG_GND 12 13 14 15 16 17 18 19 20 21 22 SCL 30 SDA 4 AGND L_IN1 REAROUT TREBLE_L 31 TREBLE_R 3 MIDDLE_RI MIX HP2. MIDDLE_RO 32 MIDDLE_LI R_IN1 2 MIDDLE_LO 33 HP1 BASS_RI 1 BASS_RO LP1 D95AU220B REV. 10 1/23 TDA7430 - TDA7431 Figure 3. Pin Connection (TDA7431) PS4 PS3 PS2 PS1 LP LP1 HP1 HP2 VOUTREF VAR_L BASSO_L VAR_R BASSO_R BASS_LO BASS_LI BASS_RO BASS_RI MIDDLE_LO MIDDLE_LI MIDDLE_RO MIDDLE_RI 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 D95AU219B VS CREF NBRO NBRIN LPVC R_IN MIX L_IN NBLIN NBLO RECOUT_L RECOUT_R L_OUT R_OUT DIG_GND SCL SDA ADDR AGND TREBLE_L TREBLE_R Table 2. Absolute Maximum Ratings Symbol VS Operating Supply Voltage Operating Ambient Temperature Tstg Storage Temperature Range Symbol Supply Voltage VCL Max Input Signal Handling so Ob Parameter let VS e t le o r P o s b Value s ( t c u d o r P e Table 3. Quick Reference Data c u d O ) Parameter Tamb ) s t( Unit 11 V 0 to 70 °C -55 to 150 °C Min. Typ. Max. Unit 7 9 10.2 V 2 VRMS THD Total Harmonic Distortion V = 0.1Vrms f = 1KHz 0.01 0.1 % S/N Signal to Noise Ratio Vout = 1Vrms (mode = OFF) 106 dB SC Channel Separation f = 1KHz 90 dB Treble Control (2dB step) -14 14 dB Middle Control (2dB step) -14 14 dB Bass Control (2dB step) -14 14 dB Balance Control 1dB step (LCH, RCH) -79 0 dB Mute Attenuation 100 dB Table 4. Thermal Data Symbol Rth j-pin 2/23 Parameter Thermal Resistance Junction-pins Value Unit 85 °C/W TDA7430 - TDA7431 Figure 4. TEST CIRCUIT (TDA7430) 2.2µF BASSO-R 22nF 22nF 37 R-IN2 36 35 31 30 29 28 38 ol 16 17 26 25 24 23 22 21 RECOUT-R L-OUT R-OUT DIG-GND SCL SDA )- BASSO-R so 100nF Ob 1.2nF 5.6nF LP LP1 5.6nF TREBLE-R 5.6nF TREBLE-L 100nF 22nF PS1 LPVC MIDDLE-LO 2.2µF ro VAR-R P e 1 13 BASSO-L 12 HP2 AGND MIDDLE-LI 2.7K MIDDLE-RO MIDDLE-RI D95AU224B 13 2 BASS-LI BASS-RO 5.6K 100nF 100nF BASS-RI 5.6K HP1 680nF 680nF VAR-L 11 HP2 10 0.47µF 1µF R-IN MIX HP1 8 7 37 0.47µF L-IN 36 35 42 VS 10µF 2 41 3 40 4 CREF NBRO 15K 39 5 34 TDA7431 22 NBLIN 15K 33 23 100nF 22µF 220nF 220nF NBRIN 6 7.5K 220nF 220nF NBLO 38 7.5K 100nF 14 18 BASS-LO 100nF 15 19 22nF 18nF 12 3 20 18nF 2.7K o r P BASS-LO s ( t c du 2.2µF let s b O 27 RECOUT-L Figure 5. TEST CIRCUIT (TDA7431) PS2 ) s t( c u d 22µF CREF e t e 11 15 PS4 100nF 100nF D95AU225B 4.7nF 0.47µF L-IN4 100nF 14 MIDDLE-RI PS3 0.47µF L-IN3 220nF 10 MIDDLE-RO 22nF 0.47µF L-IN2 TDA7430 22nF 22nF 0.47µF L-IN1 34 MIDDLE-LO 2.7K 0.47µF R-IN1 10µF 19 MIDDLE-LI 18nF 1µF MIX VS 18nF 2.7K 32 39 LPVC 22nF 5 0.47µF 33 18 TREBLE-L 100nF R-IN3 1 TREBLE-R 5.6nF 4 6 0.47µF R-IN4 44 LP1 5.6nF 7 0.47µF REARIN 43 LP 5.6nF REAROUT 42 PS1 1.2nF 8 VAR-L 41 PS2 100nF BASSO-L 2.2µF 40 PS3 4.7nF VAR-R 9 PS4 2.2µF 16 20 BASS-LI BASS-RO 5.6K 100nF 100nF 21 17 9 32 31 30 29 28 27 26 25 VOUTREF RECOUT-L RECOUT-R L-OUT R-OUT DIG-GND SCL SDA ADDR 24 BASS-RI 5.6K AGND 3/23 R-IN4 0.47µF R-IN3 0.47µF R-IN2 0.47µF R-IN1 0.47µF L-IN4 0.47µF L-IN3 0.47µF L-IN2 0.47µF L-IN1 0.47µF 37 36 35 33 28 29 30 31 2 + + - 39 VS 100K VOICE ON R6 R5 MIX-IN 1µF 32 MIX 34 LPVC 100nF 31.5dB control LPF - + + RLP1 RHP1 3 HP2 THE SWITCHES POSITION MATCHES THE RESET CONDITION 50K 50K 50K 50K 50K 50K 50K 50K 1 31.5dB control HP1 - 20 + - + 38 SUPPLY L-R 22µF LP 44 Vref MOVIE/ MUSIC SIM 1.2nF LPF 9KHz 42 RPS3 PS3 22nF 41 5 2.2µF MOVIE/SIM 4 MUSIC PS3 400Hz EFFECT CONTROL OFF PS2 4KHz PS1 90Hz 43 PS2 RPS2 PS1 RPS1 CREF LP1 AGND 4.7nF REAROUT 100nF PS4 400Hz RPS4 PS4 22nF REARIN 40 50K MIXING AMP MIXING AMP SURR OFF OFF 18 5.6nF TREBLE-R SURR TREBLE TREBLE 19 TREBLE-L 5.6nF 15 17 2.7K 18nF RM MIDDLE MIDDLE MIDDLE-LO RB 10 REAR SURR 22nF 16 BASS 13 3BAND FIX REAR RB 12 SURR FIX 5.6K 100nF 100nF 3BAND BASSO-R 79dB CONTROL MUTE REC ATT MUTE REC ATT 7 BASSO-L 79dB CONTROL I2C BUS DECODER + LATCHES BASS 11 BASS-LO 100nF BASS-LI 5.6K 22nF 100nF 14 RM 2.7K 18nF MIDDLE-LI MIDDLE-RI 680nF BASS-RI 4/23 O ) o s b e t le MIDDLE-RO t e l o u d o s ( t c BASS-RO 2.2µF 9 30K FIX VAR 30K VAR-L VAR-R 8 VAR FIX 6 2.2µF - r P e - + + s b O 5.6nF 79dB CONTROL MUTE 26 24 23 21 22 25 RECOUT-R R-OUT DIG GND SDA SCL L-OUT RECOUT-L D95AU221B SPKR ATT MUTE SPKR ATT 79dB CONTROL 27 TDA7430 - TDA7431 Figure 6. Block Diagram (TDA7430) ) s t( c u d o r P R-in 0.47µF L-in 0.47µF 50K 50K 31.5dB control 100nF MIX-IN 1µF 5 LP MOVIE/ MUSIC 36 L-R SIM 42 3 VS 2 41 SUPPLY 22nF RPS4 PS4 1 Vref 22µF 5.6nF TREBLE 22 TREBLE 5.6nF TREBLE-R SURR SURR 23 TREBLE-L OFF OFF MIXING AMP MIXING AMP PS4 400Hz VOUTREF 9 MOVIE/SIM PS3 400Hz MUSIC 24 PS3 RPS3 EFFECT CONTROL OFF PS2 4KHz RPS2 PS2 1.2nF LPF 9KHz 4 MIX 100K VOICE ON + - + - PS1 90Hz RPS1 PS1 38 + + - R6 R5 HP2 LPVC LPF - + + RLP1 RHP1 8 THE SWITCHES POSITION MATCHES THE RESET CONDITION 37 35 7 HP1 6 LP1 31.5dB control 22nF AGND 4.7nF CREF 19 21 MIDDLE MIDDLE RM 18 REAR SURR RB 2.7K 18nF 22nF RM 20 14 3BAND SURR REAR BASS FIX 3BAND 17 5.6K 100nF 100nF RB 16 BASSO-R 79dB CONTROL MUTE REC ATT MUTE REC ATT 11 BASSO-L 79dB CONTROL I2C BUS DECODER + LATCHES FIX BASS-LO 100nF BASS-LI BASS 15 5.6K 22nF 100nF MIDDLE-LO 2.7K 18nF MIDDLE-LI MIDDLE-RI 2.2µF 13 12 VAR FIX 10 2.2µF 34 30K FIX VAR 30K NB3 NB4 NB-RA 39 - + NB-LB 40 31 29 25 28 26 27 30 32 D95AU222C 79dB CONTROL MUTE SPKR ATT MUTE SPKR ATT 79dB CONTROL NB-RB 33 NB2 NB1 NB-LA NBLO 100nF BASS-RI NBLIN NBRIN 680nF BASS-RO e t le MIDDLE-RO VAR-L VAR-R u d o s ( t c O ) o s b NBRO - t e l o r P e + s b O 5.6nF RECOUT-R R-OUT ADDR DIG GND SDA SCL L-OUT RECOUT-L TDA7430 - TDA7431 Figure 7. Block Diagram (TDA7431) c u d ) s t( o r P 5/23 TDA7430 - TDA7431 Table 5. Electrical Characteristcs (refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, Vin = 1Vrms; RG = 600Ω, all controls flat (G = 0dB), Effect CTRL = -6dB, MODE = OFF; f = 1KHz unless otherwise specified). Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY VS Supply Voltage 7 9 10.2 V IS Supply Current 10 18 26 mA 60 80 35 50 2 2.5 SVR Ripple Rejection LCH / RCH out, Mode = OFF dB ) s t( INPUT STAGE RIN Input Resistance VCL Clipping Level CRANGE Control Range THD = 0.3% 65 Min. Attenuation ro AVMAX Max. Attenuation ASTEP Step Resolution eP -1 dB 31.5 32 dB 0.5 1 dB -3 0 3 mV let o s b dB 1 31 0 c u d Vrms 31.5 AVMIN KΩ VDC DC Steps adjacent att. step AVO1 Voice Canceler Output 1 LIN = RIN, RIN = ON, Vmix = 0V FIX, 0dB attenuation 5 6 7 dB AVO2 Voice Canceler Output 2 LIN = RIN = 0V, Vmix = 1Vrms FIX, 0dB attenuation -1 0 1 dB AVO3 Voice Canceler Output 3 LIN = RIN, Vmix = 0V FIX, 0dB attenuation 5 6 7 dB RLPV Low Pass Filter Resistance 22.4 32 41.6 KΩ RMIX Input Impedance 70 100 130 KΩ ±11.5 ±14.0 ±16.0 dB (s) d o r P e t e l o BASS CONTROL t c u Gb Control Range BSTEP Step Resolution 1 2 3 dB Internal Feedback Resistance 32 44 56 KΩ ±11.5 ±14.0 ±16.0 dB 1 2 3 dB 17.5 25 32.5 KΩ ±13.0 ±14.0 ±15.0 dB 1 2 3 dB s b O RB Max. Boost/cut -O MIDDLE CONTROL Gm Control Range MSTEP Step Resolution RM Max. Boost/cut Internal Feedback Resistance TREBLE CONTROL Gt Control Range TSTEP Step Resolution 6/23 Max. Boost/cut TDA7430 - TDA7431 Table 5. Electrical Characteristcs (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit 6 dB 1.5 dB EFFECT CONTROL CRANGE Control Range ±13.0 SSTEP Step Resolution 0.5 1 SURROUND SOUND MATRIX TEST CONDITION (Phase Resistor Selection D0=0, D1=1, D2=0. D3=1, D4=0, D5=1, D6=0, D7=1 GOFF In-phase Gain (OFF) Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin → Rout , Lin → Lout -1 0 1 dB DGOFF LR In-phase Gain Difference (OFF) Mode OFF, Input signal of 1kHz, 1.4 Vp-p, Rin → Rout , Lin → Lout -1 0 1 dB GMOV In-phase Gain (Movie) Movie mode, Effect Ctrl = -6dB 1kHz, 1.4 Vp-p, Rin → Rout , Lin → Lout DGMOV LR In-phase Gain Difference (Movie) Movie mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) - (Lin → Lout) GMUS In-phase Gain (Music) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) , (Lin → Lout) DGMUS LR In-phase Gain Difference (Music) Music mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p (Rin → Rout) , (Lin → Lout) LMON1 Simulated L Output 1 LMON2 Simulated L Output 2 LMON3 8 ) s t( c u d dB o r P 0 dB 7 dB 0 dB Simulated Mode, Effect Ctrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin → Lout 4.5 dB Simulated Mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin → Lout –4.0 dB Simulated L Output 3 Simulated Mode, Effect Ctrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin → Lout 7.0 dB RMON1 Simulated R Output 1 Simulated Mode, Effect Ctrl = -6dB Input signal of 250Hz, 1.4 Vp-p, Rin and Lin → Rout – 4.5 dB RMON2 Simulated R Output 2 Simulated Mode, Effect Ctrl = -6dB Input signal of 1kHz, 1.4 Vp-p, Rin and Lin → Rout 3.8 dB RMON3 Simulated R Output 3 Simulated Mode, Effect Ctrl = -6dB Input signal of 3.6kHz, 1.4 Vp-p, Rin and Lin → Rout – 20 dB e t e l o s ) s ( ct b O - u d o r P e t e l o s b O RLP1 Low Pass Filter Resistance 7 10 13 KΩ RHPI High Pass Filter Resistance 42 60 78 KΩ RLPF LP Pin Impedance 7 10 13 KΩ 7/23 TDA7430 - TDA7431 Table 5. Electrical Characteristcs (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit SURROUBND SOUBND MATRIX PHASE RPS10 Phase Shifter 1: D1 = 0, D0 = 0 8.3 11.8 15.2 KΩ RPS11 Phase Shifter 1: D1 = 0, D0 = 1 10 14.1 18.3 KΩ RPS12 Phase Shifter 1: D1 = 1, D0 = 0 12.6 17.9 23.3 KΩ RPS13 Phase Shifter 1: D1 = 1, D0 = 1 26.4 37.3 48.85 KΩ RPS20 Phase Shifter 2: D3 = 0, D2 = 0 4 5.6 7.2 KΩ RPS21 Phase Shifter 2: D3 = 0, D2 = 1 4.8 6.8 8.7 KΩ RPS22 Phase Shifter 2: D3 = 1, D2 = 0 6 8.4 10.9 KΩ RPS23 Phase Shifter 2: D3 = 1, D2 = 1 12.9 18.3 RPS30 Phase Shifter 3: D5 = 0, D4 = 0 8.5 RPS31 Phase Shifter 3: D5 = 0, D4 = 1 RPS32 Phase Shifter 3: D5 = 1, D4 = 0 RPS33 Phase Shifter 3: D5 = 1, D4 = 1 RPS40 Phase Shifter 4: D7 = 0, D6 = 0 RPS41 Phase Shifter 4: D7 = 0, D6 = 1 RPS42 Phase Shifter 4: D7 = 1, D6 = 0 RPS43 Phase Shifter 4: D7 = 1, D6 = 1 ) s ( ct u d o ro KΩ 15.6 KΩ 14.5 18.7 KΩ 18.1 23.3 KΩ 27.4 39.1 50.75 KΩ 8.5 12.1 15.6 KΩ 10.2 14.5 18.7 KΩ 12.7 18.1 23.3 KΩ 27.4 39.1 50.75 KΩ eP let -O c u d 23.7 10.2 o s b ) s t( 12.7 12.1 SPEAKER & RECORD ATTENUATORS CRANGE Control Range SSTEP Step Resolution RVEA dB 1 1.5 dB -1.5 0 1.5 dB Av = -20 to -79dB -3 0 2 dB adjacent att. steps -3 0 3 mV Output Mute Condition +70 100 Input Impedance 21 30 ol bs O AMUTE 79 -0.5 Attenuation set error EA VDC ete Pr DC Steps Av = 0 to -20dB dB 39 KΩ AUDIO OUTPUTS NO(OFF) Output Noise (OFF) Output Mute, Flat BW = 20Hz to 20KHz 4 5 µVrms µVrms NO(MOV) Output Noise (Movie) Mode = Movie BW = 20Hz to 20KHz 30 µVrms NO(Mus) Output Noise (Music) Mode = Music BW = 20Hz to 20KHz 30 µVrms Mode Simulated BW = 20Hz to 20KHz 30 µVrms NO(MON) Output Noise (Simulated) 8/23 TDA7430 - TDA7431 Table 5. Electrical Characteristcs (continued) Symbol d Parameter Distorsion Test Condition SC Min. Av = 0 ; Vin = 1Vrms Channel Separation VOCL Clipping Level ROUT Output Resistance VOUT DC Voltage Level d = 0.3% Typ. Max. Unit 0.01 0.1 % 70 90 dB 2 2.5 Vrms 10 40 70 3.8 Ω V ) s t( BUS INPUTS 3 VIL Input Low Voltage VIH Input High Voltage 3 IIN Input Current -5 VO Output Voltage SDA Acknowledge 1 IO = 1.6mA e t le 2 I C BUS INTERFACE V c u d V o r P +5 mA 0.4 V o s b Data transmission from microprocessor to the TDA7430/TDA7431 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). O ) s ( t c 3.1 Data Validity As shown in fig. 8, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. u d o r P e 3.2 Start and Stop Conditions As shown in fig.9 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. t e l o 3.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. s b O 3.4 Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 10). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 3.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. 9/23 TDA7430 - TDA7431 Figure 8. Data validity on the I2C bus SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 9. Timing Diagram of I2C bus ) s t( c u d SCL I2CBUS SDA e t le D99AU1032 START STOP o s b Figure 10. Acknowledge on the I2C bus SCL 1 O ) 2 SDA MSB START 3 7 8 9 s ( t c u d o ACKNOWLEDGMENT FROM RECEIVER r P SOFTWARE SPECIFICATION e t e l o s b O 4 o r P D99AU1033 4.1 Interface Protocol The interface protocol comprises: ■ A start condition (S) ■ A chip address byte, containing the TDA7430/TDA7431 address ■ A subaddress bytes ■ A sequence of data (N byte + achnowledge) ■ A stop condition (P) Figure 11. CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 D95AU226A 10/23 0 0 A 0 MSB ACK B DATA 1 to DATA n LSB DATA MSB ACK LSB DATA ACK P TDA7430 - TDA7431 5 EXAMPLES 5.1 No Incremental Bus The TDA7430/TDA7431 receives a start condition, the correct chip address, a subaddress with the MSB = 0 (no incremental bus), N-datas (all these datas concern the subaddress selected), a stop condition. Figure 12. SUBADDRESS CHIP ADDRESS MSB S 1 LSB 0 0 0 0 0 A 0 MSB ACK 0 DATA LSB X X MSB LSB X D3 D2 D1 D0 ACK DATA ) s t( ACK P D95AU306 c u d 5.2 Incremental Bus The TDA7430/TDA7431 receives a start condition, the correct chip address, a subaddress with the MSB = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "1XXX1010" to "1XXX1111" of DATA are ignored.The DATA 1 concern thesubaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. e t le o s b Figure 13. CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 0 0 A 0 ACK 1 LSB DATA BYTES DATA 1 to DATA n MSB s ( t c X X D95AU307 6 O ) MSB o r P X D3 D2 D1 D0 ACK LSB DATA ACK P u d o r P e Address = 80(HEX) ADDR open; 82 (HEX): need to connect supply t e l o 6.1 Function Selection s b O Table 6. The first byte (Subaddress) MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 B X X X 0 0 0 D0 0 INPUT ATTENUATION B X X X 0 0 0 1 SURROUND & OUT & EFFECT CONTROL B X X X 0 0 1 0 PHASE RESISTOR B X X X 0 0 1 1 BASS & NATURAL BASE B X X X 0 1 0 0 MIDDLE & TREBLE B X X X 0 1 0 1 SPEAKER ATTENUATION "L" B X X X 0 1 1 0 SPEAKER ATTENUATION "R" B X X X 0 1 1 1 AUX ATTENUATION "L" B X X X 1 0 0 0 AUX ATTENUATION"R" B X X X 1 0 0 1 INPUT MULTIPLEXER, & AUX OUT B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1 11/23 TDA7430 - TDA7431 Table 7. INPUT ATTENUATION SELECTION MSB D7 D6 D5 D4 D3 LSB INPUT ATTENUATION D2 D1 D0 0.5 dB STEPS X 0 0 0 0 X 0 0 1 -0.5 X 0 1 0 -1 X 0 1 1 -1.5 X 1 0 0 -2 X 1 0 1 -2.5 X 1 1 0 -3 X 1 1 1 X 0 0 0 X 0 0 1 X 0 1 0 X 0 1 1 X 1 0 0 X 1 0 1 X 1 1 X 1 INPUT ATTENUATION = 0 ~ -31.5dB e t e ol Table 8. s b O D4 -4 -8 -16 -20 -24 1 D3 0 -28 D7 D6 X 0 REARIN, REAROUT PIN ACTIVE X 1 NO REARIN, REAROUT PIN 12/23 D5 0 ) (s 4 dB STEPS -12 ct du o r P 1 so Ob o r P -3.5 e t le c u d D2 D1 D0 ) s t( REAR SWITCH TDA7430 - TDA7431 Table 9. SURROUND SELECTION MSB D7 D6 D5 D4 D3 D2 LSB D0 0 1 0 1 D1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SURROUND MODE SIMULATED MUSIC OFF MOVIE OUT VAR FIX EFFECT CONTROL -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 ) s t( c u d e t le o s b O ) s ( t c u d o o r P Table 10. PHASE RESISTOR SELECTION MSB D7 ete D6 D5 Pr D4 LSB D3 D2 0 0 1 1 0 1 0 1 l o s Ob 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D1 0 0 1 1 D0 0 1 0 1 SURROUND PHASE RESISTOR PHASE SHIFT 1 (KΩ) 12 14 18 37 PHASE SHIFT 2 (KΩ) 6 7 8 18 PHASE SHIFT 3 (KΩ) 12 14 18 39 PHASE SHIFT 4 (KΩ) 12 14 18 39 13/23 TDA7430 - TDA7431 Table 11. BASS SELECTION MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 Table 12. SPEAKER/AUX ATT. R & L SELECTION D6 D5 s ( t c u d o D4 D3 r P e t e l o s b O 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 X X X X = INDIFFERENT 0,1 SPEAKER/AUX ATTENUATION = 0dB ~ -79dB 14/23 O ) D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 BASS 2 dB STEPS -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 NATURAL BASE NBRIN, NBRO, NBLIN, NBLO PIN ACTIVE NO NBRIN, NBRO, NBLIN, NBLO PIN e t le o s b 0 MSB D7 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 LSB D0 0 1 0 1 0 1 0 1 ) s t( c u d o r P SPEAKER/AUX ATT 1 dB STEPS 0 -1 -2 -3 -4 -5 -6 -7 8 dB STEPS 0 -8 -16 -24 -32 -40 -48 -56 -64 -72 MUTE TDA7430 - TDA7431 Table 13. MIDDLE & TREBLE SELECTION MSB D7 D6 D5 D4 0 0 D2 D1 D0 2 dB STEPS 0 0 0 0 -14 0 0 0 1 -12 0 0 1 0 -10 0 0 1 1 -8 0 1 0 0 -6 0 1 0 1 -4 0 1 1 0 -2 0 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 0 1 e t e 1 0 1 0 0 0 0 0 0 1 0 0 0 1 Pr )- s ( t c u d o 0 MIDDLE D3 1 0 LSB 0 1 c u d 0 o r P 0 2 4 l o s 0 6 1 8 1 0 10 0 1 12 0 0 14 Ob TREBLE 2 dB STEPS -14 1 -12 0 -10 1 -8 0 0 -6 0 1 -4 O 1 1 0 -2 0 1 1 1 0 1 1 1 1 0 1 1 1 0 2 1 1 0 1 4 1 1 0 0 6 1 0 1 1 8 1 0 1 0 10 1 0 0 1 12 1 0 0 0 14 0 o s b 0 e t e l 1 1 ) s t( 15/23 TDA7430 - TDA7431 Table 14. VOICE CANCELLER/INPUT/RECOUT L & R SELECTION MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 VOICE CANCELER 0 1 0 OFF 0 0 1 ON INPUT MULTIPLEXER 0 0 IN2 0 1 IN3 1 0 IN4 1 1 ) s t( IN1 REC OUT "L" c u d 0 0 VER 1 (3BAND) 0 1 VER 2 (SURR) 1 0 1 1 o r P VER 3 (REAR) FIX e t le REC OUT "R" 0 0 0 0 1 0 VER 2 (SURR) 1 0 0 VER 3 (REAR) 1 1 0 FIX so ) (s Table 15. t c u Ob VER 1 (3BAND) POWER ON RESET BASS & MIDDLE od TREBLE 2dB 0dB SURROUND & OUT CONTROL+ EFFECT CONTROL OFF + FIX + MAX ATTENUATION SPEAKER/AUX ATTENUATION L &R MUTE e t e l Pr INPUT ATTENUATION + REAR SWITCH MAX ATTENUATION + ON NATURAL BASE OFF so INPUT Ob IN1 Figure 14. PINS: L-OUT, R-OUT, RECOUT-L, RECOUT-R, Figure 15. PIN: HP1 LP1 VS VS 10K 20µA 100Ω 60K HP2 GND D94AU204 16/23 GND D94AU198 TDA7430 - TDA7431 Figure 16. PIN: HP2 Figure 19. PIN: LP1 VS VS 20µA 20µA 5.5K 60K ) s t( 10K HP1 GND GND 5.5K D94AU199 20µA (s) SW t c u od 30K Pr D95AU227 Figure 18. PIN: L-IN, R-IN, L-IN2, R-IN2, L-IN3, R-IN3, L-IN4, R-IN4, s b O e t le o s b VS VS e t e ol D94AU211 Figure 20. PIN: CREF Figure 17. PIN: VAR-L, VAR-R, GND Vref c u d HP1 -O o r P 20µA 20K 42K 20K D95AU336 GND Figure 21. PIN: SCL, SDA VS 20µA 20µA 50K GND GND VREF D94AU205 D94AU200 17/23 TDA7430 - TDA7431 Figure 25. PIN: MIX Figure 22. PIN: PS1, PS2, PS3, PS4, LP VS VS 20µA 20µA ) s t( 100K GND GND c u d Vref D94AU123 D95AU308 o r P Figure 26. PINS: REAEROUT, BASSO-L, BASSO-R Figure 23. PIN: ADDR e t le o s b VS VS 20µA u d o 50K GND Pr GND e t e ol ) s ( ct -O 20µA GND D95AU230 D95AU228A Figure 27. BASS-LI, BASS-RI, MIDDLE-L, MIDDLE-RII s b O Figure 24. PIN: REARIN VS VS 20µA 20µA SW GND 50K BASS-LO GND Vref 18/23 D95AU229 45K : Bass or 25K : MIDDLE BASS-RO,MIDDLE-LO,MIDDLE-RO D95AU231A TDA7430 - TDA7431 Figure 31. NBLIN, NBRIN Figure 28. PIN: BASS-LO, BASS-RO, MIDDLELO, MIDDLE-RO, VS VS 20µA 20µA (*) ) s t( GND BASS-LI,BASS-RI,MIDDLE-LI,MIDDLE-RI GND D95AU232 SW c u d D95AU234 (*) 45K : Bass 25K : MIDDLE Figure 32. NBLO, NBRO e t le Figure 29. PIN:TREBLE-L, TREBLE-R, VS VS o s b 20µA GND e t e ol O ) s ( t c 25K o r P u d o Pr VREF GND D95AU235A D95AU309 s b O Figure 30. PIN VOUT REF, VS 20µA GND D95AU233A 10K GND 19/23 TDA7430 - TDA7431 Figure 33. TQFP44 (10 x 10) Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. A MAX. MIN. TYP. 1.60 A1 0.05 A2 1.35 B 0.30 C 0.09 D 11.80 D1 9.80 D3 0.063 0.15 0.002 1.40 1.45 0.053 0.055 0.057 0.37 0.45 0.012 0.015 0.018 0.20 0.004 12.00 12.20 0.464 0.472 0.480 10.00 10.20 0.386 0.394 0.401 8.00 0.006 12.00 12.20 0.464 0.472 0.480 E1 9.80 10.00 10.20 0.386 0.394 0.401 E3 8.00 0.315 e 0.80 0.031 0.60 L1 0.75 0.018 1.00 k 0.030 e t e ol o s b O ) TQFP44 (10 x 10 x 1.4mm) s ( t c u d o Pr D1 A A2 A1 23 34 22 0.10mm .004 B E E1 Seating Plane B bs o r P e t le 0.039 D O 0.024 0˚(min.), 3.5˚(typ.), 7˚(max.) 33 c u d 0.315 11.80 0.45 ) s t( 0.008 E L OUTLINE AND MECHANICAL DATA MAX. 12 44 11 1 C L e K TQFP4410 0076922 D 20/23 TDA7430 - TDA7431 Figure 34. SDIP42 Mechanical Data & Package Dimensions mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 5.08 0.20 A1 0.51 A2 3.05 3.81 4.57 0.120 B 0.38 0.46 0.56 0.0149 0.0181 0.0220 B1 0.89 1.02 1.14 0.035 c 0.23 0.25 0.38 0.0090 0.0098 0.0150 D 36.58 36.83 37.08 1.440 E 15.24 16.00 0.60 E1 12.70 14.48 0.50 0.020 13.72 0.150 0.180 0.040 0.540 0.070 e1 15.24 0.60 0.570 e2 18.54 0.730 e3 1.52 0.060 3.30 3.56 0.10 c u d 1.460 0.629 1.778 2.54 ) s t( 0.045 1.450 e L OUTLINE AND MECHANICAL DATA MAX. 0.130 0.140 e t le o s b O SDIP42 (0.600") ) s ( t c u d o E A2 A E1 L s b O Pr A1 e t e ol o r P B B1 e e1 e2 D c E 42 22 .015 0,38 Gage Plane 1 e3 21 e2 SDIP42 21/23 TDA7430 - TDA7431 Table 16. Revision History Date Revision Description of Changes January 2004 9 First Issue in EDOCS DMS June 2004 10 Changed the Style-sheet in compliance to the new “Corporate Technical Pubblications Design Guide” ) s t( c u d e t le o s b O ) s ( t c u d o r P e t e l o s b O 22/23 o r P TDA7430 - TDA7431 ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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