TDA7463D013TR

TDA7463 LOW VOLTAGE TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR 1 „ „ „ „ „ „ „ „ „ 2 FEATURES Figure 1. Package 1 STEREO INPUT 1 STEREO OUTPUT TREBLE BOOST BASS CONTROL BASS AUTOMATIC LEVEL CONTROL VOLUME CONTROL IN 1dB STEPS MUTE STAND-BY FUNCTION SOFTWARE CONTROLLED ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS SO16 Table 1. Order Codes Part Number C1 0.47µF o r P e IN-R t e l o s b O C2 0.47µF ct du TREBLE-R o s b O - Low Distortion, Low Noise and DC stepping are obtained.obtained. R5 5.6K 100nF BASSI-R 100nF C11 C10 BASSO-R RB -63dB CONTROL 0/-10dB x1 TREBLE BASS OUT-R x5 50K VS BASS_ALC CONTROL SCL ALC I2C VS 1 HALF_WAVE RECTIFIER R3 1KΩ R4 1KΩ I2C BUS DECODER + LATCHES + SDA C3 0.47µF TREBLE 50K BASS 0/-10dB VREF VS SUPPLY VS C8 100nF TREBLE-L C4 3.3nF DGND SDA x1 -63dB CONTROL D96AU482B VS SCL OUT-L x5 IN-L 2 3 4 R1 1MΩ RB April 2010 o r P e t le Bass ALC (Automatic Level Control) function can be adjusted by a dedicated pin. The control of all (s) SO16 Tape & Reel The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, The TDA7463 is a volume tone (bass and treble) processor for quality audio applications in Low voltage supply portable systems. C12 3.3nF c u d TDA7463D TDA7463D013TR ) s t( the functions is accomplished by serial bus. DESCRIPTION Figure 2. Block Diagram Package BASSI-L C5 100nF R2 5.6K BASSO-L C6 100nF GND C9 100µF CREF C7 22µF REV. 5 1/12 TDA7463 Table 2. Absolute Maximum Ratings Symbol Parameter Value Operating Supply Voltage VS Tamb 5 V 0 to 70 °C -55 to 150 °C Operating Ambient Temperature Storage Temperature Range Tstg Unit Figure 3. Pin Connection VS 1 16 ALC IN-L 2 15 IN-R TREBLE-L 3 14 TREBLE-R BASSI-L 4 13 BASSI-R BASSO-L 5 12 BASSO-R OUT-L 6 11 OUT-R SDA 7 10 CREF SCL 8 9 GND D96AU484 Table 3. Thermal Data Symbol Rth j-pin Parameter Thermal Resistance Junction-pins ) s ( ct Table 4. Quick Reference Data Symbol Parameter du VS Supply voltage VCL Max. input signal handling o r P e THD S/N t e l o Sc s b O e t le o s b O Test Condition o r P Value Unit 85 °C/W Min. Typ. Max. 1.8 2.4 3 0.2 Unit V Vrms Total Harmonic Distortion V = 0.1Vrms ; f = 1KHz Signal to Noise Ratio Vout = 0.1Vrms (mode = OFF 80 dB Channel Separation f = 1KHz 80 dB Volume control 0.1 % (1dB step) -63 0 dB -10dB damping -10 0 dB -14dB 0 14 dB Treble Control 0 8 dB Bass Control 0 mute attenuation 2/12 c u d 100 14 dB 8 dB ) s t( TDA7463 Table 5. Electrical Characteristcs (refer to the test circuit Tamb = 25°C, VS =2.4V, RL= 10KΩ, RG = 600Ω, all controls flat, unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. 1.8 2.4 3 Unit SUPPLY VS Supply Voltage IS Supply Current 4 mA IST-BY Stand-By Current 50 µA SVR Ripple Rejection 70 dB V INPUT STAGE RIN Input Resistance VCL Clipping Level 35 THD = 0.3% 50 65 0.2 KΩ Vrms VOLUME CONTROL CRANGE Control Range AV MIN Min Attenuation -1 0 1 dB AVMAX Max. Attenuation 62 63 64 dB ASTEP Step Resolution Amute Mute Attenuation A-10dB -10dB damping G14dB 14dB gain 63 80 Control Range Max. Boost/on e t le RB Internal Feedback Resistance TREBLE CONTROL (1) Control Range Max. Boost on AUDIO OUTPUTS RL Clipping Level Output Load Resistance VDC DC Voltage Level GENERAL Output Noise Et Total Tracking Error o r P e (t s) S/N Signal to Noise Ratio SC Channel Separation Left/Right t e l o d s b O c u d NO E o s b O - 33.75 Distortion d = 0.3% 14 14 45 KΩ VRMS 10 KΩ 0.8 V 5 8 µV µV 0 1 80 dB dB 80 AV = 0; VI = 0.1VRMS ; dB dB dB 0.2 All gains 0dB; VO = 0.1VRMS; dB dB 56.25 8 Outout Muted All gains = 0dB; BW = 20Hz to 20KHz flat ) s t( dB o r P 100 10 Gb VCLIP c u d 1 BASS CONTROL (1) Gt dB dB 0.1 % 0.5 V 5 µA 0.4 V BUS INPUT VIL Input Low Voltage VIH Input High Voltage IIN Input Current VIN = 0.4V VO Output Voltage SDA Acknowledge IO = 1.6mA 1.9 -5 V Note: 1. BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry. 3/12 TDA7463 3 DATA BYTES Address = (HEX) 10001000 Table 6. FUNCTION SELECTION: The first byte (subaddress)58 MSB LSB SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 X X B 0 0 0 0 X X B 0 0 0 1 BASS X X B 0 0 1 0 VOLUME STAND-BY & TREBLE & OTHERS B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1 c u d Table 7. STAND_BY & TREBLE & OTHERS MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 STAND-BY e t le 1 o r P ALL CIRCUITS STOP TREBLE so 1 1 1 (s) 0 t c u 1 d o r P e 1 0 t e l o bs O 4/12 0 0 b O 0 0 0 0 0 0 STAND-BY (Treble block stops) BOOST OFF BOOST ON High Boost (+8dB) Low Boost (+4dB) MUTE Input Mute ON Input Mute OFF Output Mute ON Output Mute OFF BASS 1 Release Current Circuit ON 0 Release Current Circuit OFF INPUT Select 1 INPUT 1 0 INPUT 2 ) s t( TDA7463 Table 8. BASS MSB LSB D7 D6 D5 D4 D3 D2 D1 1 0 BASS D0 STAND-BY (Bass block stops) 1 BASS (boost OFF) 0 BASS (boost ON) 1 0 High boost (Ex. + 14dB) 0 0 Low boost (Ex. + 6dB) 1 ALC mode OFF (ALC block stops) 0 ALC mode ON 0 0 Attack time resistor (12.5KΩ) Release current (0.4µA) 0 1 Attack time resistor (25KΩ) Release current (0.2µA) 1 0 Attack time resistor (50KΩ) Release current (0.1µA) 1 1 Attack time resistor (100KΩ) Release current (0.05µA) 0 1 Threshold2 (0.14Vrms) 1 0 Threshold3 (0.1Vrms) 1 1 Threshold4 (0.07Vrms) e t le Table 9. VOLUME D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 ) s ( ct u d o 0 0 0 0 1 1 1 1 r P e t e l o s b O o r P 0 MSB D7 1 0 1 0 c u d Threshold1 (0.2Vrms) 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 so LSB D0 0 1 0 1 0 1 0 1 b O - ) s t( VOLUME 1 dB STEPS 0 -1 -2 -3 -4 -5 -6 -7 8 dB STEPS 0 -8 -16 -24 -32 -40 -48 -56 OUTPUT GAIN 0dB +14dB OUTPUT ATTENUATION 0dB -10dB VOLUME : 0 ~ -63dB 5/12 TDA7463 3.1 ALC IN general: Table 10. VOLUME setting with ALC Target Volume [dB] Volume [dB] Output Gain 0/+14dB0/-10dB [dB] Output Attenuation 0/-10dB [dB] +14 0 0 -14 -1 -15 -2 -16 -3 -17 -4 -18 -5 -19 -6 -20 -7 -21 -8 -22 -9 -23 -10 -24 -11 -25 -12 -26 -13 -27 -14 -14 -15 -15 -16 -16 -17 -17 -18 -18 -19 -19 -20 -20 -21 -21 -22 -23 o r P e -24 t e l o bs O 6/12 ) s ( ct du c u d e t le 0 o r P 0 o s b O - -22 -23 -14 -25 -15 -26 -16 -27 -17 : : : : -70 -60 -71 -61 -72 -62 -73 -63 0 -10 ) s t( TDA7463 Figure 4. PIN: IN-L, IN-R Figure 7. OUT-L, OUT-R VS VS 20µA 20µA 10Ω 50K GND GND Vref D99AU1107 D99AU1106 Figure 5. PIN: TREBLE-L, TREBLE-R VS e t le 20µA 25K GND ) s ( ct D99AU1108 Figure 6. PIN: BASSI-L, BASSI-R u d o r P e VS t e l o O bs GND o s b O - o r P GND D99AU1109 Figure 9. BASSO-L, BASSO-R VS 20µA 20µA 45K 45K BASSO-L,BASSO-R c u d Figure 8. SCL, SDA ) s t( GND D99AU1110 BASSI-L,BASSI-R D99AU1111 7/12 TDA7463 Figure 10. PIN: ALC Figure 12. BASS ALC: Threshold curve VO (Vrms) VS D99AU1115 Bass boost without ALC VS=1.8V; f=100Hz; Volume=-14dB; Output gain=+14dB Intern. release circuit=ON Bass boost with ALC 20µA Threshold: 8dB 11dB 14dB 0.1 17dB 100K Bass= +14dB boost flat GND D99AU1112 Figure 11. PIN CREF 0.01 0.01 0.1 VI(Vrms) c u d Figure 13. BASS ALC: THD THD V =1.8V; f=100Hz; S (%) Volume=-14dB; Output gain=+14dB Intern. release circuit=ON Threshold B 1 14d o s b O 0.1 17dB o r P B 20µA 1K e t le Bass boost with ALC 8dB 10 11d VS D99AU1114 Bass boost without ALC 0.01 GND D99AU1113 (s) t c u d o r P e t e l o s b O 8/12 0.001 0.01 flat 0.1 VI(Vrms) ) s t( TDA7463 Figure 14. board and Components Layout of the Application & Test Circuit. c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 9/12 TDA7463 Figure 15. SO16 Wide Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 0.23 0.32 0.009 0.013 10.10 10.50 0.398 0.413 7.60 0.291 C D (1) E 7.40 e 1.27 0.299 0.050 H 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 k OUTLINE AND MECHANICAL DATA c u d 0˚ (min.), 8˚ (max.) ddd 0.10 e t le 0.004 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. ) s ( ct o r P SO16 (Wide) o s b O - u d o r P e t e l o s b O 0016021 C 10/12 ) s t( TDA7463 Table 11. Revision History Date Revision Description of Changes May 2002 3 Third issue June 2004 4 Changed the Style-sheet in compliance to the new “Corporate Technical Pubblications Design Guide” 26-Apr-2010 5 Major revision to update RPN on cover page for revalidation process c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 11/12 TDA7463 c u d Please Read Carefully: ) s t( Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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