TDA7491MV

TDA7491MV 25 W mono BTL class-D audio amplifier Datasheet - production data Description The TDA7491MV is a mono BTL class-D audio amplifier with single power supply designed for LCD TVs and monitors. Thanks to the high efficiency and an exposed-pad-down (EPD) package no heatsink is required. Furthermore, the filterless operation allows a reduction in the external component count. PowerSSO-36 with exposed pad down The TDA7491MV is pin to pin compatible with the TDA7491P, TDA7491LP and TDA7491HV for the left channel. Features  20 W continuous output power: RL = 8 , THD = 10% at VCC = 18 V  25 W continuous output power: RL = 6 , THD = 10% at VCC = 16 V  Wide range single supply operation (5 V - 18 V)  High efficiency ( = 90%)  Four selectable, fixed gain settings of nominally 20 dB, 26 dB, 30 dB and 32 dB  Differential inputs minimize common-mode noise  Filterless operation  No ‘pop’ at turn-on/off  Standby and mute features  Short-circuit protection  Thermal overload protection  Externally synchronizable Table 1. Device summary Order code Operating temp. range Package Packaging TDA7491MV13TR - 40 to 85 °C PowerSSO-36 EPD Tape and reel March 2014 This is information on a product in full production. DocID14576 Rev 4 1/28 www.st.com Contents TDA7491MV Contents 1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 4 2.1 Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 7 8 2/28 Compatibility with TDA7491 stereo BTL family . . . . . . . . . . . . . . . . . . . . 19 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.1 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.3 Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.4 Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.4.1 Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.4.2 Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.5 Filterless modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.6 Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.7 Protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.8 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.9 Heatsink requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DocID14576 Rev 4 TDA7491MV List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 How to set up SYNCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DocID14576 Rev 4 3/28 28 List of figures TDA7491MV List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. 4/28 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 THD vs output power (1 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 THD vs. output power (100 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 FFT (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FFT (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Closed-loop gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power dissipation and efficiency vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Attenuation vs. mute voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Current consumption vs. voltage on pin STBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Attenuation vs. voltage on pin STBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power supply rejection ratio vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Test board (TDA7491HV) layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Applications circuit for class-D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Standby and mute circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Turn-on/off sequence for minimizing speaker “pop” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Device input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Unipolar PWM output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Typical LC filter for a 8  speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Typical LC filter for a 4  speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Behavior of pin DIAG for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power derating curves for PCB used as heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DocID14576 Rev 4 TDA7491MV 1 Device block diagram Device block diagram Figure 1 shows the block diagram of the TDA7491MV. Figure 1. Internal block diagram DocID14576 Rev 4 5/28 28 Pin description TDA7491MV 2 Pin description 2.1 Pin out Figure 2. Pin connection (top view, PCB view) SUB_GND 1 36 VSS NC 2 35 SVCC NC 3 34 VREF NC 4 33 SGND NC 5 32 VDDS NC 6 31 GAIN1 NC 7 30 GAIN0 NC 8 29 SVR NC 9 28 DIAG 10 27 SGND 11 26 VDDS 12 25 SYNCLK 13 24 ROSC 23 INN OUTN OUTN PVCC PVCC 6/28 Exposed pad down PGND 14 PGND 15 22 INP OUTP 16 21 MUTE OUTP 17 20 STBY PGND 18 19 VDDPW DocID14576 Rev 4 TDA7491MV 2.2 Pin description Pin list Table 2. Pin description list Pin n° Name Type Description 1 SUB_GND POWER 2, 3 NC - No internal connection 4, 5 NC - No internal connection 6, 7 NC - No internal connection 8, 9 NC - No internal connection 10,11 OUTN OUT Negative PWM output 12,13 PVCC POWER Power supply 14,15 PGND POWER Power stage ground 16,17 OUTP OUT Positive PWM output 18 PGND POWER Power stage ground 19 VDDPW OUT 20 STBY INPUT Standby mode control 21 MUTE INPUT Mute mode control 22 INP INPUT Positive differential input 23 INN INPUT Negative differential input 24 ROSC OUT 25 SYNCLCK IN/OUT 26 VDDS OUT 27 SGND POWER 28 DIAG OUT Open-drain diagnostic output 29 SVR OUT Supply voltage rejection 30 GAIN0 INPUT Gain setting input 1 31 GAIN1 INPUT Gain setting input 2 32 VDDS POWER To be connected to VDDS (pin 26) 33 SGND POWER Signal ground 34 VREF OUT 35 SVCC POWER 36 VSS OUT Connect to the frame 3.3 V (nominal) regulator output referred to ground for power stage Master oscillator frequency-setting pin Clock in/out for external oscillator 3.3 V (nominal) regulator output referred to ground for signal blocks Signal ground Half VDDS (nominal) referred to ground Signal power supply 3.3 V (nominal) regulator output referred to power supply DocID14576 Rev 4 7/28 28 Electrical specifications TDA7491MV 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol 3.2 Parameter Value Unit 24 V VCC DC supply voltage for pins PVCCA, PVCCB, SVCC Top Operating temperature -40 to 85 °C Tj Junction temperature -40 to 150 °C Tstg Storage temperature -40 to 150 °C Min. Typ. Max. Unit - 2 3 - 24 - Thermal data Table 4. Thermal data Symbol Parameter Rth j-case Thermal resistance, junction to case Rth j-amb °C/W Thermal resistance, junction to ambient (mounted on recommended PCB)(1) 1. FR4 with vias to copper area of 9 cm2 (see also Section 7.9: Heatsink requirements on page 26). 3.3 Electrical specifications Unless otherwise stated, the results in Table 5 below are given for the conditions: VCC = 18 V, RL (load) = 8 , ROSC = R3 = 39 k, C8 = 100 nF, f = 1 kHz, GV = 20 dB, and Tamb = 25 °C. Table 5. Electrical specifications Symbol Condition Min. Typ. Max. Unit Supply voltage for pins PVCC, SVCC - 5 - 18 V Total quiescent Without LC filter - 26 35 mA Quiescent current in standby - - 2.5 5.0 µA VOS Output offset voltage Play mode -150 - 150 mV VOS Output offset voltage Mute mode -60 - 60 mV IOCP Overcurrent protection threshold RL = 0  3 5 - A Tj Junction temperature at thermal shutdown - - 150 - °C Ri Input resistance Differential input 55 60 - k 19 21 - V VCC Iq IqSTBY VOVP 8/28 Parameter Overvoltage protection threshold - DocID14576 Rev 4 TDA7491MV Electrical specifications Table 5. Electrical specifications (continued) Symbol Parameter Condition Min. Typ. Max. Unit - - - 4 V High side - 0.2 - Low side - 0.2 - THD = 10% - 20 - THD = 1% - 16 - RL = 8 , THD = 10% VCC = 12 V - 9.5 - RL = 8 , THD = 1% VCC = 12 V - 7.2 - RL = 6 , THD = 10% VCC = 16 V - 20 - RL = 6 , THD = 1% VCC = 16 V - 16 - Dissipated power Po = 20 W THD = 10% - 2.0 - W Efficiency Po = 20 W 80 90 - % Total harmonic distortion Po = 1 W - 0.1 0.2 % GAIN0 = L, GAIN1 = L 18 20 22 GAIN0 = L, GAIN1 = H 24 26 28 GAIN0 = H, GAIN1 = L 28 30 32 GAIN0 = H, GAIN1 = H 30 32 34 - -1 - 1 A Curve, GV = 20 dB - 20 - f = 22 Hz to 22 kHz - 25 35 40 50 - dB - 50 - ns 290 310 330 kHz 250 - - 250 - - 2.3 - - - - 0.8 60 80 - VUVP Undervoltage protection threshold RdsON Power transistor on resistance Po Po Po PD  THD GV GV eN Output power W Output power Output power W W Closed loop gain dB Gain matching Total input noise Supply voltage rejection ratio fr = 100 Hz, Vr = 0.5 V, CSVR = 10 µF Tr, Tf Rise and fall times - Switching frequency Internal oscillator With internal oscillator fSWR Output switching frequency VinH Digital input high (H) VinL Digital input low (L) AMUTE (1) With external oscillator (2) kHz Mute attenuation VMUTE = 1 V DocID14576 Rev 4 dB µV SVRR fSW  V dB 9/28 28 Electrical specifications TDA7491MV Table 5. Electrical specifications (continued) Symbol Parameter Condition VSTBY < 0.5 V, VMUTE = X Function Standby, mute and play modes mode Min. Typ. Unit Standby - VSTBY > 2.5 V, VMUTE < 0.8 V Mute - VSTBY > 2.5 V, VMUTE > 2.5 V Play - 1. fSW = 106 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 k (see Figure 18.) 2. fSW = fSYNCLK / 2 with the frequency of the external oscillator. 10/28 Max. DocID14576 Rev 4 TDA7491MV Characterization curves The following characterization curves were made using the TDA7491MV demo board. The LC filter for the 8- load uses components of 33 µH and 220 nF. All other test conditions are given along side the corresponding curves. Figure 3. Output power vs. supply voltage Output Power vs. Supply Voltage(8 ohm) Test Condition : Vcc = 5~18V, RL = 8 ohm, Rosc =39kO, Cosc =100nF, Output Power (W) 4 Characterization curves f =1kHz, Gv =30dB, Tamb =25℃ Specification Limit: Typical: Vs =18V,Rl = 8 ohm Po =20W @THD =10% 22 20 18 16 14 12 10 8 6 4 2 0 Po =16W @THD =1% THD =10% Rl =8 ohm f =1kHz THD =1% 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Supply Voltage (V) Figure 4. THD vs output power (1 kHz) THD (%) 10 Test Condition: 5 Vcc =18V, 2 RL= 8 ohm, 1 Rosc =39kΩ, Cosc =100nF, f =1kHz, Gv =30dB, Tamb =25℃ 0.5 0.2 0.1 0.05 Specification Limit: Typical: Po =20W @ THD =10% 0.02 0.01 0.005 100m 200m 500m 1 2 5 10 20 30 Output Power (W) DocID14576 Rev 4 11/28 28 Characterization curves TDA7491MV Figure 5. THD vs. output power (100 Hz) THD (%) 10 5 Test Condition: Vcc =18V, 2 RL= 8 ohm, 1 Rosc =39kΩ, Cosc =100nF, 0.5 f =100Hz, 0.2 Gv =30dB, Tamb =25℃ 0.1 0.05 Specification Limit: 0.02 Typical: 0.01 Po =20W @ THD =10% 0.005 100m 200m 500m 1 2 5 10 20 Output Power (W) Figure 6. THD vs. frequency THD (%) 1 Test Condition: Vcc =18V, 0.5 RL= 8 ohm, Rosc =39kΩ, Cosc =100nF, 0.2 f =1kHz, Gv =30dB, 0.1 Po =1W Tamb =25℃ 0.05 0.02 Specification Limit: Typical: THD60dB -130 for the harmonic frequency -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k 2k 5k 10k 20k Frequency (Hz) Figure 9. FFT (-60 dB) FFT (dB) +0 -10 Test Condition: -20 Vcc =18V, -30 RL= 8 ohm, -40 Rosc =39kΩ, Cosc =100nF, -50 f =1kHz, -60 Gv =30dB, -70 Po = -60dB (@ 1W =0dB) -80 -90 Tamb =25℃ -100 -110 Specification Limit: -120 Typical: > 90dB -130 for the harmonic frequency -140 -150 20 50 100 200 500 1k Frequency (Hz) Figure 10. Closed-loop gain vs. frequency +0. 5 Test Condition : Gain=32dB -0 Vcc = 18V, RL = 8 ohm, -0. 5 Gain=22dB Rosc =39kO, Cosc =100nF, -1 Gain=26dB 0dB@f=1kHz, Po=1w, Gv=32dB, Tamb =25℃ -1. 5 d B r Gain=30dB -2 Vcc=18V, -2. 5 Rload=8ohm, A -3 0dB@f=1kHz, Po=1w, Gv=32dB -3. 5 -4 -4.5 -5 20 50 100 200 500 1k 2k 5k 10k 20k 30k Hz TDA7491MV 8ohm Closed-loop gain vs Freq .at27 DocID14576 Rev 4 13/28 28 Characterization curves TDA7491MV Figure 11. Power dissipation and efficiency vs. output power Vcc = 18V, RL = 8 ohm, Rosc =39kO, Cosc =100nF, Gv =30dB, Tamb =25℃ 4 80 3.5 70 Efficiency (%) f =1kHz, 90 3 60 2.5 50 2 40 Vcc=18V 30 Rload=8ohm 1.5 1 Gain=30dB 20 f=1kHz 0.5 10 0 0 5 10 15 Output power per channel (W) 20 Dissipation Power (W) Power dissipation & Efficiency vs Output power Test Condition : 0 Figure 12. Attenuation vs. mute voltage Attenuation vs Mute voltage Test Condition : Vcc = 18V, RL = 8 ohm, 0dB@f =1kHz, Po=1w Gv =30dB, Tamb =25℃ Attenuation (dB) Rosc =39kO, Cosc =100nF, 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 Vcc=18V Rload=8ohm Gain=30dB 0dB@f=1kHz,Po=1w 0 0.5 1 1.5 2 Mute voltage (V) 2.5 3 3.5 Figure 13. Current consumption vs. voltage on pin STBY Iquiescent vs Standby voltage Test Condition : Vcc = 18V, 30 RL = 8 ohm, 25 Vin=0, Gv =30dB, Tamb =25℃ Iquiescent (mA) Rosc =39kO, Cosc =100nF, Vcc=18V 20 Rload=8ohm Gain=30dB 15 Vin=0 10 5 0 14/28 0 0.5 1 DocID14576 Rev 4 1.5 2 Standby voltage (V) 2.5 3 3.5 TDA7491MV Characterization curves Figure 14. Attenuation vs. voltage on pin STBY Attenuation vs Standby voltage Test Condition : Vcc = 5~18V, 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 RL = 8 ohm, 0dB@f=1kHz, Po=1w, Gv =30dB, Tamb =25℃ Attenuation (dB) Rosc =39kO, Cosc =100nF, Vcc=18V Rload=8ohm Gain=30dB 0dB@f=1kHz,Po=1W 0 0.5 1 1.5 2 Standby voltage (V) 2.5 3 3.5 Figure 15. Power supply rejection ratio vs. frequency +0 Test Condition : T -10 Vcc = 18V, -20 RL = 8 ohm, Rosc =39kO, Cosc =100nF, Ripple frequency=100Hz -30 Vin=0, Gv =30dB, Tamb =25℃ Ripple voltage=500mV -40 d B r -50 A -60 -70 -80 -90 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz DocID14576 Rev 4 15/28 28 Characterization curves 4.1 TDA7491MV Test board Figure 16. Test board (TDA7491HV) layout 16/28 DocID14576 Rev 4 TDA7491MV Package mechanical data The TDA7491MV comes in a 36-pin PowerSSO package with exposed pad down. Figure 17 below shows the package outline and Table 6 gives the dimensions. Figure 17. PowerSSO-36 EPD outline drawing h x 45° 5 Package mechanical data DocID14576 Rev 4 17/28 28 Package mechanical data TDA7491MV Table 6. PowerSSO-36 EPD dimensions Dimensions in mm Dimensions in inches Symbol Min. Typ. Max. Min. Typ. Max. A 2.15 - 2.47 0.085 - 0.097 A2 2.15 - 2.40 0.085 - 0.094 a1 0.00 - 0.10 0.000 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees L 0.60 - 1.00 0.024 - 0.039 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 6.50 - 7.10 0.256 - 0.280 In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 18/28 DocID14576 Rev 4 TDA7491MV 6 Applications circuit Applications circuit Figure 18. Applications circuit for class-D amplifier TDA7491MV Input settings for gain: 6.1 Input settings for standby, mute and play: GAIN0 : GAIN1 Nominal gain STBY : MUTE Mode 0V:0V 20 dB 0V:0V Standby 0 V : 3.3 V 26 dB 0 V : 3.3 V Standby 3.3 V : 0 V 30 dB 3.3 V : 0 V Mute 3.3 V : 3.3 V 32 dB 3.3 V : 3.3 V Play Compatibility with TDA7491 stereo BTL family TDA7491MV mono BTL analog class-D amplifier is derived from the TDA7491 stereo analog class-D BTL family. TDA7491MV has only the left channel of the stereo BTL family. In order to guarantee the pin to pin compatibility when moving the application from stereo to mono, it is necessary to connect the right channel inputs (pins 32 and 33 of TDA7491 BTL family) to VCC and GND, that is, pin 32 to VDDS and pin 33 to SGND. DocID14576 Rev 4 19/28 28 Application information TDA7491MV 7 Application information 7.1 Mode selection The three operating modes of the TDA7491MV are set by the two inputs STBY (pin 20) and MUTE (pin 21).  Standby mode: all circuits are turned off, very low current consumption.  Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty cycle.  Play mode: the amplifiers are active. The protection functions of the TDA7491MV are realized by pulling down the voltages of the STBY and MUTE inputs shown in Figure 19. The input current of the corresponding pins must be limited to 200 µA. Table 7. Mode settings Mode Selection STBY MUTE Standby L (1) X (don’t care) Mute H Play (1) L H H 1. Drive levels defined in Table 5: Electrical specifications on page 8 Figure 19. Standby and mute circuits Standby 3.3 V 0V STBY R2 30 k C7 2.2 µF R4 30 k C15 2.2 µF Mute 3.3 V 0V TDA7491MV MUTE Figure 20. Turn-on/off sequence for minimizing speaker “pop” 20/28 DocID14576 Rev 4 TDA7491MV 7.2 Application information Gain setting The gain of the TDA7491MV is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin 31). Internally, the gain is set by changing the feedback resistors of the amplifier. Table 8. Gain settings 7.3 GAIN0 GAIN1 Nominal gain, Gv (dB) 0 0 20 0 1 26 1 0 30 1 1 32 Input resistance and capacitance The input impedance is set by an internal resistor Ri = 60 k (typical). An input capacitor (Ci) is required to couple the AC input signal. The equivalent circuit and frequency response of the input components are shown in Figure 21. For Ci = 220 nF the high-pass filter cut-off frequency is below 20 Hz: fc = 1 / (2 *  * Ri * Ci) Figure 21. Device input circuit and frequency response Rf Input signal Ci Input pin Ri DocID14576 Rev 4 21/28 28 Application information 7.4 TDA7491MV Internal and external clocks The clock of the class-D amplifier can be generated internally or can be driven by an external source. If two or more class-D amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. This can be implemented by using one TDA7491MV as master clock, while the other devices are in slave mode (that is, externally clocked. The clock interconnect is via pin SYNCLK of each device. As explained below, SYNCLK is an output in master mode and an input in slave mode. 7.4.1 Master mode (internal clock) Using the internal oscillator, the output switching frequency, fSW, is controlled by the resistor, ROSC, connected to pin ROSC: fSW = 106 / ((16 * ROSC + 182) * 4) kHz where ROSC is in k. In master mode, pin SYNCLK is used as a clock output pin, whose frequency is: fSYNCLK = 2 * fSW For master mode to operate correctly then resistor ROSC must be less than 60 k as given below in Table 9. 7.4.2 Slave mode (external clock) In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin SYNCLK to be internally configured as an input as given in Table 9. The output switching frequency of the slave devices is: fSW = fSYNCLK / 2 Table 9. How to set up SYNCLK Mode ROSC SYNCLK Master ROSC < 60 k Output Slave Floating (not connected) Input Figure 22. Master and slave connection Master Slave TDA7491M ROSC TDA7491M SYNCLK Output Cosc 100 nF 22/28 Rosc 39 k DocID14576 Rev 4 SYNCLK Input ROSC TDA7491MV 7.5 Application information Filterless modulation The output modulation scheme of the BTL is called unipolar pulse width modulation (PWM). The differential output voltages change between 0 V and +VCC and between 0 V and -VCC. This is in contrast to the traditional bipolar PWM outputs which change between +VCC and -VCC. An advantage of this scheme is that it effectively doubles the switching frequency of the differential output waveform. The OUTP and OUTN are in the same phase when the input is zero, then the switching current is low and the loss in the load is small. In practice, a short delay is introduced between these two outputs in order to avoid the BTL output switching at the same time. TDA7491MV can be used without a filter before the speaker, because the frequency of the TDA7491MV output is beyond the audio frequency, the audio signal can be recovered by the inherent inductance of the speaker and natural filter of the human ear. Figure 23. Unipolar PWM output INP INN OUTP OUTN Differential OUT DocID14576 Rev 4 23/28 28 Application information 7.6 TDA7491MV Output low-pass filter To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The cutoff frequency should be larger than 22 kHz and much lower than the output switching frequency. It is necessary to choose the L-C component values depending on the loud speaker impedance. Some typical values, which give a cut-off frequency of 27 kHz, are shown in Figure 24 and Figure 25 below. Figure 24. Typical LC filter for a 8  speaker Figure 25. Typical LC filter for a 4  speaker 24/28 DocID14576 Rev 4 TDA7491MV 7.7 Application information Protection function The TDA7491MV is fully protected against overvoltage, undervoltage, overcurrent and thermal overloads as explained here. Overvoltage protection (OVP) If the supply voltage exceeds the value for VOVP given in Table 5: Electrical specifications on page 8 the overvoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage drops to below the threshold value the device restarts. Undervoltage protection (UVP) If the supply voltage drops below the value for VUVP given in Table 5: Electrical specifications on page 8 the undervoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage recovers the device restarts. Overcurrent protection (OCP) If the output current exceeds the value for IOCP given in Table 5: Electrical specifications on page 8 the overcurrent protection is activated which forces the outputs to the high-impedance state. Periodically, the device attempts to restart. If the overcurrent condition is still present then the OCP remains active. The restart time, TOC, is determined by the R-C components connected to pin STBY. Thermal protection (OTP) If the junction temperature, Tj, reaches 145 °C (nominal), the device goes to mute mode and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction temperature exceeds the value for Tj given in Table 5: Electrical specifications on page 8 the device shuts down and the output is forced to the high impedance state. When the device cools sufficiently the device restarts. 7.8 Diagnostic output The output pin DIAG is an open drain transistor. When the protection is activated it is in the high-impedance state. The pin can be connected to a power supply (< 18 V) by a pull-up resistor whose value is limited by the maximum sinking current (200 µA) of the pin. Figure 26. Behavior of pin DIAG for various protection conditions VDD TDA7491MV R1 DIAG Protection logic VDD Restart Restart Overcurrent protection OV, UV, OT protection DocID14576 Rev 4 25/28 28 Application information 7.9 TDA7491MV Heatsink requirements A thermal resistance of 24 °C/W can be obtained using the PCB copper ground layer with 16 vias connecting it to the contact area for the exposed pad. Ensure that the copper ground area is a nominal 9 cm2 for 24 °C/W. Figure 27 shows the derating curves for copper areas of 4 cm2 and 9 cm2. As with most amplifiers, the power dissipated within the device depends primarily on the supply voltage, the load impedance and the output modulation level. The maximum estimated power dissipation for the TDA7491MV is less than 4 W. When properly mounted on the above PCB the junction temperature could increase by 96 °C. However, with a musical program the dissipated power is about 40% less, leading to a temperature increase of around 60 °C. Even at the maximum recommended ambient temperature for consumer applications of 50 °C there is still a clear safety margin before the maximum junction temperature (150 °C) is reached. Figure 27. Power derating curves for PCB used as heatsink 3G:   &RSSHU$UHD[FP DQGYLDKROHV   7'$09 3662   &RSSHU$UHD[FP DQGYLDKROHV         7DPEƒ&  26/28 DocID14576 Rev 4      TDA7491MV 8 Revision history Revision history Table 10. Document revision history Date Revision Changes 21-Oct-2008 1 Initial release. 29-May-2009 2 Updated text concerning oscillator R and C in Section 3.3: Electrical specifications on page 8 Updated test condition for Iq, added VUVP, updated STBY and MUTE voltages and rectified several anomalies in Table 5: Electrical specifications on page 8 Updated equation for fSW on page 10 and on page 22 Updated Figure 16: Test board (TDA7491HV) layout on page 16 Updated Figure 17: PowerSSO-36 EPD outline drawing on page 17 and Table 6: PowerSSO-36 EPD dimensions on page 18 Updated Figure 18: Applications circuit for class-D amplifier on page 19 20-Feb-2014 3 Updated order code Table 1 on page 1 21-Mar-2014 4 Updated operating temperature range from 0 to 70 °C in - 40 to 85 °C Table 1 on page 1 and Table 3 on page 8 DocID14576 Rev 4 27/28 28 TDA7491MV Please Read Carefully: Information in this document is provided solely in connection with ST products. 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