TDA7492MV13TR

TDA7492MV 50 W mono BTL class-D audio amplifier Datasheet - production data Description The TDA7492MV is a mono BTL class-D audio amplifier with single power supply designed for home systems and docking stations. Thanks to the high efficiency and an exposed-pad-down (EPD) package no heatsink is required. PowerSSO-36 with exposed pad down Features  50 W continuous output power: RL = 6 , THD = 10% at VCC = 25 V  40 W continuous output power: RL = 8 , THD = 10% at VCC = 25 V  Wide range single supply operation (10 - 26 V)  High efficiency ( = 90%)  Four selectable, fixed gain settings of nominally 21.6 dB, 27.6 dB, 31.1 dB and 33.6 dB  Differential inputs minimize common-mode noise  Standby and mute features  Short-circuit protection  Thermal-overload protection  Externally synchronizable Table 1. Device summary Order code Operating temp. range Package Packaging TDA7492MV13TR 0 to 70 °C PowerSSO-36 EPD Tape and reel May 2020 This is information on a product in full production. DocID16264 Rev 3 1/28 www.st.com Contents TDA7492MV Contents 1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 4 5 6 2.1 Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 For 6  load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 For 8  load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/28 Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.5.2 Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.6 Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.7 Protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.8 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 7 5.5.1 PowerSSO-36 EPD package mechanical data . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DocID16264 Rev 3 TDA7492MV List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 How to set up SYNCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DocID16264 Rev 3 3/28 28 List of figures TDA7492MV List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. 4/28 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output power vs supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 THD vs output power (1 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 THD vs output power (100 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 THD vs frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 THD vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 FFT (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 FFT (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output power vs supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 THD vs output power (1 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 THD vs output power (100 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 THD vs frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 THD vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FFT (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FFT (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Test board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Applications circuit for class-D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Standby and mute circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Turn-on/off sequence for minimizing speaker “pop” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Device input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Typical LC filter for a 8  speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Typical LC filter for a 4  speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Behavior of pin DIAG for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DocID16264 Rev 3 TDA7492MV 1 Device block diagram Device block diagram Figure 1 shows the block diagram of the TDA7492MV. Figure 1. Internal block diagram DocID16264 Rev 3 5/28 28 Pin description TDA7492MV 2 Pin description 2.1 Pin out Figure 2. Pin connection (top view, PCB view) SUB_GND 1 36 VSS NC 2 35 SVCC NC 3 34 VREF NC 4 33 SGND2 NC 5 32 VDDS2 NC 6 31 GAIN1 NC 7 30 GAIN0 NC 8 29 SVR NC 9 28 DIAG OUTN 10 27 SGND OUTN 11 26 VDDS PVCC 12 25 SYNCLK PVCC 13 24 ROSC PGND 14 23 INN PGND 15 22 INP 16 21 MUTE 17 20 STBY 18 19 VDDPW OUTP OUTP PGND 6/28 EP, exposed pad down Connect to ground DocID16264 Rev 3 TDA7492MV 2.2 Pin description Pin list Table 2. Pin description list Pin n° Name Type Description 1 SUB_GND POWER Connect to the frame 2,3 NC - No internal connection 4,5 NC - No internal connection 6,7 NC - No internal connection 8,9 NC - No internal connection 10,11 OUTN OUT Negative PWM output 12,13 PVCC POWER Power supply for output channel 14,15 PGND POWER Power ground for output channel 16,17 OUTP OUT Positive PWM output 18 PGND POWER Power supply ground 19 VDDPW OUT 3.3-V (nominal) regulator output referred to ground for power stage 20 STBY INPUT Standby mode control 21 MUTE INPUT Mute mode control 22 INP INPUT Positive differential input 23 INN INPUT Negative differential input 24 ROSC OUT Master oscillator frequency-setting pin 25 SYNCLCK IN/OUT Clock in/out for external oscillator 26 VDDS OUT 3.3-V (nominal) regulator output referred to ground for signal blocks 27 SGND POWER Signal ground 28 DIAG OUT Open-drain diagnostic output 29 SVR OUT Supply voltage rejection 30 GAIN0 INPUT Gain setting input 1 31 GAIN1 INPUT Gain setting input 2 32 VDDS2 INPUT To be connected to VDDS (pin 26) 33 SGND2 INPUT To be connected to SGND (pin 27) 34 VREF OUT Half VDDS (nominal) referred to ground 35 SVCC POWER Signal power supply 36 VSS OUT 3.3-V (nominal) regulator output referred to power supply - EP - Exposed pad for ground-plane heatsink, to be connected to ground DocID16264 Rev 3 7/28 28 Electrical specifications TDA7492MV 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol 3.2 Parameter Value Unit VCC DC supply voltage for pins PVCC, SVCC 30 V VI Voltage limits for input pins STBY, MUTE, INN, INP, GAIN0, GAIN1 -0.3 - 3.6 V Top Operating temperature 0 to 70 °C Tj Junction temperature -40 to 150 °C Tstg Storage temperature -40 to 150 °C Thermal data Table 4. Thermal data 3.3 Symbol Parameter Rth j-case Thermal resistance, junction to case Min - Typ 2 Max 3 Unit °C/W Electrical specifications Unless otherwise stated, the results in Table 5 below are given for the conditions: VCC = 25 V, RL (load) = 8 , ROSC = R3 = 39 k, C8 = 100 nF, f = 1 kHz, GV = 21.6 dB and Tamb = 25 °C. Table 5. Electrical specifications Symbol 8/28 Parameter Condition Min Typ Max Unit VCC Supply voltage for pins PVCCA, PVCCB, SVCC - 10 - 26 V Iq Total quiescent current Without LC - 26 35 mA IqSTBY Quiescent current in standby - - 2.5 5.0 µA VOS Output offset voltage Play mode -100 - 100 Mute mode -60 - 60 IOCP Overcurrent protection threshold RL = 0  4.8 6.0 - A Tj Junction temperature at thermal shutdown - - 150 - °C Ri Input resistance Differential input 48 60 - k VOVP Overvoltage protection threshold - 28 29 - V VUVP Undervoltage protection threshold - - 7 V - DocID16264 Rev 3 mV TDA7492MV Electrical specifications Table 5. Electrical specifications (continued) Symbol Parameter Condition RdsON Power transistor on resistance Po Output power Po Output power Min Typ Max High side - 0.2 - Low side - 0.2 - THD = 10% - 40 - THD = 1% - 32 - RL = 6 , THD = 10%, VCC = 25V - 50 - RL = 6 , THD = 1% VCC = 25V - 40 - Unit  W W PD Dissipated power Po =40W, THD = 10% - 4.0 - W  Efficiency Po = 40 W 80 90 - % THD Total harmonic distortion Po = 1 W - 0.1 0.4 % GAIN0 = L, GAIN1 = L 20.6 21.6 22.6 GAIN0 = L, GAIN1 = H 26.6 27.6 28.6 GAIN0 = H, GAIN1 = L 30.1 31.1 32.1 GAIN0 = H, GAIN1 = H 32.6 33.6 34.6 - -1 - 1 A Curve, GV = 20 dB - 20 - f = 22 Hz to 22 kHz - 25 35 GV Closed-loop gain dB GV Gain matching eN Total input noise SVRR Supply voltage rejection ratio fr = 100 Hz, Vr = 0.5 V, CSVR = 10 µF 40 50 - dB Tr, Tf Rise and fall times - - 50 - ns fSW Switching frequency Internal oscillator 290 310 330 kHz 250 - 400 250 - 400 2.3 - - - - 0.8 60 80 - fSWR Output switching frequency range VinH Digital input high (H) VinL Digital input low (L) AMUTE Mute attenuation With internal oscillator With external oscillator VMUTE = 1 V (1) (2) dB µV kHz V dB 1. fSW = 106 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 k (see Figure 20.). 2. fSW = fSYNCLK / 2 with the frequency of the external oscillator. DocID16264 Rev 3 9/28 28 Characterization curves 4 TDA7492MV Characterization curves The following characterization curves were made using the TDA7492MV exposed-paddown test board with VCC = 25 V, a signal frequency of 1 kHz and an output power of 1 W unless otherwise specified. The LC filter for the 8- load uses components of 33 µH and 220 nF and for the 6- load 22 µH and 220 nF. 4.1 For 6  load Figure 3. Output power vs supply voltage 52 48 O utput P ow er (W ) 44 THD = 10% 40 36 32 THD = 1% 28 24 20 16 12 15 16 17 18 19 20 21 22 23 24 S upply V oltage (V ) Figure 4. THD vsvs. output THD Outputpower Power (1 kHz) THD (%) 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 200m 500m 1 2 5 Output Power (W) 10/28 DocID16264 Rev 3 10 20 60 25 TDA7492MV Characterization curves Figure 5. THD vs Output outputPower power (100 Hz) THD vs. THD (%) 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 200m 500m 1 2 5 10 20 60 Output Power (W) Figure 6. THD vs frequency (100 mW) THD vs. Frequency THD (%) 0.5 0.4 0.3 0.2 0.1 0.08 0.06 0.05 0.04 0.03 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Figure 7. THD vs frequency THD vs. Frequency THD (%) 0.5 0.4 0.3 0.2 0.1 0.08 0.06 0.05 0.04 0.03 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) DocID16264 Rev 3 11/28 28 Characterization curves TDA7492MV Figure 8. Frequency q y p response Ampl (dB) +2 +1 -0 -1 -2 -3 -4 -5 10 20 50 100 200 500 1k 2k 5k 10k 30k Frequency (Hz) Figure 9. FFT (0 dB) FFT (0 dB) FFT (dB) +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Figure 10. (-60 dB) FFT FFT ( 60 dB) FFT (dB) +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k Frequency (Hz) 12/28 DocID16264 Rev 3 2k 5k 10k 20k TDA7492MV For 8  load Figure 11. Output power vs supply voltage 42 38 Output Power (W) 4.2 Characterization curves 34 THD = 10% 30 26 THD = 1% 22 18 14 10 15 16 17 18 19 20 21 22 Supply Voltage (V) 23 24 25 Figure 12. THD vs output power (1 kHz) THD vs. Output Power THD (%) 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 100m 200m 500m 1 2 5 10 20 60 Output Power (W) DocID16264 Rev 3 13/28 28 Characterization curves TDA7492MV Figure 13. THD vs output power (100 Hz) THD vs. Output Power THD (%) 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 100m 200m 500m 1 2 5 10 20 60 Output Power (W) Figure 14. THD THD vs frequency (100 mW) vs. Frequency THD (%) 0.5 0.4 0.3 0.2 0.1 0.08 0.06 0.05 0.04 0.03 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k Frequency (Hz) FigureTHD 15. THD vs frequency vs. Frequency THD (%) 0.5 0.4 0.3 0.2 0.1 0.08 0.06 0.05 0.04 0.03 0.02 0.01 20 50 100 200 500 1k Frequency (Hz) 14/28 DocID16264 Rev 3 2k 5k 10k 20k 20k TDA7492MV Characterization curves Figure 16.Frequency Frequency response Response Ampl (dB) +2 +1 -0 -1 r -2 -3 -4 -5 10 20 50 100 200 500 1k 2k 5k 10k 30k Frequency (Hz) Figure 17. FFT (0 dB) FFT (0 dB) FFT (dB) +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Figure 18. FFT (-60 dB) FFT (-60 dB) FFT (dB) +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) DocID16264 Rev 3 15/28 28 Characterization curves 4.3 TDA7492MV Test board Figure 19. Test board layout 16/28 DocID16264 Rev 3 TDA7492MV Applications information 5 Applications information 5.1 Applications circuit Figure 20. Applications circuit for class-D amplifier TDA7492MV DocID16264 Rev 3 17/28 28 Applications information 5.2 TDA7492MV Mode selection The three operating modes of the TDA7492MV are set by the two inputs STBY (pin 20) and MUTE (pin 21).  Standby mode: all circuits are turned off, very low current consumption.  Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty cycle.  Play mode: the amplifiers are active. The protection functions of the TDA7492MV are realized by pulling down the voltages of the STBY and MUTE inputs shown in Figure 21. The input current of the corresponding pins must be limited to 200 µA. Table 6. Mode settings Mode Selection STBY MUTE L (1) Standby Mute H Play H X (don’t care) (1) L H 1. Drive levels defined in Table 5: Electrical specifications on page 8 Figure 21. Standby and mute circuits Standby 3.3 V 0V STBY R2 30 k C7 2.2 µF R4 30 k C15 2.2 µF Mute 3.3 V 0V TDA7492MV MUTE Figure 22. Turn-on/off sequence for minimizing speaker “pop” 18/28 DocID16264 Rev 3 TDA7492MV 5.3 Applications information Gain setting The gain of the TDA7492MV is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin 31). Internally, the gain is set by changing the feedback resistors of the amplifier. Table 7. Gain settings 5.4 GAIN0 GAIN1 Nominal gain, Gv (dB) L L 21.6 L H 27.6 H L 31.1 H H 33.6 Input resistance and capacitance The input impedance is set by an internal resistor Ri = 60 k (typical). An input capacitor (Ci) is required to couple the AC input signal. The equivalent circuit and frequency response of the input components are shown in Figure 23. For Ci = 470 nF the high-pass filter cut-off frequency is below 20 Hz: fc = 1 / (2 *  * Ri * Ci) Figure 23. Device input circuit and frequency response Rf Input signal Ci Input pin Ri DocID16264 Rev 3 19/28 28 Applications information 5.5 TDA7492MV Internal and external clocks The clock of the class-D amplifier can be generated internally or can be driven by an external source. If two or more class-D amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. This can be implemented by using one TDA7492MV as master clock, while the other devices are in slave mode (that is, externally clocked. The clock interconnect is via pin SYNCLK of each device. As explained below, SYNCLK is an output in master mode and an input in slave mode. 5.5.1 Master mode (internal clock) Using the internal oscillator, the output switching frequency, fSW, is controlled by the resistor, ROSC, connected to pin ROSC: fSW = 106 / ((16 * ROSC + 182) * 4) kHz where ROSC is in k. In master mode, pin SYNCLK is used as a clock output pin, whose frequency is: fSYNCLK = 2 * fSW For master mode to operate correctly then resistor ROSC must be less than 60 k as given below in Table 8. 5.5.2 Slave mode (external clock) In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin SYNCLK to be internally configured as an input as given in Table 8. The output switching frequency of the slave devices is: fSW = fSYNCLK / 2 Table 8. How to set up SYNCLK Mode 20/28 ROSC SYNCLK Master ROSC < 60 k Output Slave Floating (not connected) Input DocID16264 Rev 3 TDA7492MV Applications information Figure 24. Master and slave connection Master Slave TDA7492xy ROSC TDA7492M SYNCLK Output Cosc 100 nF SYNCLK ROSC Input Rosc 39 k DocID16264 Rev 3 21/28 28 Applications information 5.6 TDA7492MV Output low-pass filter To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The cutoff frequency should be larger than 22 kHz and much lower than the output switching frequency. It is necessary to choose the L-C component values depending on the loud speaker impedance. Some typical values, which give a cut-off frequency of 27 kHz, are shown in Figure 25 and Figure 26 below. Figure 25. Typical LC filter for a 8  speaker Figure 26. Typical LC filter for a 4  speaker 5.7 Protection function The TDA7492MV is fully protected against overvoltage, undervoltage, overcurrent and thermal overloads as explained here. Overvoltage protection (OVP) If the supply voltage exceeds the value for VOVP given in Table 5: Electrical specifications on page 8 the overvoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage falls back to within the operating range the device restarts. Undervoltage protection (UVP) If the supply voltage drops below the value for VUVP given in Table 5: Electrical specifications on page 8 the undervoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage recovers to within the operating range the device restarts. 22/28 DocID16264 Rev 3 TDA7492MV Applications information Overcurrent protection (OCP) If the output current exceeds the value for IOCP given in Table 5: Electrical specifications on page 8 the overcurrent protection is activated which forces the outputs to the high-impedance state. Periodically, the device attempts to restart. If the overcurrent condition is still present then the OCP remains active. The restart time, TOC, is determined by the R-C components connected to pin STBY. Thermal protection (OTP) If the junction temperature, Tj, reaches 145 °C (nominal), the device goes to mute mode and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction temperature exceeds the value for Tj given in Table 5: Electrical specifications on page 8 the device shuts down and the output is forced to the high impedance state. When the device cools sufficiently the device restarts. 5.8 Diagnostic output The output pin DIAG is an open drain transistor. When the protection is activated it is in the high-impedance state. The pin can be connected to a power supply (< 26 V) by a pull-up resistor whose value is limited by the maximum sinking current (200 µA) of the pin. Figure 27. Behavior of pin DIAG for various protection conditions VDD TDA7492MV R1 DIAG Protection logic VDD Restart Restart Overcurrent protection OV, UV, OT protection DocID16264 Rev 3 23/28 28 Package information 6 TDA7492MV Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 24/28 DocID16264 Rev 3 TDA7492MV PowerSSO-36 EPD package mechanical data The TDA7492MV comes in a 36-pin PowerSSO package with exposed pad down. Figure 28 below shows the package outline and Table 9 gives the dimensions. Figure 28. PowerSSO-36 EPD outline drawing h x 45° 6.1 Package information DocID16264 Rev 3 25/28 28 Package information TDA7492MV Table 9. PowerSSO-36 EPD dimensions Dimensions in mm Dimensions in inches Symbol 26/28 Min. Typ. Max. Min. Typ. Max. A 2.15 - 2.47 0.085 - 0.097 A2 2.15 - 2.40 0.085 - 0.094 a1 0.00 - 0.10 0.000 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees L 0.60 - 1.00 0.024 - 0.039 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 6.50 - 7.10 0.256 - 0.280 DocID16264 Rev 3 TDA7492MV 7 Revision history Revision history Table 10. Document revision history Date Revision Changes 20-Oct-2009 1 Initial release 20-Feb-2014 2 Updated order code Table 1 on page 1 11-May-2020 3 Updated Y dimensions in Table 9 DocID16264 Rev 3 27/28 28 TDA7492MV IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved 28/28 DocID16264 Rev 3