TDA7492PE
45 W + 45 W dual BTL class-D audio amplifier
Datasheet - production data
•
•
•
•
•
•
•
•
Features
•
•
•
•
•
Wide-range single-supply operation
(7 - 26 V)
Possible output configurations:
−
2 x PBTL
−
1 x Parallel BTL
BTL output capabilities (VCC = 22 V):
−
::ȍ7+'
−
::ȍ7+'
−
::ȍ7+'
−
::ȍ7+'
−
::ȍ7+'
−
::ȍ7HD 10%
Parallel BTL output capabilities (VCC = 22 V):
−
:ȍ7+'
−
:ȍ7+'
High efficiency
February 2017
Four selectable, fixed-gain settings of
nominally 20.8 dB, 26.8 dB, 30 dB and
32.8 dB
Differential inputs minimize common-mode
noise
Standby, mute and play operating modes
Short-circuit protection
Output power limited by PLIMIT function
Detection of shorted output pins during
startup
Thermal overload protection
ECOPACK® environmentally friendly
package
Description
The TDA7492PE is a dual BTL class-D audio
amplifier with single power supply designed for
home audio applications.
The device is housed in a 36-pin PowerSSO
package with exposed pad down (EPD) to
facilitate power dissipation through a properly
designed PCB area underneath the TDA7492PE.
Table 1: Device summary
Order code
Package
-40 to +85°C
PowerSSO-36
EPD
TDA7492PE
TDA7492PETR
DocID027029 Rev 2
This is information on a product in full production.
Operating
temp. range
Packaging
Tube
Tape and
reel
1/23
www.st.com
Contents
TDA7492PE
Contents
1
Device block diagram...................................................................... 5
2
Pin description ................................................................................ 6
3
4
2.1
Pinout................................................................................................ 6
2.2
Pin list ............................................................................................... 7
Electrical specifications.................................................................. 8
3.1
Absolute maximum ratings ................................................................ 8
3.2
Thermal data ..................................................................................... 8
3.3
Electrical specifications ..................................................................... 9
3.4
Stereo BTL application.................................................................... 10
3.5
Parallel BTL (mono) application ...................................................... 10
Application information ................................................................ 11
4.1
Gain setting ..................................................................................... 11
4.2
Stereo and mono applications......................................................... 11
4.3
Smart protections ............................................................................ 11
4.4
4.3.1
Overcurrent protection (OCP) .......................................................... 11
4.3.2
Thermal protection............................................................................ 12
4.3.3
Power limit ........................................................................................ 12
Mode selection ................................................................................ 13
5
Schematic diagram........................................................................ 15
6
Characterization curves ................................................................ 17
7
Package information ..................................................................... 19
7.1
8
2/23
PowerSSO36 EPD package information......................................... 19
Revision history ............................................................................ 22
DocID027029 Rev 2
TDA7492PE
List of tables
List of tables
Table 1: Device summary ...........................................................................................................................1
Table 2: Pin description list .........................................................................................................................7
Table 3: Absolute maximum ratings ...........................................................................................................8
Table 4: Thermal data.................................................................................................................................8
Table 5: Electrical specifications.................................................................................................................9
Table 6: Stereo BTL application ...............................................................................................................10
Table 7: Stereo BTL (mono) application ...................................................................................................10
Table 8: Gain settings ...............................................................................................................................11
Table 9: Overcurrent protection ................................................................................................................11
Table 10: Overcurrent protection (mute mode) ........................................................................................12
Table 11: Max effective voltage of PLIMIT pin vs. power supply and load...............................................13
Table 12: Mode settings............................................................................................................................13
Table 13: BTL configuration......................................................................................................................16
Table 14: PowerSSO-36 EPD package mechanical data ........................................................................21
Table 15: Document revision history ........................................................................................................22
DocID027029 Rev 2
3/23
List of figures
TDA7492PE
List of figures
Figure 1: Internal block diagram (showing one channel only) ....................................................................5
Figure 2: Pin connections (top view, PCB view) .........................................................................................6
Figure 3: Mono BTL settings.....................................................................................................................11
Figure 4: Recommended power limit pin connections..............................................................................12
Figure 5: Standby and mute circuits .........................................................................................................14
Figure 6: Turn-on/off sequence for minimizing speaker “pop”..................................................................14
Figure 7: Application circuit.......................................................................................................................15
Figure 8: Output power vs. supply voltage ...............................................................................................17
Figure 9: Efficiency vs. output power........................................................................................................17
Figure 10: THD vs. output power (f = 1 kHz) ............................................................................................17
Figure 11: THD vs. output power (100 Hz) ...............................................................................................17
Figure 12: THD vs. frequency...................................................................................................................17
Figure 13: Frequency response................................................................................................................17
Figure 14: FFT (0 dB) ...............................................................................................................................18
Figure 15: FFT (-60 dB) ............................................................................................................................18
Figure 16: PSRR parameter .....................................................................................................................18
Figure 17: PowerSSO-36 EPD package outline.......................................................................................20
4/23
DocID027029 Rev 2
Device block diagram
TDA7492PE
Device block diagram
Figure 1: "Internal block diagram (showing one channel only)" shows the block diagram of
one of the two identical channels of the TDA7492PE.
Figure 1: Internal block diagram (showing one channel only)
GAIN
PLMT
Gain Settings
Power Limit
+
INP
+
-
INN
-
+
Gate
Driver
OUTP
Gate
Driver
OUTN
+
-
VREF
+
+
-
-
PWM logic level shift
1
ROSC
Oscillator
SYNCLK
Standby Mute/Play
STANDBY
MUTE
Thermal,Undervoltage
Overcurrent protections
DIAG
DocID027029 Rev 2
VDD,VSS Regulators
VDDS
VSS
5/23
Pin description
TDA7492PE
2
Pin description
2.1
Pinout
Figure 2: Pin connections (top view, PCB view)
6/23
S UB _G ND
1
36
VS S
OUTP B
2
35
S VC C
OUTP B
3
34
VR E F
P G NDB
4
33
INNB
P G NDB
5
32
INP B
P VC C B
6
31
G AIN
P VC C B
7
30
P LIMIT
OUTNB
8
29
S VR
OUTNB
9
28
DIAG
OUTNA
10
27
S G ND
OUTNA
11
26
VDDS
P VC C A
12
25
S Y NC LK
P VC C A
13
24
R OS C
P G NDA
14
23
INNA
P G NDA
15
22
INP A
OUTP A
16
21
MUTE
OUTP A
17
20
S TB Y
P G ND
18
19
VDDP W
EP
Exposed pad down
(Connected to ground )
DocID027029 Rev 2
TDA7492PE
2.2
Pin description
Pin list
Table 2: Pin description list
Number
Name
Type
Description
1
SUB_GND
PWR
2, 3
OUTPB
O
4, 5
PGNDB
PWR
Power stage ground for right channel
6, 7
PVCCB
PWR
Power supply for right channel
8, 9
OUTNB
O
Negative PWM output for right channel
10, 11
OUTNA
O
Negative PWM output for left channel
12, 13
PVCCA
PWR
Power supply for left channel
14, 15
PGNDA
PWR
Power stage ground for left channel
16, 17
OUTPA
O
Positive PWM output for left channel
18
PGND
PWR
19
VDDPW
O
3.3 V (nominal) regulator output referred to ground for
power stage
20
STBY
I
Standby mode control
21
MUTE
I
Mute mode control
22
INPA
I
Positive differential input of left channel
23
INNA
I
Negative differential input of left channel
Connect to the frame
Positive PWM for right channel
Power stage ground
24
ROSC
O
Master oscillator frequency-setting pin
25
SYNCLK
I/O
Clock in/out for external oscillator
26
VDDS
O
3.3 V (nominal) regulator output referred to ground for
signal blocks
27
SGND
PWR
28
DIAG
O
Open-drain diagnostic output
29
SVR
O
Supply voltage rejection
30
PLIMIT
I
Output voltage level setting
31
GAIN
I
Gain setting input
32
INPB
I
Positive differential input of right channel
33
INNB
I
Negative differential input of right channel
Half VDDS (nominal) referred to ground
Signal ground
34
VREF
O
35
SVCC
PWR
36
VSS
O
3.3 V (nominal) regulator output referred to power supply
-
EP
-
Exposed pad for heatsink, to be connected to GND
Signal power supply
DocID027029 Rev 2
7/23
Electrical specifications
TDA7492PE
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3: Absolute maximum ratings
Symbol
VCC
VI
3.2
Parameter
Value
Unit
30
V
Voltage limits for input pins STBY, MUTE, INNA, INPA,
INNB, INPB, GAIN, MODE
DC supply voltage for pins PVCCA, PVCCB, SVCC
-0.3 to +4.6
V
Tj
Operating junction temperature
-40 to +150
°C
Top
Operating ambient temperature
-40 to +85
°C
Tstg
Storage temperature
-40 to +150
°C
Thermal data
Table 4: Thermal data
Symbol
8/23
Parameter
Rth j-case
Thermal resistance, junction-to-case
Rth j-amb
Thermal resistance, junction-to-ambient
DocID027029 Rev 2
Min.
Typ.
Max.
Unit
-
2.98
°C/W
24
°C/W
TDA7492PE
3.3
Electrical specifications
Electrical specifications
Unless otherwise stated, the results in below are given for the conditions: VCC = 22 V,
RL ȍ5OSC 5 NȍI N+]*V = 20.8 dB and Tamb = 25 °C.
Table 5: Electrical specifications
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Supply voltage for pins
PVCCA, PVCCB, SVCC
-
7
-
26
V
Total quiescent current
No LC filter, no load
-
40
IqSTBY
Quiescent current in
standby
-
-
1
VOS
Output offset voltage
Vi = 0, no load
IOCP
Overcurrent protection
threshold to switch off
the device
Tj
Junction temperature at
thermal shutdown
-
Ri
Input resistance
Differential input
Power transistor onresistance
High side
-
0.2
-
Low side
-
0.2
-
20.8
-
Iq
RdsON
Condition
Closed-loop gain
13
A
140
150
160
°C
60
-
Nȍ
0.25*Vdd < GAIN < 0.5*Vdd
-
26.8
-
0.5*Vdd < GAIN < 0.75*Vdd
-
30
-
GAIN1 > 0.75*Vdd
-
32.8
-
Gain matching
-
Cross talk
f = 1 kHz, PO = 1 W
Supply voltage rejection
ratio
fr = 100 Hz, Vr = 0.5 Vpp,
CSVR = 10 μF
-
Rise and fall times
-
fSW
Switching frequency
Internal oscillator
fSWR
Output switching
frequency range
With internal oscillator by
changing Rosc(1)
VinH
Digital input high (H)
VinL
Digital input low (L)
Function
mode
Standby, Mute, Play
-
Mute attenuation
dB
-
±1
dB
-
dB
60
-
dB
24
40
ns
kHz
450
-
550
2.0
-
-
-
-
0.8
kHz
V
Standby
STBY > 2.5 V Mute < 0.8 V
Mute
STBY > 2.5 V Mute > 2.5 V
Play
VMUTE = 1 V
ȍ
70
500
STBY < 0.5 V Mute = X
AMUTE
mV
10
CT
Tr, Tf
μA
9
ǻ*V
SVRR
-
20
GAIN < 0.25*Vdd
GV
mA
60
80
-
dB
Notes:
(1)f
6
SW = 10 / [( ROSC * 12 + 110) * 4] kHz, fSYNCLK = 2 * fSW (where ROSC LVLQNȍDQGISW in kHz) with
5RVF Nȍ
DocID027029 Rev 2
9/23
Electrical specifications
3.4
TDA7492PE
Stereo BTL application
All specifications are for VCC 95RVF NȍI N+]7DPE = 25 °C, unless
otherwise specified.
Table 6: Stereo BTL application
Symbol
Po
THD
VN
3.5
Parameter
Condition
Min.
Typ.
Max.
RL ȍ7+'
-
41
-
RL ȍ7+'
-
32
-
RL ȍ7+'
VCC = 18 V
-
27
-
RL ȍ7+'
VCC = 18 V
-
21
-
Total harmonic distortion
Po = 1 W, fin = 1 kHz
-
0.04
-
%
Total output noise
Inputs shorted and
connected to GND,
A Curve, GV = 20.8 dB
-
150
-
μV
Output power
Unit
W
Parallel BTL (mono) application
All specifications are for VCC 95RVF NȍI N+]7DPE = 25 °C, INPB, INNB
connected to VDDS, unless otherwise specified.
Table 7: Stereo BTL (mono) application
Symbol
Po
THD
VN
10/23
Parameter
Condition
Min.
Typ.
Max.
RL ȍ7+'
-
90
-
RL ȍ7+'
-
70
-
RL ȍ7+'
Vcc = 18 V
-
53
-
RL ȍ7+'
Vcc = 18 V
-
41
-
Total harmonic distortion
Po = 1 W, fin = 1 kHz
-
0.04
-
%
Total output noise
Inputs shorted and
connected to GND,
A Curve, GV = 20.8 dB
-
150
-
μV
Output power
DocID027029 Rev 2
Unit
W
TDA7492PE
Application information
4
Application information
4.1
Gain setting
The four gain settings of the TDA7492PE are set by GAIN (pin 31). Internally, gain is set by
changing the feedback resistors of the amplifier. The gain setting pins can be controlled by
standard logic drivers.
Table 8: Gain settings
Voltage on GAIN pin
Total gain
VGAIN < 0.25*VDDS
20.8 dB
GAIN pin connected to SGND
0.25*VDDS < VGAIN < 0.5*VDDS
26.8 dB
External resistor divider < 100 k
30 dB
External resistor divider < 100 k
0.5*VDDS < VGAIN < 0.75*VDDS
VGAIN > 0.75*VDDS
4.2
Application recommendations
32.8 dB
GAIN pin connected to VDDS
Stereo and mono applications
The TDA7492PE can be used in stereo BTL or in mono BTL configuration. When the input
pins, INPB and INNB of the right channel are directly shorted to VDDS (without input
capacitors) the device is in mono configuration as shown in Figure 3: "Mono BTL settings".
Figure 3: Mono BTL settings
OUTPB
INPA
INNA
IC
INPB
INNB
OUTPA
OUTNA
LC
Filter
OUTNB
4.3
Smart protections
4.3.1
Overcurrent protection (OCP)
If the overcurrent protection threshold is reached, the power stage will be shut down
immediately. The device will recover automatically when the fault is removed.
Table 9: Overcurrent protection
I (Shutdown)
High side (A)
11.2
Low side (A)
10.0
DocID027029 Rev 2
11/23
Application information
TDA7492PE
The thresholds in mute mode are reduced to about 1/2 and two typical thresholds are as
follows.
Table 10: Overcurrent protection (mute mode)
I (Shutdown)
4.3.2
High side (A)
6.2
Low side (A)
5.9
Thermal protection
When internal die temperature exceeds 140 °C, the device enters into Mute by pulling the
MUTE pin low first.
When internal die temperature exceeds 150 °C, the device directly shuts down the power
stage. The TDA7492PE automatically recovers when the temperature become lower than
the threshold.
4.3.3
Power limit
A built-in power limit is used to limit the output voltage level below the supply rail by limiting
the duty cycle. The limit level is set through the voltage at PLIMIT (pin 30). The pin voltage
is set by the following equation:
(ܴ݀݊//400݇)
൨
ܸܸܲ = ܶܫܯܫܮ
(ܴ݀݊//400݇ + ܴ)ݑ
Figure 4: Recommended power limit pin connections
VDDS
PLIMIT
400 N
Rup
Rdn
Power
Limiter
,WLVUHFRPPHQGHGWKDWH[WHUQDOUHVLVWRUVDUHOHVVWKDQNȍLIDYROWDJHGLYLGHULVXVHGDV
shown in Figure 4: "Recommended power limit pin connections". The relationship of the
maximum duty cycle (Dmax) and the voltage at PLIMIT is:
ቐ8.8 ×
= ݔܽ݉ܦ
ܸܲܶܫܯܫܮ
2 × ܸ × ܴ ݏ+ 1ቑ
ܸ െ
ܴ݈ × ݀ܽ2 × ܴݏ
2
Where VCC is the power supply voltage, VPLIMIT is the voltage applied at the PLIMIT pin, Rs
is the series resistance including Rdson of the power transistor, output filter resistance and
bonding wire resistance. Rload is the load resistance.
12/23
DocID027029 Rev 2
TDA7492PE
Application information
An example of maximum effective control voltage at PLIMIT vs. power supply and load
resistance is shown in Table 11: "Max effective voltage of PLIMIT pin vs. power supply and
load".
Table 11: Max effective voltage of PLIMIT pin vs. power supply and load
Power supply
Rload
4.4
7V
13 V
24 V
ȍ
0.71 V
1.32 V
2.44 V
ȍ
0.74 V
1.37 V
2.53 V
ȍ
0.75 V
1.39 V
2.57 V
Mode selection
The three operating modes of the TDA7492PE are set by two inputs: STBY (pin 20) and
MUTE (pin 21).
•
•
•
Standby mode: all circuits are turned off, very low current consumption.
Mute mode: inputs are connected to ground and the positive and negative PWM
outputs are at 50% duty cycle
Play mode: the amplifiers are active.
The protection functions of the TDA7492PE are implemented by pulling down the voltages
of the STBY and MUTE inputs shown in Figure 5: "Standby and mute circuits". The input
current of the corresponding pins must be limited to 200 μA.
Table 12: Mode settings
Mode
STBY
MUTE
Standby
L(1)
X (don’t care)
Mute
H
L
Play
H
H
Notes:
(1)Drive
levels defined in Table 5: "Electrical specifications".
DocID027029 Rev 2
13/23
Application information
TDA7492PE
Figure 5: Standby and mute circuits
R2
Standby
3.3 V
STBY
33 k
0V
C7
Mute
2.2 μF
R4
3.3 V
0V
20
21
TDA7492PE
MUTE
33 k
C15
2.2 μF
Figure 6: Turn-on/off sequence for minimizing speaker “pop”
14/23
DocID027029 Rev 2
5
TDA7492PE
For
Single-Ended
Input
J8
OU T
Input
Single-Ended
S1 STB Y
1
2
3
3V3 POWER SUPP LY
2 GN D C9
100nF
1.2k
R8 VCC
33k
33k
R2
R4
1uF
C12
1uF
C11
J15
J3
J10
100k
R12
100k
For
100k
R3
39K
J11
2
C8
100nF
C6
100nF
R11
1
R7
22R
R10
47k
R14
100k
S2 MUTE
1
2
3
PS
C5
100nF
+
C7
2.2uF
16V
C14
1nF
C13
1nF
100nF
100nF
C19
100nF
C25
Figure 7: Application circuit
DocID027029 Rev 2
TDA7492PE CLASS-D AMPLIFIER
+
J5
J9
J12
C10
R20
J6
C15
2.2uF
16V
R21
47k
R1
C4
1nF
1uF
C2
C3
1nF
C1
1uF
R9
Q1
180K
KTC3875(S)
3
R13
FREQUENC Y SHIF T
J7
IN
IC 2
1 L4931CZ3 3 3
4.7k
R19
J4
C29
2.2uF
3V3
L+, L- Only
INPU T
PS
3 R-
4 R+
1 L-
2 L+
MO NO
J1
INPU T
Schematic diagram
C16
10uF
10V
C17
4.7uF
10V
VCC
330pF
C21
1uF
C31
R5
22R
VCC
C27
330pF
C30
1uF
22R
R6
+
220nF
C22
*220nF
C20
220nF
C18
C23
2200uF
35V
220nF
C24
*220nF
C26
220nF
C28
Optional components or circuitry
MO NO
OU T
MO NO
OU T
VCC
GN D
VCC
8R
R18
220nF
C43
220nF
C42
8R
R17
J2
2
1
8R
R16
220nF
C41
220nF
C40
8R
R15
J13
1
R-
R+
2
J14
1
Load=6 ohm
R-OUTPU T
L-
L-OUTPU T
Load=6 ohm
L+ 2
15/23
Schematic diagram
Schematic diagram
TDA7492PE
Table 13: BTL configuration
16/23
Load
impedance
L4, L3, L2, L1
C26, C20
C28, C24,
C22, C18
R15, R16,
R17, R18
C40, C41,
C42, C43
ȍ
15 μh
1 μF
220 nF
ȍ
220 nF
ȍ
22 μh
680 nF
220 nF
ȍ
220 nF
ȍ
22 μh
470 nF
220 nF
ȍ
220 nF
DocID027029 Rev 2
TDA7492PE
6
Characterization curves
Characterization curves
Unless otherwise stated, measurements were made under the following conditions:
VCC 95, ȍI N+]*Y G%5OSC Nȍ*DLQ G%DQG
Tamb = 25 °C.
Note: Maximum output power must be derated according to case temperature.
Figure 9: Efficiency vs. output power
Figure 8: Output power vs. supply voltage
90
80
70
Efficiency(%)
60
Vs = 20 V
50
Rl = 6 ohm
f = 1 kHz
40
30
20
10
0
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
Pout per chann el (W)
Figure 11: THD vs. output power (100 Hz)
Figure 10: THD vs. output power (f = 1 kHz)
10
10
5
5
2
2
1
1
Vs = 20 V, Rl = 6 , f = 1 kHz
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.00 5
0.002
0.001
10 m
Vs = 20 V, Rl = 6 , f = 100 Hz
0.5
THD (%)
THD (%)
0.5
0.00 2
20 m
50 m
100 m
200 m
500 m
1
2
5
10
20
50
0.00 1
10m
20m
50m
10 0 m
20 0 m
Pout (W)
2
5
10
20
50
Figure 13: Frequency response
10
+2
+1.5
5
+1
2
+0.5
1
Vs = 20 V, Rl = 6 ,
f = 1 kHz, Pout = 1 W
0.5
-0
-0.5
-1
0.2
dBr (A)
THD (%)
1
Pout (W)
Figure 12: THD vs. frequency
0.1
0.05
-1.5
Vs = 20 V, Rl = 6 , Pout = 1 W
-2
-2.5
-3
0.02
-3.5
0.01
-4
0.005
-4.5
-5
0.002
0.001
20
50 0 m
-5.5
50
100
200
500
1k
2k
5k
10k
20k
freq (Hz)
-6
20
50
10 0
20 0
50 0
1k
2k
5k
10k
freq (Hz)
DocID027029 Rev 2
17/23
20k
Characterization curves
TDA7492PE
Figure 14: FFT (0 dB)
+0
+0
-10
-10
-20
-20
-30
-30
Vs = 20 V, Rl = 6 ,
Pout = 1 W, f = 1 kHz
-40
-50
-50
-70
-80
-70
-80
-90
-90
-10 0
-11 0
-11 0
-12 0
-12 0
-13 0
-13 0
-14 0
-14 0
50
10 0
20 0
50 0
1k
2k
5k
10 k
20 k
-15 0
20
50
10 0
20 0
50 0
1k
freq (Hz)
freq (Hz)
Figure 16: PSRR parameter
dBr (A)
V s = 20 V, R l = 6 ,
Vr = 500 m V, C svr = 10 μF
freq (H z)
18/23
-60
-10 0
-15 0
20
Vs = 20 V, Rl = 6 ,
Pout = 1 W, f = 1 kHz
-40
-60
dBr (A)
dBr (A)
Figure 15: FFT (-60 dB)
DocID027029 Rev 2
2k
5k
10 k
20 k
TDA7492PE
7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
PowerSSO36 EPD package information
The TDA7492PE comes in a 36-pin PowerSSO package with exposed pad down (EPD).
Figure 17: "PowerSSO-36 EPD package outline" shows the package outline and Table 14:
"PowerSSO-36 EPD package mechanical data" gives the dimensions.
DocID027029 Rev 2
19/23
Package information
TDA7492PE
Figure 17: PowerSSO-36 EPD package outline
7587131_I
20/23
DocID027029 Rev 2
TDA7492PE
Package information
Table 14: PowerSSO-36 EPD package mechanical data
Dimensions in mm
Dimensions in inches
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
ș
0º
-
8°
0º
-
8°
ș
5°
-
10°
5°
-
10°
ș
0°
-
-
0°
-
-
A
2.15
-
2.45
0.085
-
0.096
A1
0.00
-
0.10
0.00
-
0.004
A2
2.15
-
2.35
0.085
-
0.093
b
0.18
-
0.32
0.007
-
0.013
b1
0.13
0.25
0.30
0.005
0.010
0.012
c
0.23
-
0.32
0.009
-
0.013
c1
0.20
0.20
0.30
0.008
0.008
0.012
D
10.30 BSC
0.406 BSC
D1
6.50
-
7.10
0.256
-
0.280
D2
-
3.65
-
-
0.144
-
D3
-
4.30
-
-
0.169
-
e
0.50 BSC
0.020 BSC
E
10.30 BSC
0.406 BSC
E1
7.50 BSC
0.295 BSC
E2
4.10
-
4.70
0.161
-
0.185
E3
-
2.30
-
-
0.091
-
E4
-
2.90
-
-
0.114
-
G1
-
1.20
-
-
0.047
-
G2
-
1.00
-
-
0.039
-
G3
-
0.80
-
-
0.032
-
h
0.30
-
0.40
0.012
-
0.016
L
0.55
0.70
0.85
0.022
0.028
0.033
L1
1.40 REF
0.055 REF
L2
0.25 BSC
0.010 BSC
N
36
R
0.30
-
-
0.012
-
-
R1
0.20
-
-
0.008
-
-
S
0.25
-
-
0.010
-
-
DocID027029 Rev 2
21/23
Revision history
8
TDA7492PE
Revision history
Table 15: Document revision history
22/23
Date
Revision
Changes
14-Nov-2014
1
Initial release
24-Feb-2017
2
Updated minimum voltage to 7 V throughout datasheet
Updated VOS and Tr, Tf in Table 5: "Electrical specifications"
Updated Section 7.1: "PowerSSO36 EPD package information"
DocID027029 Rev 2
TDA7492PE
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
DocID027029 Rev 2
23/23
工商网监
湘ICP备2023018690号
