TDA7498

TDA7498 Datasheet 100-watt + 100-watt dual BTL class-D audio amplifier Features PowerSSO-36 exposed pad up • 100 W + 100 W output power at THD = 10% with RL = 6 Ω and VCC = 36 V • 80 W + 80 W output power at THD = 10% with RL = 8 Ω and VCC = 34 V • • • Wide-range single-supply operation (14 - 39 V) High efficiency (η = 90%) Four selectable, fixed gain settings of nominally 25.6 dB, 31.6 dB, 35.1 dB and 37.6 dB Differential inputs minimize common-mode noise Standby and mute features Short-circuit protection Thermal overload protection Externally synchronizable • • • • • Description The TDA7498 is a dual BTL class-D audio amplifier with single power supply designed for home systems and active speaker applications. It comes in a 36-pin PowerSSO package with exposed pad up (EPU) to facilitate mounting a separate heatsink. Product status link TDA7498 Product summary Order code TDA7498TR Temperature range -40 to 85 °C Package PowerSSO36 (EPU) Packing Tape and reel DS6437 - Rev 10 - August 2020 For further information contact your local STMicroelectronics sales office. www.st.com TDA7498 Device block diagram 1 Device block diagram Figure 1. Internal block diagram (showing one channel only) shows the block diagram of one of the two identical channels of the TDA7498. Figure 1. Internal block diagram (showing one channel only) DS6437 - Rev 10 page 2/22 TDA7498 Pin description 2 Pin description 2.1 Pinout Figure 2. Pin connections (top view, PCB view) DS6437 - Rev 10 SUB_GND 1 OUTPB 2 VREF OUTPB 3 INNB PGNDB 4 32 INPB PGNDB 5 31 GAIN1 PVCCB 6 30 GAIN0 PVCCB 7 29 SVR OUTNB 8 36 VSS 35 SVCC 34 33 28 DIAG OUTNB 9 27 SGND OUTNA 10 26 VDDS OUTNA 11 25 SYNCLK PVCCA 12 24 ROSC PVCCA 13 23 INNA PGNDA 14 22 INPA PGNDA 15 21 MUTE OUTPA 16 20 STBY OUTPA 17 19 VDDPW PGND 18 EP, exposed pad Conn ect to ground page 3/22 TDA7498 Pin list 2.2 Pin list Table 1. Pin description list Number DS6437 - Rev 10 Name Type Description 1 SUB_GND PWR Connect to the frame 2,3 OUTPB O Positive PWM for right channel 4,5 PGNDB PWR Power stage ground for right channel 6,7 PVCCB PWR Power supply for right channel 8,9 OUTNB O Negative PWM output for right channel 10,11 OUTNA O Negative PWM output for left channel 12,13 PVCCA PWR Power supply for left channel 14,15 PGNDA PWR Power stage ground for left channel 16,17 OUTPA O Positive PWM output for left channel 18 PGND PWR Power stage ground 19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power stage 20 STBY I Standby mode control 21 MUTE I Mute mode control 22 INPA I Positive differential input of left channel 23 INNA I Negative differential input of left channel 24 ROSC O Master oscillator frequency-setting pin 25 SYNCLK I/O Clock in/out for external oscillator 26 VDDS O 3.3-V (nominal) regulator output referred to ground for signal blocks 27 SGND PWR Signal ground 28 DIAG O Open-drain diagnostic output 29 SVR O Supply voltage rejection 30 GAIN0 I Gain setting input 1 31 GAIN1 I Gain setting input 2 32 INPB I Positive differential input of right channel 33 INNB I Negative differential input of right channel 34 VREF O Half VDDS (nominal) referred to ground 35 SVCC PWR Signal power supply 36 VSS O 3.3-V (nominal) regulator output referred to power supply - EP - Exposed pad for heatsink, to be connected to ground page 4/22 TDA7498 Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol VCC DC supply voltage for pins PVCCA, PVCCB, SVCC Value Unit 45 V VI Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN0, GAIN1 -0.3 to 3.6 V Tj Operating junction temperature -40 to 150 °C Storage temperature -40 to 150 °C Tstg 3.2 Parameter Thermal data Table 3. Thermal data Symbol Rth j-case 3.3 Parameter Min. Typ. Max. Unit - 2 3 °C/W Min. Typ. Max. Unit Supply voltage for pins PVCCA, PVCCB, SVCC 14 - 39 V Ambient operating temperature -40 - 85 °C Thermal resistance, junction to case Recommended operating conditions Table 4. Recommended operating conditions Symbol VCC Tamb 3.4 Parameter Electrical specifications Unless otherwise stated, the values in the table below are specified for the conditions: VCC = 36 V, RL = 6 Ω, ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 25.6 dB Tamb = 25 °C. Table 5. Electrical specifications Symbol Iq IqSTBY Conditions Min. Typ. Max. Unit Total quiescent current No LC filter, no load - 40 60 mA Quiescent current in standby - - 1 10 µA Play mode -100 - 100 Mute mode -60 - 60 VOS Output offset voltage IOCP Overcurrent protection threshold RL = 0 Ω 6 7 - A Tj Junction temperature at thermal shutdown - - 150 - °C Ri Input resistance Differential input 48 60 - kΩ Overvoltage protection threshold - 42 43 - V VOVP DS6437 - Rev 10 Parameter mV page 5/22 TDA7498 Electrical specifications Symbol Parameter VUVP Undervoltage protection threshold RdsON Power transistor on-resistance Po Output power Po Output power PD Dissipated power η THD GV ΔGV Conditions Min. Typ. Max. Unit - - - 8 V High side - 0.2 - Low side - 0.2 - THD = 10% - 100 - THD = 1% - 78 - RL = 8 Ω, THD = 10% - 80 - W - 20 - W Po = 100 W + 100 W, THD = 10% Ω W Efficiency Po = 100 W + 100 W - 90 - % Total harmonic distortion Po = 1 W - 0.1 - % GAIN0 = L, GAIN1 = L 24.6 25.6 26.6 GAIN0 = L, GAIN1 = H 30.6 31.6 32.6 GAIN0 = H, GAIN1 = L 34.1 35.1 36.1 GAIN0 = H, GAIN1 = H 36.6 37.6 38.6 Closed-loop gain dB Gain matching - -1 - 1 dB CT Crosstalk f = 1 kHz, Po = 1 W 50 70 - dB eN Total input noise A Curve, GV = 20 dB - 15 - f = 22 Hz to 22 kHz - 25 50 µV SVRR Supply voltage rejection ratio fr = 100 Hz, Vr = 0.5 Vpp, CSVR = 10 µF - 70 - dB Tr, Tf Rise and fall times - - 50 - ns fSW Switching frequency Internal oscillator 290 310 330 kHz fSWR Output switching frequency range With internal oscillator (1) 250 - 400 With external oscillator (2) 250 - 400 VinH Digital input high (H) 2.3 - - VinL Digital input low (L) - - 0.8 2.7 - - - - 0.5 2.5 - - - - 0.8 - 70 - VSTBY VMUTE AMUTE Pin STBY voltage high (H) Pin STBY voltage low (L) Pin MUTE voltage high (H) Pin MUTE voltage low (L) Mute attenuation - - VMUTE = L, VSTBY = H kHz V V V dB 1. fSW = 106 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 kΩ (see Figure 19. Application circuit for 6 Ω or 8 Ω speakers). 2. fSW = fSYNCLK / 2 with the external oscillator. DS6437 - Rev 10 page 6/22 TDA7498 Characterization curves 4 Characterization curves 4.1 Test circuit Figure 3. Test circuit for characterizations shows the test circuit with which the characterization curves, shown in the next sections, were measured. Figure 4. Test board shows the PCB layout. Figure 3. Test circuit for characterizations 1 SUB_GND OUTPA 16 22 INPA OUTPA 17 C3 1nF 23 INNA PGNDA 14 C4 1nF PGNDA 15 27 SGND C1 1uF C2 1uF J1 C5 INPUT 100nF 3 L- 4 L+ 1 R- 2 R+ For J7 Single-Ended Input VDDS 26 VDDS R1 DIAG 28 100k R7 22R DIAG FREQUENCY SHIFT R9 Q1 KTC3875(S) 180K 3 C8 R13 FS 100nF 1 47k 2 R14 100k 25 SYNCLK R3 24 ROSC J5 30 GAIN0 39K VDDS J8 31 GAIN1 C10 C11 FS 32 1uF 3V3 C13 1nF C12 J4 S2 1uF MUTE 1 2 3 IN IC2 1 L4931CZ33 3 2 GND C9 100nF DS6437 - Rev 10 INNB 21 MUTE + C15 2.2uF 20 STBY 16V 33k + C7 2.2uF 16V 6.8k D1 18V 3V3 POWER SUPPLY 33 INPB 120k R2 R8 VCC OUT C29 2.2uF C14 1nF R4 S1 STBY 1 2 3 1uF 680nF 220nF C27 330pF 2 PVCCB 7 PVCCB 6 PGNDB 5 4 OUTNB 9 OUTNB 8 VREF C23+ 50V * J3 1 VCC 2 GND OUTPUT Load = 6 ohm L+ 1 L2 R3 R+ 4 J2 22uH * C18 22R 220nF R17 8R C42 100nF PGNDB 2200uF L1 R5 R16 8R 22uH 3 OUTPB C41 220nF L3 * OUTPB C40 * C24 PVCCA 13 SVCC 100nF 36 VSS 3V3 TDA7498 * 100nF IC1 R15 8R 220nF PVCCA 12 C19 35 220nF C30 J6 For Single-Ended Input 22R OUTNA 11 18 PGND * C28 C25 OUTNA 10 100nF * R6 C26 19 VDDPW C6 L4 22uH C20 C31 680nF 1uF * * 220nF 220nF R18 8R L2 * 34 C43 C22 C21 330pF 220nF 22uH C17 SVR 29 TDA7498 CLASS-D AMPLIFIER 10uF 10V C16 10uF 10V LC FILTER COMPONENTS Load L1,L2,L3,L4 6 ohm 22 uH 680 nF 220 nF 8 ohm 22 uH 470 nF 220 nF C20,C26 C18,C22,C24,C28 page 7/22 TDA7498 Characterization curves Figure 4. Test board 4.2 Characterization curves Unless otherwise stated the measurements were made under the following conditions: VCC = 36 V, f = 1 kHz, GV = 25.6 dB, ROSC = 39 kΩ, COSC = 100 nF, Tamb = 25 °C DS6437 - Rev 10 page 8/22 TDA7498 Characterization curves 4.2.1 For RL = 6 Ω Figure 5. Output power (THD = 10%) vs. supply voltage Figure 6. THD vs. output power 10 5 120 110 2 100 1 THD+N (%) Output powe r (W) 90 80 70 0.5 0.2 f = 1 kHz 60 0.1 50 0.05 40 f = 100 Hz 30 0.02 20 0.01 10 0.005 100m +10 +12 +14 +16 +1 8 +20 +22 +24 +26 +2 8 +30 +32 +34 200m 500m 1 2 5 10 20 50 100 200 Output powe r (W) +36 Su pply volta ge (V) Figure 7. THD vs. frequency (1 W) Figure 8. THD vs. frequency (100 mW) 2 1 1 0.5 0.5 0.2 0.2 THD+N (%) THD+N (%) 2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.01 20 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k Fre qu ency (Hz) Fre qu ency (Hz) Figure 9. Frequency response Figure 10. FFT performance (0 dBFS) +3 +0 -10 +2.5 -20 +2 -30 -40 +1.5 -50 -60 -70 +0.5 FFT (dB) Ampl (dB) +1 +0 -0.5 -80 -90 -100 -110 -120 -1 -130 -1.5 -140 -150 -2 -160 -2.5 -3 -170 -180 10 20 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k Fre qu ency (Hz) Fre qu ency (Hz) Figure 11. FFT performance (-60 dBFS) +0 -10 -20 -30 -40 -50 -60 FFT (dB) -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Fre qu ency (Hz) DS6437 - Rev 10 page 9/22 TDA7498 Characterization curves 4.2.2 For RL = 8 Ω Figure 12. Output power (THD = 10%) vs. supply voltage Figure 13. THD vs. output power 10 5 120 110 2 100 1 90 THD+N % ( ) Output powe r (W) 0.5 80 70 60 0.2 f = 1 kHz 0.1 0.05 50 40 0.02 f = 100 Hz 30 0.01 20 10 0.005 100m +10 +12 +14 +16 +1 8 +20 +22 +24 +26 +2 8 +30 +32 +34 200m 500m 1 2 5 10 20 50 100 200 Output powe r (W) +36 Su pply volta ge (V) Figure 14. THD vs. frequency (1 W) Figure 15. THD vs. frequency (100 mW) 2 1 1 0.5 0.5 0.2 0.2 THD+N (%) THD+N (%) 2 0.1 0.05 0.02 0.01 0.1 0.05 0.02 20 50 100 200 500 1k 2k 5k 10k 0.01 20k 20 50 Fre qu ency (Hz) 100 200 500 1k 2k 5k 10k 20k Fre qu ency (Hz) Figure 17. FFT performance (0 dB) Figure 16. Frequency response +3 +2.5 +2 +1.5 +1 Ampl (dB) +0.5 +0 -0.5 -1 -1.5 -2 -2.5 -3 10 20 50 100 200 500 1k 2k 5k 10k 20k Fr e quency (H z) Figure 18. FFT performance (-60 dB) +0 -10 -20 -30 -40 -50 -60 FFT (dB) -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Fre qu ency (Hz) DS6437 - Rev 10 page 10/22 TDA7498 Application information 5 Application information 5.1 Application circuit Figure 19. Application circuit for 6 Ω or 8 Ω speakers 1 C1 1uF C3 1nF C2 1uF C4 1nF J1 C5 INPUT 100nF 3 L- 4 L+ 1 R- 2 J7 R+ For Single-Ended Input SUB_GND OUTPA 16 22 INPA OUTPA 17 23 INNA PGNDA 14 PGNDA 15 27 SGND VDDS 26 VDDS R1 28 DIAG FREQUENCY SHIFT R9 Q1 KTC3875(S) 180K 3 R13 FS 47k R14 100k 1 100nF 24 39K TDA7498 ROSC 2 J5 30 GAIN0 31 GAIN1 3 OUTPB 2 PVCCB 7 PVCCB 6 For Single-Ended Input 35 SVCC PGNDB C11 FS 1uF 3V3 C13 1nF C12 J4 1uF MUTE 1 2 3 S1 STBY 1 2 3 S2 IN IC2 1 L4931CZ33 3 2 GND C9 100nF + 33k + R8 VCC OUT C29 2.2uF C14 1nF R4 120k R2 32 INPB 33 INNB 21 MUTE * 9 8 VCC 2 GND 22uH * C18 220nF R17 8R C42 C20 C31 680nF 1uF VREF 34 SVR 29 * * R18 8R L2 * C43 220nF 220nF C21 330pF 220nF C22 4 OUTNB 1 J2 22R C7 2.2uF 16V TDA7498 CLASS-D AMPLIFIER 6.8k D1 18V C23+ 50V L1 R5 R16 8R 2200uF 5 OUTNB C41 220nF L3 22uH J3 OUTPUT Load = 6 ohm L+ 1 L2 R3 R+ 4 22uH C17 C15 2.2uF 20 STBY 16V 3V3 POWER SUPPLY 5.2 330pF 100nF PGNDB * C24 C19 C10 C40 220nF 220nF C27 * OUTPB J6 100nF 36 VSS 3V3 680nF IC1 25 SYNCLK R3 VDDS J8 C26 1uF OUTNA 11 18 PGND C8 * C30 OUTNA 10 C6 R15 8R C28 220nF C25 19 VDDPW 100nF * R6 22R 100nF PVCCA 13 DIAG 22uH PVCCA 12 100k R7 22R L4 * 10uF 10V C16 10uF 10V LC FILTER COMPONENTS Load L1,L2,L3,L4 6 ohm 22 uH 680 nF 220 nF 8 ohm 22 uH 470 nF 220 nF C20,C26 C18,C22,C24,C28 Mode selection The three operating modes of the TDA7498 are set by the two inputs, STBY (pin 20) and MUTE (pin 21). • Standby mode: all circuits are turned off, very low current consumption. • Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty cycle. • Play mode: the amplifiers are active. The protection functions of the TDA7498 are enabled by pulling down the voltages of the STBY and MUTE inputs shown in Figure 20. Standby and mute circuits. The input current of the corresponding pins must be limited to 200 µA. Table 6. Mode settings Mode STBY (1) MUTE Standby L X (don’t care) Mute H (1) L Play H H 1. Drive levels defined in Table 5. Electrical specifications DS6437 - Rev 10 page 11/22 TDA7498 Gain setting Figure 20. Standby and mute circuits Standby STBY 3.3 V 0V R2 30 kΩ C7 2.2 µF R4 30 kΩ C15 2.2 µF Mute TDA7498 MUTE 3.3 V 0V Figure 21. Turn on/off sequence for minimizing speaker “pop” 5.3 Gain setting The gain of the TDA7498 is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin31). Internally, the gain is set by changing the feedback resistors of the amplifier. Table 7. Gain settings GAIN0 5.4 Nominal gain, Gv (dB) GAIN1 L L 25.6 L H 31.6 H L 35.6 H H 37.6 Input resistance and capacitance The input impedance is set by an internal resistor Ri = 60 kΩ (typical). An input capacitor (Ci) is required to couple the AC input signal. The equivalent circuit and frequency response of the input components are shown in Figure 22. Input circuit and frequency response. For Ci = 470 nF the high-pass filter cutoff frequency is below 20 Hz: fC = 1 / (2 * π * Ri * Ci) DS6437 - Rev 10 page 12/22 TDA7498 Internal and external clocks Figure 22. Input circuit and frequency response 5.5 Internal and external clocks The clock of the class-D amplifier can be generated internally or can be driven by an external source. If two or more class-D amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. This can be implemented by using one TDA7498 as master clock, while the other devices are in slave mode, that is, externally clocked. The clock interconnect is via pin SYNCLK of each device. As explained below, SYNCLK is an output in master mode and an input in slave mode. 5.5.1 Master mode (internal clock) Using the internal oscillator, the output switching frequency, fSW, is controlled by the resistor, ROSC, connected to pin ROSC: fSW = 106 / [(ROSC * 16 + 182) * 4] kHz where ROSC is in kΩ. In master mode, pin SYNCLK is used as a clock output pin whose frequency is: fSYNCLK = 2 * fSW For master mode to operate correctly then resistor ROSC must be less than 60 kΩ as given below in Table 8. How to set up SYNCLK. 5.5.2 Slave mode (external clock) In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin SYNCLK to be internally configured as an input as given in Table 8. How to set up SYNCLK. The output switching frequency of the slave devices is: fSW = fSYNCLK / 2 Table 8. How to set up SYNCLK DS6437 - Rev 10 Mode ROSC SYNCLK Master ROSC < 60 kΩ Output Slave Floating (not connected) Input page 13/22 TDA7498 Output low-pass filter Figure 23. Master and slave connection ROSC Ma s te r S la ve TDA7498 TDA7498 SYNCLK Output Cosc 100 nF 5.6 SYNCLK ROSC Inpu t Rosc 39 k Ω Output low-pass filter To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The cutoff frequency should be larger than 22 kHz and much lower than the output switching frequency. It is necessary to choose the L and C component values depending on the loudspeaker impedance. Some typical values, which give a cutoff frequency of 27 kHz, are shown in Figure 24. Typical LC filter for an 8 Ω speaker and Figure 25. Typical LC filter for a 6 Ω speaker below. Figure 24. Typical LC filter for an 8 Ω speaker Figure 25. Typical LC filter for a 6 Ω speaker DS6437 - Rev 10 page 14/22 TDA7498 Protection functions 5.7 Protection functions The TDA7498 is fully protected against overvoltages, undervoltages, overcurrents and thermal overloads as explained here. Overvoltage protection (OVP) If the supply voltage exceeds the value for VOVP given in Table 5. Electrical specifications , the overvoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage falls back to within the operating range, the device restarts. Undervoltage protection (UVP) If the supply voltage drops below the value for VUVP given in Table 5. Electrical specifications , the undervoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage falls back to within the operating range, the device restarts. Overcurrent protection (OCP) If the output current exceeds the value for IOCP given in Table 5. Electrical specifications , the overcurrent protection is activated which forces the outputs to the high-impedance state. Periodically, the device attempts to restart. If the overcurrent condition is still present, then the OCP remains active. The restart time, TOC, is determined by the RC components connected to pin STBY. Thermal protection (OTP) If the junction temperature, Tj, reaches 145 °C (nominally), the device goes to mute mode and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction temperature reaches the value for Tj given in Table 5. Electrical specifications , the device shuts down and the output is forced to the high-impedance state. When the device cools sufficiently the device restarts. 5.8 Diagnostic output The output pin DIAG is an open-drain transistor. When any protection is activated, it switches to the highimpedance state. The pin can be connected to a power supply (< 39 V) by a pull-up resistor whose value is limited by the maximum sinking current (200 µA) of the pin. Figure 26. Behavior of pin DIAG for various protection conditions VDD TDA7498 R1 DIAG Protection logic VDD Overcurrent prot ection DS6437 - Rev 10 Restart Restart OV, UV, OT prot ection page 15/22 TDA7498 Package information 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 6.1 PowerSSO-36 EPU package information Figure 27. PowerSSO-36 EPU package outline DS6437 - Rev 10 page 16/22 TDA7498 PowerSSO-36 EPU package information Table 9. PowerSSO-36 EPU package mechanical data Symbol DS6437 - Rev 10 mm inches Min. Typ. Max. Min. Typ. Max. A 2.15 - 2.45 0.085 - 0.096 A2 2.15 - 2.35 0.085 - 0.093 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees L 0.55 - 0.85 0.022 - 0.033 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 6.50 - 7.10 0.193 - 0.280 page 17/22 TDA7498 Revision history Table 10. Document revision history Date Revision 11-Aug-2009 1 27-Aug-2009 2 Changes Initial release. Updated supply voltage range on page 1. Updated package exposed pad dimension Y (Min) in Section 6.1 . Updated first feature on page 1. Updated order code name in Section 23-Oct-2009 3 Updated Table 5. Electrical specifications Updated Section 4.2 Characterization curves Removed tables for standby, mute and gain after Figure 19. Application circuit for 6 Ω or 8 Ω speakers. Removed datasheet preliminary status, updated features list and updated Section DS6437 - Rev 10 30-Jun-2010 4 Added Table 4. Recommended operating conditions with updated minimum supply voltage. 27-Jan-2011 5 Updated applications circuit in Figure 19. Application circuit for 6 Ω or 8 Ω speakers. 11-Feb-2011 6 Updated test circuit for characterizations in Section 4.1 . 29-Mar-2011 7 Updated IOCP in Table 5. Electrical specifications . 12-Sep-2011 8 Updated OUTNA in Table 1. Pin description list 09-Sep-2015 9 Updated VCC in Table 2. Absolute maximum ratings and dimension L in Section 6.1 28-Aug-2020 10 Removed order code for tube version. page 18/22 TDA7498 Contents Contents 1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3 4 5 6 2.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Characterization curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2.1 For RL = 6 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2.2 For RL = 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.5 Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5.1 Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5.2 Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.6 Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.7 Protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.8 Diagnostic output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 6.1 PowerSSO-36 EPU package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 DS6437 - Rev 10 page 19/22 TDA7498 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Pin description list . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions. . . . . . . . Electrical specifications . . . . . . . . . . . . . . . . Mode settings . . . . . . . . . . . . . . . . . . . . . . . Gain settings . . . . . . . . . . . . . . . . . . . . . . . . How to set up SYNCLK. . . . . . . . . . . . . . . . . PowerSSO-36 EPU package mechanical data . Document revision history . . . . . . . . . . . . . . . DS6437 - Rev 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . 5 . 5 . 5 . 5 11 12 13 17 18 page 20/22 TDA7498 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. DS6437 - Rev 10 Internal block diagram (showing one channel only) . . . Pin connections (top view, PCB view) . . . . . . . . . . . Test circuit for characterizations . . . . . . . . . . . . . . . . Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output power (THD = 10%) vs. supply voltage . . . . . . THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . THD vs. frequency (1 W) . . . . . . . . . . . . . . . . . . . . . THD vs. frequency (100 mW) . . . . . . . . . . . . . . . . . . Frequency response . . . . . . . . . . . . . . . . . . . . . . . . FFT performance (0 dBFS) . . . . . . . . . . . . . . . . . . . FFT performance (-60 dBFS) . . . . . . . . . . . . . . . . . . Output power (THD = 10%) vs. supply voltage . . . . . . THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . THD vs. frequency (1 W) . . . . . . . . . . . . . . . . . . . . . THD vs. frequency (100 mW) . . . . . . . . . . . . . . . . . . Frequency response . . . . . . . . . . . . . . . . . . . . . . . . FFT performance (0 dB) . . . . . . . . . . . . . . . . . . . . . FFT performance (-60 dB) . . . . . . . . . . . . . . . . . . . . Application circuit for 6 Ω or 8 Ω speakers . . . . . . . . . Standby and mute circuits . . . . . . . . . . . . . . . . . . . . Turn on/off sequence for minimizing speaker “pop” . . . Input circuit and frequency response . . . . . . . . . . . . . Master and slave connection . . . . . . . . . . . . . . . . . . Typical LC filter for an 8 Ω speaker . . . . . . . . . . . . . . Typical LC filter for a 6 Ω speaker . . . . . . . . . . . . . . . Behavior of pin DIAG for various protection conditions . PowerSSO-36 EPU package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 7 . 8 . 9 . 9 . 9 . 9 . 9 . 9 . 9 10 10 10 10 10 10 10 11 12 12 13 14 14 14 15 16 page 21/22 TDA7498 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS6437 - Rev 10 page 22/22