TDA7498E

TDA7498E 160-watt + 160-watt dual BTL class-D audio amplifier Datasheet - production data      Differential inputs minimize common-mode noise Standby and mute features Smart protection Thermal overload protection Small offset less than 20 mV Description The TDA7498E is a dual BTL class-D audio amplifier with a single power supply designed for home systems and active speaker applications. PowerSSO-36 exposed pad up Features       160-W + 160-W output power at THD = 10% with RL = 4 Ω and VCC = 36 V 1 x 220 W output power mono parallel BTL at THD = 10% with RL = 3 Ω and VCC = 36 V Wide-range single-supply operation (14 - 36 V) High efficiency (η = 85%) Parallel BTL function using the MODE pin Four selectable, fixed gain settings of nominally 23.8 dB, 29.8 dB, 33.3 dB and 35.8 dB June 2015 It comes in a 36-pin PowerSSO package with exposed pad up (EPU) to facilitate mounting a separate heatsink. Table 1: Device summary Order code Package Packaging TDA7498E 0 to 70 °C PowerSSO36 (EPU) Tube TDA7498ETR 0 to 70 °C PowerSSO36 (EPU) Tape and reel DocID022595 Rev 2 This is information on a product in full production. Operating temp. range 1/18 www.st.com Contents TDA7498E Contents 1 Device block diagram...................................................................... 5 2 Pin description ................................................................................ 6 3 4 5 6 2.1 Pinout ................................................................................................ 6 2.2 Pin list ............................................................................................... 7 Electrical specifications .................................................................. 8 3.1 Absolute maximum ratings ................................................................ 8 3.2 Thermal data ..................................................................................... 8 3.3 Recommended operating conditions ................................................. 8 3.4 Electrical specifications ..................................................................... 8 3.5 Test circuit ....................................................................................... 10 Characterization curves ................................................................ 11 4.1 For RL = 4 Ω, stereo configuration ................................................... 11 4.2 For RL = 3 Ω, mono BTL configuration ............................................ 12 Application information ................................................................ 13 5.1 Stereo and mono BTL operation selection using the MODE pin ..... 13 5.2 Gain setting ..................................................................................... 13 5.3 Smart protection .............................................................................. 13 Package information ..................................................................... 14 6.1 7 2/18 PowerSSO-36 EPU package information ........................................ 14 Revision history ............................................................................ 17 DocID022595 Rev 2 TDA7498E List of tables List of tables Table 1: Device summary ........................................................................................................................... 1 Table 2: Pin description list ......................................................................................................................... 7 Table 3: Absolute maximum ratings ........................................................................................................... 8 Table 4: Thermal data ................................................................................................................................. 8 Table 5: Recommended operating conditions ............................................................................................ 8 Table 6: Electrical specifications ................................................................................................................. 8 Table 7: Gain settings ............................................................................................................................... 13 Table 8: PowerSSO-36 EPU package mechanical data .......................................................................... 16 Table 9: Document revision history .......................................................................................................... 17 DocID022595 Rev 2 3/18 List of figures TDA7498E List of figures Figure 1: Internal block diagram (showing one channel only) .................................................................... 5 Figure 2: Pin connections (top view, PCB view) ......................................................................................... 6 Figure 3: Test circuit stereo application and mono BTL mode ................................................................. 10 Figure 4: Output power vs. supply voltage ............................................................................................... 11 Figure 5: THD vs. output power ................................................................................................................ 11 Figure 6: THD vs. frequency ..................................................................................................................... 11 Figure 7: FFT performance ....................................................................................................................... 11 Figure 8: Crosstalk vs. frequency ............................................................................................................. 11 Figure 9: Output power vs. supply voltage ............................................................................................... 12 Figure 10: THD vs. output power .............................................................................................................. 12 Figure 11: THD vs. frequency ................................................................................................................... 12 Figure 12: PowerSSO-36 EPU package outline ....................................................................................... 15 4/18 DocID022595 Rev 2 TDA7498E 1 Device block diagram Device block diagram The figure below shows the block diagram of one of the two identical channels of the TDA7498E. Figure 1: Internal block diagram (showing one channel only) DocID022595 Rev 2 5/18 Pin description TDA7498E 2 Pin description 2.1 Pinout Figure 2: Pin connections (top view, PCB view) SUB_GND 1 SVCC OUTPB 2 34 VREF OUTPB 3 33 INNB PGNDB 4 32 PGNDB 5 31 MODE PVCCB 6 30 GAIN PVCCB 7 29 OUTNB 8 28 DIAG OUTNB 9 27 SGND OUTNA 10 26 VDDS OUTNA 11 25 SYNCLK PVCCA 12 24 ROSC PVCCA 13 23 INNA PGNDA 14 PGNDA 15 OUTPA 16 OUTPA 17 PGND 18 36 VSS 35 INPB SVR 22 INPA 21 MUTE EP, exposedpad Connect to ground 20 STBY 19 VDDPW 6/18 DocID022595 Rev 2 TDA7498E 2.3 Pin description Pin list Table 2: Pin description list Number Name Type Description 1 SUB_GND PWR Connect to the frame 2,3 OUTPB O Positive PWM for right channel 4,5 PGNDB PWR Power stage ground for right channel 6,7 PVCCB PWR Power supply for right channel 8,9 OUTNB O Negative PWM output for right channel 10,11 OUTNA O Negative PWM output for left channel 12,13 PVCCA PWR Power supply for left channel 14,15 PGNDA PWR Power stage ground for left channel 16,17 OUTPA O Positive PWM output for left channel 18 PGND PWR Power stage ground 19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power stage 20 STBY I Standby mode control 21 MUTE I Mute mode control 22 INPA I Positive differential input of left channel 23 INNA I Negative differential input of left channel 24 ROSC O Master oscillator frequency-setting pin 25 SYNCLK I/O Clock in/out for external oscillator 26 VDDS O 3.3-V (nominal) regulator output referred to ground for signal blocks 27 SGND PWR Signal ground 28 DIAG O Open-drain diagnostic output 29 SVR O Supply voltage rejection 30 GAIN I Gain setting input 31 MODE I Enables stereo or mono BTL mode of operation 32 INPB I Positive differential input of right channel 33 INNB I Negative differential input of right channel 34 VREF O Half VDDS (nominal) referred to ground 35 SVCC PWR Signal power supply 36 VSS O 3.3-V (nominal) regulator output referred to power supply - EP - Exposed pad for heatsink, to be connected to ground DocID022595 Rev 2 7/18 Electrical specifications TDA7498E 3 Electrical specifications 3.1 Absolute maximum ratings Table 3: Absolute maximum ratings Symbol 3.2 Parameter Value Unit VCC DC supply voltage for pins PVCCA, PVCCB, SVCC 45 V VI Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN, MODE -0.3 to 4.0 V Tj Operating junction temperature 0 to 150 °C Top Operating ambient temperature 0 to 70 °C Tstg Storage temperature -40 to 150 °C Thermal data Table 4: Thermal data Symbol Rth j-case 3.3 Parameter Thermal resistance, junction to case Min Typ - 3.0 Max Unit °C/W Recommended operating conditions Table 5: Recommended operating conditions Symbol 3.4 Parameter Min Typ Max Unit VCC Supply voltage for pins PVCCA, PVCCB, SVCC 14 - 39 V Tamb Ambient operating temperature 0 - 70 °C Electrical specifications Unless otherwise stated, the values in the table below are specified for the conditions: VCC = 36 V, RL = 4 Ω, ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 23.6 dB Tamb = 25 °C. Table 6: Electrical specifications Symbol 8/18 Parameter Condition Min Typ Max Unit Iq Total quiescent current No LC filter, no load - 60 mA IqSTBY Quiescent current in standby - - 1 µA VOS Output offset voltage Vi = 0, Av = 23.6 dB, no load -20 - 20 mV IOCP Overcurrent protection threshold RL = 0 Ω 10 11 14 A Tj Junction temperature at thermal shutdown - 140 150 160 °C Ri Input resistance Differential input 69 - kΩ DocID022595 Rev 2 TDA7498E Electrical specifications Symbol Parameter Condition VUVP Undervoltage protection threshold RdsON Power transistor on-resistance Po Output power Po Parallel BTL (mono) output power, RL = 3 ohm, Vcc = 36 V η Efficiency THD Total harmonic distortion GV Closed-loop gain Min Typ Max - - - 8 High side - 0.15 - Low side - 0.15 - THD = 10% - 160 - THD = 1% - 125 - THD = 10% - 220 - THD = 1% - 170 - - 85 - % - 0.05 - % Po = 1 W GAIN < 0.25*VDD 23.8 0.25*VDD < GAIN < 0.5*VDD 29.8 0.5*VDD < GAIN < 0.75*VDD 33.3 GAIN > 0.75*VDD 35.8 Unit V Ω W W dB ΔGV Gain matching - -1 - 1 dB CT Crosstalk f = 1 kHz, Po = 1 W 50 60 - dB Vn Total output noise Inputs shorted and to ground, A Curve 231 Inputs shorted and to ground, f = 20 Hz to 20 kHz 400 µV SVRR Supply voltage rejection ratio fr = 100 Hz, Vr = 0.5 Vpp, CSVR = 10 µF - 55 - dB Tr, Tf Rise and fall times - - 35 - ns fSW Switching frequency Internal oscillator 240 310 400 kHz fSWR Output switching frequency range With internal oscillator by (1) changing ROSC 240 - VinH Digital input high (H) 2.0 - - VinL Digital input low (L) - - 0.8 Functio n mode Standby & mute & play AMUTE Mute attenuation STBY < 0.5 V; MUTE = X Standby STBY > 2.5 V; MUTE < L Mute STBY > 2.5 V; MUTE > H Play VMUTE < L, VSTBY = H - 75 kHz - V dB Notes: (1) 6 fSW = 10 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 kΩ (see Figure 3: "Test circuit stereo application and mono BTL mode"). DocID022595 Rev 2 9/18 Electrical specifications 3.5 TDA7498E Test circuit Figure 3: Test circuit stereo application and mono BTL mode D2 1 C1 C2 1uF J1 C5 INPUT 100nF 4L+ J7 1R- For Single-Ended Input 23 INNA C4 1nF 27 SGND VDDS R9 Q1 180K KTC3875(S) 3 R13 MONO INPUT L+, L- Only 1 47k R14 100k PS 2 28 DIAG DIAG 24 ROSC J8 For Single-Ended Input and MONO Config J3 MONO Config VCC TDA7498E PS C13 1nF C12 J4 S2 1uF MUTE 1 2 3 S1 STBY 1 2 3 33k IN IC2 1 L4931CZ33 3 C29 2 GND C9 2.2uF 100nF R8 VCC OUT 6.8k D1 18V 3V3 POWER SUPPLY 10/18 C14 1nF R4 R19 120k 33k R2 OUTPB 3 OUTPB 2 PVCCB 7 PVCCB 6 + C15 2.2uF 16V + C7 2.2uF 16V D6 220nF C32 + 2200uF 50V L1 C23 + 2200uF 50V R5 22R GND J2 C18 220nF WL- C31 36 VSS VCC 2 R17 8R C42 100nF C10 1 L1S D7 30 GAIN 1uF PGNDB 5 C21 PGNDB 4 330pF OUTNB 9 OUTNB 8 220nF 33 INNB R-OUTPUT Load=4 ohm R+ C20 WRMONO OUT VCC 32 INPB 1uF L3 D5 C19 100nF J13 C41 C24 8R OUTNA 11 35 SVCC VDDS 2 L- R16 J5 C11 3V3 1uF MONO OUT 31 MODE J6 J10 R12 100k WR+ LOUTPUT Load=4 ohm L+ 1 L3S IC1 100k C26 D4 VCC 25 SYNCLK J12 C40 220nF 220nF 19 VDDPW 18 PGND J11 220nF C27 330pF OUTNA 10 R3 39K 8R C28 PVCCA 13 SYNC C8 100nF R15 L4S C30 1uF PVCCA 12 47k 100nF R11 100k 22R C25 J9 VDDS PGNDA 15 100nF VDDS R10 R6 L4 WL+ C6 FREQUENCY SHIFT D3 PGNDA 14 26 VDDS R1 R7 22R 2R+ OUTPA 17 C3 1nF VCC OUTPA 16 22 INPA 1uF 3L- SUB_GND D8 L2 D9 L2S 2 1 1uF RJ14 C43 C22 220nF 220nF R18 8R VREF 34 C17 10uF 10V 21 MUTE 20 STBY GAIN SETTING SVR 29 C16 10uF 10V Optional components or circuitry MODE SETTING TDA7498E (PSSO36) CLASS-D AMPLIFIER DocID022595 Rev 2 MODE JUMPER STEREO J5 MONO J6,J3,J8 GAIN JUMPER 23.6dB J9 29.6dB J10 33.1dB J11 35.6dB J12 TDA7498E 4 Characterization curves Characterization curves Unless otherwise stated the measurements were made under the following conditions: VCC = 36 V, f = 1 kHz, GV = 23.6 dB, ROSC = 39 kΩ, COSC = 100 nF, Tamb = 25 °C 4.1 For RL = 4 Ω, stereo configuration Figure 4: Output power vs. supply voltage Figure 5: THD vs. output power Figure 6: THD vs. frequency Figure 7: FFT performance Figure 8: Crosstalk vs. frequency DocID022595 Rev 2 11/18 Characterization curves 4.3 TDA7498E For RL = 3 Ω, mono BTL configuration Figure 9: Output power vs. supply voltage Figure 11: THD vs. frequency 12/18 DocID022595 Rev 2 Figure 10: THD vs. output power TDA7498E Application information 5 Application information 5.1 Stereo and mono BTL operation selection using the MODE pin The TDA7498E can be used in stereo applications or mono BTL applications. Connecting the MODE pin to the VDDS pin configures the device in mono BTL. The output of the two channels can be paralleled. When the MODE pin is connected to ground or floating (pulled down internally) the device works as a stereo amplifier. 5.2 Gain setting The gain of the TDA7498E is set by GAIN (pin 30). Table 7: Gain settings GAIN 5.3 Total gain Application recommendation VGAIN < 0.25*VDDS 23.6 dB GAIN pin connected to SGND 0.25*VDDS < VGAIN < 0.5*VDDS 29.6 dB Rc10 = Rc11 = Rc12 = 100 K max 0.5*VDDS < VGAIN < 0.75*VDDS 33.1 dB Rc10 = Rc11 = Rc12 = 100 K max VGAIN > 0.75VDDS 35.6 dB GAIN pin connected to VDDS Smart protection The TDA7498E embeds an overcurrent protection circuitry to protect the device from unwanted current peaks. If the overcurrent protection threshold (Table 6: "Electrical specifications ") is exceeded, the power stage will be shut down immediately. The device will recover automatically once the fault is removed. DocID022595 Rev 2 13/18 Package information 6 TDA7498E Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 6.1 PowerSSO-36 EPU package information The TDA7492E comes in a 36-pin PowerSSO package with exposed pad up (EPU). Figure 12: "PowerSSO-36 EPU package outline" shows the package outline and Table 8: "PowerSSO-36 EPU package mechanical data" gives the dimensions. 14/18 DocID022595 Rev 2 TDA7498E Package information Figure 12: PowerSSO-36 EPU package outline 7618147_F DocID022595 Rev 2 15/18 Package information TDA7498E Table 8: PowerSSO-36 EPU package mechanical data Dimensions in mm Dimensions in inches Symbol 16/18 Min. Typ. Max. Min. Typ. Max. A 2.15 - 2.45 0.085 - 0.096 A2 2.15 - 2.35 0.085 - 0.093 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees L 0.55 - 0.85 0.022 - 0.033 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 4.90 - 7.10 0.193 - 0.280 DocID022595 Rev 2 TDA7498E 7 Revision history Revision history Table 9: Document revision history Date Revision Changes 12-Dec-2011 1 Initial release. 16-Jun-2015 2 Updated VCC in Table 3: "Absolute maximum ratings" , updated Section 6.3: "Smart protection", and updated dimension L in Table 8: "PowerSSO-36 EPU package mechanical data". DocID022595 Rev 2 17/18 TDA7498E IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 18/18 DocID022595 Rev 2