TDA7498L

TDA7498L Datasheet 80 watt + 80 watt dual BTL class-D audio amplifier Features PowerSSO-36 exposed pad up • 80 W + 80 W output power at THD = 10% with RL = 6 Ω and VCC = 32 V • 70 W + 70 W output power at THD = 10% with RL = 8 Ω and VCC = 34 V • • • Wide-range single-supply operation (14 - 36 V) High efficiency (η = 90%) Four selectable, fixed gain settings of nominally 25.6 dB, 31.6 dB, 35.1 dB and 37.6 dB Differential inputs minimize common-mode noise Standby and mute features Short-circuit protection Thermal overload protection Externally synchronizable • • • • • Description The TDA7498L is a dual BTL class-D audio amplifier with single power supply designed for home systems and active speaker applications. It comes in a 36-pin PowerSSO package with exposed pad up (EPU) to facilitate mounting a separate heatsink. Product status link TDA7498L Product summary Order code TDA7498LTR Temperature range -40 to 85 °C Package PowerSSO36 (EPU) Packing Tape and reel DS6539 - Rev 6 - June 2020 For further information contact your local STMicroelectronics sales office. www.st.com TDA7498L Device block diagram 1 Device block diagram Figure 1. Internal block diagram (showing one channel only) shows the block diagram of one of the two identical channels of the TDA7498L. Figure 1. Internal block diagram (showing one channel only) DS6539 - Rev 6 page 2/23 TDA7498L Pin description 2 Pin description 2.1 Pinout Figure 2. Pin connections (top view, PCB view) DS6539 - Rev 6 SUB_GND 1 OUTPB 2 VREF OUTPB 3 INNB PGNDB 4 32 INPB PGNDB 5 31 GAIN1 PVCCB 6 30 GAIN0 PVCCB 7 29 SVR OUTNB 8 36 VSS 35 SVCC 34 33 28 DIAG OUTNB 9 27 SGND OUTNA 10 26 VDDS OUTNA 11 25 SYNCLK PVCCA 12 24 ROSC PVCCA 13 23 INNA PGNDA 14 22 INPA PGNDA 15 21 MUTE OUTPA 16 20 STBY OUTPA 17 19 VDDPW PGND 18 EP, exposed pad Conn ect to ground page 3/23 TDA7498L Pin list 2.2 Pin list Table 1. Pin description list Number Name Type SUB_GND PWR 2,3 OUTPB O 4,5 PGNDB PWR Power stage ground for right channel 6,7 PVCCB PWR Power supply for right channel 8,9 OUTNB O Negative PWM output for right channel 10,11 OUTNA O Negative PWM output for left channel 12,13 PVCCA PWR Power supply for left channel 14,15 PGNDA PWR Power stage ground for left channel 16,17 OUTPA O Positive PWM output for left channel 18 PGND PWR 19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power stage 20 STBY I Standby mode control 21 MUTE I Mute mode control 22 INPA I Positive differential input of left channel 23 INNA I Negative differential input of left channel 24 ROSC O Master oscillator frequency-setting pin 25 SYNCLK I/O Clock in/out for external oscillator 26 VDDS O 3.3-V (nominal) regulator output referred to ground for signal blocks 27 SGND PWR 28 DIAG O Open-drain diagnostic output 29 SVR O Supply voltage rejection 30 GAIN0 I Gain setting input 1 31 GAIN1 I Gain setting input 2 32 INPB I Positive differential input of right channel 33 INNB I Negative differential input of right channel 34 VREF O Half VDDS (nominal) referred to ground 35 SVCC PWR 36 VSS O 3.3-V (nominal) regulator output referred to power supply EP - Exposed pad for heatsink, to be connected to ground 1 - DS6539 - Rev 6 Description Connect to the frame Positive PWM for right channel Power stage ground Signal ground Signal power supply decoupling page 4/23 TDA7498L Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol VCC_MAX Parameter DC supply voltage for pins PVCCA, PVCCB, SVCC VL_MAX Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN0, GAIN1 Tj_MAX Operating junction temperature Tstg Storage temperature Value Unit 45 V -0.3 to 3.6 V 0 to 150 °C -40 to 150 °C Note: warning: stresses beyond those listed under “Absolute maximum ratings” make cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended operating condition” are not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. In the real application, the power supply with the nominal value rated in the recommended operating conditions may rise beyond the maximum operating condition for a short time when no or very low current is sunk (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum rating is not exceeded. 3.2 Thermal data Table 3. Thermal data 3.3 Symbol Parameter Min. Typ. Max. Unit Rth j-case Thermal resistance, junction to case - 2 3 °C/W Min. Typ. Max. Unit Supply voltage for pins PVCCA, PVCCB 14 - 36 V Ambient operating temperature -20 - 85 °C Recommended operating conditions Table 4. Recommended operating conditions Symbol VCC Tamb DS6539 - Rev 6 Parameter page 5/23 TDA7498L Electrical characteristics 3.4 Electrical characteristics Unless otherwise stated, the values in the table below are specified for the conditions: VCC = 32 V, RL = 6 Ω, ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 25.6 dB Tamb = 25 °C. Table 5. Electrical characteristics Symbol Iq IqSTBY Parameter Test conditions Min. Typ. Max. Unit Total quiescent current No LC filter, no load - 40 60 mA Quiescent current in standby - - 1 10 µA Play mode -100 - 100 Mute mode -60 - 60 RL = 0 Ω 5.0 6.0 - A - 150 - °C VOS Output offset voltage IOCP Overcurrent protection threshold mV TjS Junction temperature at thermal shutdown - Ri Input resistance Differential input 48 60 - kΩ VOVP Overvoltage protection threshold - 42 43 - V VUVP Undervoltage protection threshold - - - 8 V RdsON Power transistor on-resistance High side - 0.2 - Low side - 0.2 - THD = 10% - 80 - THD = 1% - 65 - Ω Po Output power Po Output power RL = 8 Ω, THD = 10%, VCC = 32 V - 65 - W PD Dissipated power Po = 80 W + 80 W, THD = 10% - 16 - W Efficiency Po = 80 W + 80 W - 90 - % Total harmonic distortion Po = 1 W - 0.1 - % GAIN0 = L, GAIN1 = L 24.6 25.6 26.6 GAIN0 = L, GAIN1 = H 30.6 31.6 32.6 GAIN0 = H, GAIN1 = L 34.1 35.1 36.1 GAIN0 = H, GAIN1 = H 36.6 37.6 38.6 η THD GV ΔGV Closed-loop gain W dB Gain matching - -1 - 1 dB CT Crosstalk f = 1 kHz, Po = 1 W 50 70 - dB eN Total input noise A Curve, GV = 20 dB - 15 - f = 22 Hz to 22 kHz - 25 50 - 70 - dB - 50 - ns 290 310 330 kHz 250 - 400 250 - 400 2.3 - - - - 0.8 fr = 100 Hz, Vr = 0.5 Vpp, SVRR Supply voltage rejection ratio Tr, Tf Rise and fall times - Switching frequency Internal oscillator fSW fSWR Output switching frequency range VinH Digital input high (H) VinL Digital input low (L) DS6539 - Rev 6 CSVR = 10 µF With internal oscillator (1) With external oscillator (2) - µV kHz V page 6/23 TDA7498L Electrical characteristics Symbol VSTBY VMUTE AMUTE Parameter Pin STBY voltage high (H) Pin STBY voltage low (L) Pin MUTE voltage high (H) Pin MUTE voltage low (L) Mute attenuation Test conditions - - Min. Typ. Max. 2.7 - - - - 0.5 2.5 - - - - 0.8 - 70 - VMUTE < 0.8 V Unit V V dB 1. fSW = 106 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 kΩ (see Figure 20. Application circuit). 2. fSW = fSYNCLK / 2 with the external oscillator. DS6539 - Rev 6 page 7/23 TDA7498L Characterizations 4 Characterization curves Figure 20. Application circuit shows the test circuit with which the characterization curves, shown in the next sections, were measured. Figure 3. Test board below shows the PCB layout. 4.1 PCB layout Figure 3. Test board 4.2 Top view Top copp er Bott om view Bottom coppe r Characterization curves Unless otherwise stated the measurements were made under the following conditions: DS6539 - Rev 6 page 8/23 TDA7498L Characterization curves VCC = 32 V, f = 1 kHz, GV = 25.6 dB, ROSC = 39 kΩ, COSC = 100 nF, Tamb = 25 °C 4.2.1 For RL = 6 Ω Figure 5. THD vs. output power (1 kHz) Figure 4. Output power vs. supply voltage 10 5 2 1 0.5 0.2 0.1 % 0.05 0.02 0.01 0.005 0.002 0.001 100m 200m 500m 1 2 5 10 20 50 90 W Figure 7. THD vs. frequency (1 W) Figure 6. THD vs. output power (100 Hz) 10 1 5 0.5 2 1 0.2 0.5 0.2 % 0.1 0.1 % 0.05 0.05 0.02 0.02 0.01 0.005 0.01 0.002 0.001 100m 0.005 200m 500m 1 2 5 W DS6539 - Rev 6 10 20 50 90 20 50 100 200 500 1k 2k 5k 10k 20k Hz page 9/23 TDA7498L Characterization curves Figure 9. Frequency response Figure 8. THD vs. frequency (100 mW) 1 +3 +2.5 0.5 +2 +1.5 +1 0.2 % d B r 0.1 A 0.05 +0.5 +0 -0.5 -1 -1.5 -2 0.02 -2.5 0.01 20 50 100 200 500 1k 2k 5k 10k -3 20 20k 50 100 200 500 Figure 10. FFT performance (0 dBFS) A +0 +0 -10 -10 -20 -20 -30 -30 -40 -40 d B r -70 -80 A 10k 20k 10k 20k -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 50 100 200 500 1k Hz DS6539 - Rev 6 5k -50 -60 -150 20 2k Figure 11. FFT performance (0 dBFS) -50 d B r 1k Hz Hz 2k 5k 10k 20k -150 20 50 100 200 500 1k 2k 5k Hz page 10/23 TDA7498L Characterization curves 4.2.2 For RL = 8 Ω Figure 13. THD vs. output power (1 kHz) Figure 12. Output power vs. supply voltage 10 5 2 1 0.5 0.2 % 0.1 0.05 0.02 0.01 0.005 0.002 0.001 100m 200m 500m 1 2 5 10 20 50 90 W Figure 14. THD vs. output power (100 Hz) Figure 15. THD vs. frequency (1 W) 10 1 5 0.5 2 1 0.2 0.5 0.2 % 0.1 0.1 % 0.05 0.05 0.02 0.02 0.01 0.005 0.01 0.002 0.001 100m 200m 500m 1 2 5 W DS6539 - Rev 6 10 20 50 90 0.005 20 50 100 200 500 1k 2k 5k 10k 20k Hz page 11/23 TDA7498L Characterization curves Figure 16. THD vs. frequency (100 mW) Figure 17. Frequency response +3 1 +2.5 0.5 +2 +1.5 +1 0.2 % d B r 0.1 A 0.05 +0.5 +0 -0.5 -1 -1.5 -2 0.02 -2.5 0.01 20 50 100 200 500 1k 2k 5k 10k -3 20 20k 50 100 200 500 Figure 18. FFT performance (0 dB) 20k 10k 20k -20 -30 -30 -40 -40 -50 -50 -70 d B r -80 A -60 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 -130 -130 -140 -140 50 100 200 500 1k Hz DS6539 - Rev 6 10k -10 -20 -150 20 5k +0 +0 A 2k Figure 19. FFT performance (-60 dB) -10 d B r 1k Hz Hz 2k 5k 10k 20k -150 20 50 100 200 500 1k 2k 5k Hz page 12/23 TDA7498L Application information 5 Application information 5.1 Application circuit Figure 20. Application circuit 1 C1 1uF 1nF S GND 1nF S GND 100nF S GND LL+ 1 R- 2 R+ 27 R1 28 DIAG J 7 S ingle -Ende d 22R Q1 R3 2 39K 100nF 25 S YNC 1 R13 68k 120K R14 47k S GND S GND S GND ROS C J 5 30 GAIN0 For 35 FS 1uF FS S GND 1 3 1 3 120k S GND + R2 2 33k S GND S GND + S GND R8 IN IC2 L4931CZ33 3 C29 1 2.2uF 2 GND C9 OUT 18V S GND S GND S GND S GND 3V3 P OWER S UP P LY 5.2 VCC 6.8k D1 100nF 33 INNB C14 R4 2 1nF S GND 2200uF C23+ R5 1nF 21 MUTE C15 2.2uF 20 S TBY 16V C7 2.2uF 16V * 4 OUTNB 9 OUTNB 8 R+ 1 VCC 2 GND 2 3 4 22uH * C18 220nF R17 8R C42 C31 C20 1uF 680nF 5 P GNDB LR- R16 J2 22R 100nF C13 C12 S 2 MUTE 1uF S 1 S TBY P VCCB P GNDB INP B 22uH 1 C41 220nF 8R L1 2 7 6 S VCC 32 * L3 3 P VCCB Loa d=6 ohm L+ C24 330pF J3 OUTP UT 220nF C27 C19 100nF 36 VS S C11 S GND TDA7498L OUTP B 8R C40 220nF 50V C10 Input J4 100nF 680nF J6 J 8 S ingle -Ende d 3V3 C26 1uF * 31 GAIN1 S GND * C30 IC1 OUTP B VDDS 220nF OUTNA 11 S YNCLK 24 FS R9 C28 C25 OUTNA 10 18 P GND R15 * R6 22R P VCCA 12 P VCCA 13 19 VDDP W 3 FREQUENCY S HIFT S GND DIAG C6 C8 22uH S GND Input S GND * P GNDA 14 P GNDA 15 100k R7 For 100nF 3V3 INNA VDDS26 VDDS C5 J1 4 23 L4 OUTP A 16 OUTP A 17 C4 1uF 3 INP A C3 C2 INP UT S UB_GND 22 VREF 34 S VR 29 * * 220nF R18 C17 S GND 22uH 10uF 10V C16 S GND TDA7498L CLAS S -D AMP LIFIER 8R L2 * C43 C22 220nF C21 330pF 220nF 10uF 10V LC FILTER COMP ONENT Loa d L1,L2,L3,L4 C20,C26 C18,C22,C24,C28 6 ohm 22 uH 680 nF 220 nF 8 ohm 22 uH 470 nF 220 nF Mode selection The three operating modes of the TDA7498L are set by the two inputs, STBY (pin 20) and MUTE (pin 21). • Standby mode: all circuits are turned off, very low current consumption. • Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty cycle. • Play mode: the amplifiers are active. The protection functions of the TDA7498L are enabled by pulling down the voltages of the STBY and MUTE inputs shown in Figure 21. Standby and mute circuits. The input current of the corresponding pins must be limited to 200 µA. Table 6. Mode settings Mode STBY MUTE Standby L (1) X (don’t care) Mute H (1) L Play H H 1. Drive levels defined in Table 5. Electrical characteristics DS6539 - Rev 6 page 13/23 TDA7498L Gain settings Figure 21. Standby and mute circuits Standby 3.3 V 0V STBY R2 30 kΩ C7 2.2 µF R4 30 kΩ C15 2.2 µF Mute 3.3 V 0V TDA7498L MUTE Figure 22. Turn on/off sequence for minimizing speaker “pop” 5.3 Gain settings The gain of the TDA7498L is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin31). Internally, the gain is set by changing the feedback resistors of the amplifier. Table 7. Gain settings DS6539 - Rev 6 GAIN0 GAIN1 Nominal gain, Gv (dB) L L 25.6 L H 31.6 H L 35.6 H H 37.6 page 14/23 TDA7498L Input resistance and capacitance 5.4 Input resistance and capacitance The input impedance is set by an internal resistor Ri = 60 kΩ (typical). An input capacitor (Ci) is required to couple the AC input signal. The equivalent circuit and frequency response of the input components are shown in Figure 23. Input circuit and frequency response. For Ci = 470 nF the high-pass filter cutoff frequency is below 20 Hz: fC = 1 / (2 * π * Ri * Ci) Figure 23. Input circuit and frequency response 5.5 Internal and external clocks The clock of the class-D amplifier can be generated internally or can be driven by an external source. If two or more class-D amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. This can be implemented by using one TDA7498L as master clock, while the other devices are in slave mode, that is, externally clocked. The clock interconnect is via pin SYNCLK of each device. As explained below, SYNCLK is an output in master mode and an input in slave mode. 5.5.1 Master mode (internal clock) Using the internal oscillator, the output switching frequency, fSW, is controlled by the resistor, ROSC, connected to pin ROSC: fSW = 106 / [(ROSC * 16 + 182) * 4] kHz where ROSC is in kΩ. In master mode, pin SYNCLK is used as a clock output pin whose frequency is: fSYNCLK = 2 * fSW DS6539 - Rev 6 page 15/23 TDA7498L Output low-pass filter For master mode to operate correctly then resistor ROSC must be less than 60 kΩ as given below in Table 8. How to set up SYNCLK. 5.5.2 Slave mode (external clock) In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin SYNCLK to be internally configured as an input as given in Table 8. How to set up SYNCLK. The output switching frequency of the slave devices is: fSW = fSYNCLK / 2 Table 8. How to set up SYNCLK Mode ROSC SYNCLK Master ROSC < 60 kΩ Output Slave Floating (not connected) Input Figure 24. Master and slave connection Ma s te r S la ve TDA7498L ROSC TDA7498L SYNCLK Output Cosc 100 nF 5.6 SYNCLK ROSC Inpu t Rosc 39 k Ω Output low-pass filter To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The cutoff frequency should be larger than 22 kHz and much lower than the output switching frequency. It is necessary to choose the L and C component values depending on the loudspeaker impedance. Some typical values, which give a cutoff frequency of 27 kHz, are shown in Figure 25. Typical LC filter for an 8 Ω speaker and Figure 26. Typical LC filter for a 6 Ω speaker below. Figure 25. Typical LC filter for an 8 Ω speaker DS6539 - Rev 6 page 16/23 TDA7498L Protection functions Figure 26. Typical LC filter for a 6 Ω speaker 5.7 Protection functions The TDA7498L is fully protected against overvoltages, undervoltages, overcurrents and thermal overloads as explained here. Overvoltage protection (OVP) If the supply voltage exceeds the value for VOVP given in Table 5. Electrical characteristics , the overvoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage falls back to within the operating range, the device restarts. Undervoltage protection (UVP) If the supply voltage drops below the value for VUVP given in Table 5. Electrical characteristics , the undervoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage falls back to within the operating range, the device restarts. Overcurrent protection (OCP) If the output current exceeds the value for IOCP given in Table 5. Electrical characteristics , the overcurrent protection is activated which forces the outputs to the high-impedance state. Periodically, the device attempts to restart. If the overcurrent condition is still present then the OCP remains active. The restart time, TOC, is determined by the RC components connected to pin STBY. Thermal protection (OTP) If the junction temperature, Tj, reaches 145 °C (nominally), the device goes to mute mode and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction temperature reaches the value for Tj given in Table 5. Electrical characteristics , the device shuts down and the output is forced to the high-impedance state. When the device cools sufficiently, the device restarts. 5.8 Diagnostic output The output pin DIAG is an open drain transistor. When any protection is activated it switches to the highimpedance state. The pin can be connected to a power supply (< 36 V) by a pull-up resistor whose value is limited by the maximum sinking current (200 µA) of the pin. DS6539 - Rev 6 page 17/23 TDA7498L Diagnostic output Figure 27. Behavior of pin DIAG for various protection conditions VDD TDA7498L R1 DIAG Protection logic VDD Overcurrent prot ection DS6539 - Rev 6 Restart Restart OV, UV, OT prot ection page 18/23 TDA7498L Package information 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 6.1 PowerSSO-36 EPU package information Figure 28. PowerSSO-36 EPU package outline DS6539 - Rev 6 page 19/23 TDA7498L PowerSSO-36 EPU package information Table 9. PowerSSO-36 EPU package mechanical data Symbol DS6539 - Rev 6 mm inches Min. Typ. Max. Min. Typ. Max. A 2.15 - 2.45 0.085 - 0.096 A2 2.15 - 2.35 0.085 - 0.093 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees L 0.55 - 0.85 0.022 - 0.033 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 6.50 - 7.10 0.193 - 0.280 page 20/23 TDA7498L Revision history Table 10. Document revision history Date Revision 04-Dec-2009 1 Changes Initial release. Removed datasheet preliminary status, updated Section Features list and Table 1. Device summary 02-Jul-2010 2 Updated minimum supply voltage and temperature range in Table 5. Recommended operating conditions Updated typical power output for 8 Ω to 32 V in Table 6. Electrical specifications DS6539 - Rev 6 12-Sep-2011 3 Updated OUTNA in Table 2. Pin description list; minor textual updates 09-Sep-2015 4 Updated VCC_MAX in Table 3. Absolute maximum ratings and dimension L in Table 10. PowerSSO-36 EPU package mechanical data 24-Jan-2019 5 Updated product summary table in cover page 26-Jul-2020 6 Updated Figure 28 and Y min. value in Table 9 page 21/23 TDA7498L Contents Contents 1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3 4 5 6 2.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Characterization curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2.1 For RL = 6 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2.2 For RL = 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5.1 Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5.2 Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.7 Protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.8 Diagnostic output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 6.1 PowerSSO-36 EPU package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 DS6539 - Rev 6 page 22/23 TDA7498L IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS6539 - Rev 6 page 23/23