TDA7502

TDA7502 In-car remote amplifier DSP Features ■ 24-Bit fixed-point dsp core delivering up to 50 MIPS ■ 2 x 1024 x 24 Bit of RAM for X and Y data memory. ■ 3072 x 24 Bit of RAM for program also usable for delay ■ Serial audio interface. ■ Debug port. ■ Control interface for external GPIOs, interrupts, and reset. ■ SPI and I2C for communication between external micro and DSP. Both master and slave operating modes. ) s ( ct u d o r P e LQFP44 (10x 10x 1.4mm) ■ PLL clock oscillator ■ 5V-tolerant 3.3V I/O interface ) (s t c u Description d o r This device is a high-performance, fully programmable DSP, suitable for a wide range of applications and particularly for audio and sound processing. It contains a 24-bit 50 MIPS DSP core, several interfaces for control and data, plus a configurable PLL. P e t e l o s b O t e l o s b O The computational power and the memory configuration make this device particularly suitable for in car equalisation. This device will offer the best trade-off between performance and cost when coupled with the TDA7535, or other devices of the same family. A library of sound processing functions is available for this device; some of these functions are: parametric equaliser, cross over filters, acoustic delay, dynamic compression, vol/bass/treble/fader, active equalisation, Stereo spatial enhancement and more. Order codes Part numbers Package Packing TDA7502 LQFP44 (10x 10x 1.4mm) Tube TDA7502013TR LQFP44 (10x 10x 1.4mm) Tape and Reel November 2006 Rev 11 1/25 www.st.com 1 Contents TDA7502 Contents 1 Block diagram and PIN description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 SAI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ) s ( ct u d o r P e 6.1 24-BIT DSP core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 Data and program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 t e l o 1024 x 24-Bit X-RAM (XRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.2 1024 x 24 Bit Y-RAM (YRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.3 3072 X 24-Bit Program RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.4 512 x 24-Bit Bootstrap ROM (Boot ROM) . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.5 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ) (s Pr 6.3.7 bs 7 t c u od 6.3.6 e t e ol s b O 6.3.1 Serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.8 General purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3.9 PLL clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 O 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/25 TDA7502 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Low voltage TTL interface DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Debug port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Casper IC boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 3/25 List of figures TDA7502 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Maximum DSP clock frequency (Fdsp) versus junction temperature (Tj). . . . . . . . . . . . . . 10 SAI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0 . . . . . . . . . . . . . . . . . . . . . . . . . 11 SAI protocol when RLRS=1; RREL=0; RCKP=1; RDIR=1. . . . . . . . . . . . . . . . . . . . . . . . . 12 SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0. . . . . . . . . . . . . . . . . . . . . . . . . 12 SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0. . . . . . . . . . . . . . . . . . . . . . . . . 12 SPI clocking scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Debug port serial clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Debug port acknowledge timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Debug port data I/O to status timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Debug port read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Debug port DBCK next command after read register timing. . . . . . . . . . . . . . . . . . . . . . . . 15 Definition of timing for the I2C bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Application schematic for TDA7502 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Block diagram of car amplifier audio sub-system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 TQFP44 (10x10) mechanical data & package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . 23 ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 4/25 s b O TDA7502 1 Block diagram and PIN description Block diagram and PIN description Figure 1. Block diagram SDI0 SDI1 SDI2 SDO0 SDO1 SDO2 VDD3 GND3 SCANEN TESTEN VDD4 GND4 LRCLKT XAB SERIAL AUDIO INTERFACE SCKT LRCLKR 1024 x 24 X-RAM XDB VDD5 GND5 SCKR YAB SCL I2C INTERFACE SDA SCK MOSI e t e ol GPIO3 GPIO4 GPIO GPIO5 DBCK/GPIO1 DEBUG INTERFACE DBIN/GPIO2 ) (s t c u DBRQN/GPIO3 DBRQ d o r INT PLL OSCILLATOR VDD2 GND2 XTO MISO MOSI SS SCK SDA SCL GPIO3 42 GND6 GPIO4 43 VDD6 GPIO5 44 41 40 39 38 37 36 35 34 30 VDD5 TESTEN 5 29 SDO2 DBRQN 6 28 SDO1 DBOUT 7 27 SDO0 VDD2 8 26 GND4 GND2 9 25 VDD4 DBCK 10 24 SCKR DBIN 11 23 LRCKR 12 13 14 15 16 17 18 19 20 21 22 SDI2 4 SDI1 GND5 SCANEN SDI0 31 GND3 3 VDD3 LRCKT INT RESET 32 XTI SCKT GND1 XTO 33 2 PVCC VDD1 1 PGND s b O RESET PVCC PGND XTI CLKOUT D99AU1034 Pin connection (Top view) P e t e l o VDD1 GND1 3072 x 24 P/DELAY-RAM 128 x 24 BOOT-ROM ORPHEUS 24bit DSP CORE CLKOUT Figure 2. s b O GND6 o r P PDB MISO VDD6 c u d PAB SS SPI INTERFACE ) s ( t 1024 x 24 Y-RAM YDB D99AU1035 5/25 Block diagram and PIN description Table 1. Pin description N. Name Type Reset status 1 VDD1 P – 3.3V core supply. 2 GND1 G – Core ground. 3 INT I/O – External interrupt line (Input/Output). When this line is asserted low, the DSP may be interrupted. Acts as IRQA line of DSP core. 4 SCANEN I – SCAN enable when active with TESTEN also active, controls theshifting of the internal scan chains. 5 TESTEN I – Test enable when active, puts the chip into test mode and muxes the XTI clock to all flip-flops. When SCANEN is also active, the scan chain shifting 6 DBRQN I – Debug port request Input. A means of entering the Debug mode of operation. 7 DBOUT/GPIO2 I/O I The serial data output for the Debug port. Can also be used as a GPIO. 8 VDD2 I – 3.3V core supply. 9 GND2 I – Core ground. I Debug port Bit Clock/Chip status 1. The serial clock for the Debug Port is provided when an input. When an output, provides information about the chip status. Can also be used as GPIO 10 DBCK/GPIO0 ) s ( ct u d o r P e t e l o s b O I/O I O – Output clock. PGND G – PLL clock ground Input. Ground connection for oscillator circuit. 14 PVCC P – PLL clock power supply. Positive supply for PLL clock oscillator. 15 XTO (1) O High Crystal oscillator output. Crystal oscillator output drive. 16 XTI (1) I – Crystal oscillator input. External clock input or crystal connection. DBIN/GPIO1 12 CLKOUT t e l o 6/25 ) (s t c u 11 d o r P e O I/O Function Debug port Serial Input/Chip status 0. The serial data input for the Debug Port is provided when an input. When an output, provides information about the chip status. Can also be used as GPIO. 13 bs TDA7502 17 RESET I/O I System reset. A logic low level applied to RESET input initializes DSPs. During debug mode if this pin is pulled low in while the DBRQN line is pulled low then the DSP pointed to by the DBSEL pin will be reset. 18 VDD3 P – 3.3V supply. 19 GND3 G – Ground. 20 SDI0 I – SDI0 is a stereo digital audio data input pin channel 0. 21 SDI1 I – SDI1 is a stereo digital audio data input pin channel 1. 22 SDI2 I – SDI2 is a stereo digital audio data input pin channel 2. TDA7502 Block diagram and PIN description Table 1. N. Name Type Reset status 23 LRCKR I/O – Left-right clock for SAI Receiver. Master or slave. 24 SCKR I/O – SAI receive bit clock. Master or slave. 25 VDD4 P – 3.3V supply. 26 GND4 G – Ground. 27 SDO0 O High SDO0 is a stereo digital audio data output pin channel 0. 28 SDO1 O High SDO1 is a stereo digital audio data output pin channel 1. 29 SDO2 O High SDO2 is a stereo digital audio data pin channel 2. 30 VDD5 P – 3.3V supply. 31 GND5 G – Ground. 32 LRCKT I/O – SAI transmit left/right clock. Master or slave. 33 SCKT I/O – SAI transmit bit clock. Master or slave. 34 SCL I/O – Clock line for I2C bus. Schmitt trigger input. 35 SDA I/O – Data line for I2C bus. Schmitt trigger input. 36 SCK I – Bit clock for SPI control interface. 37 SS I – Slave select input pin for SPI control interface. 38 MOSI I/O – Serial data output for SPI type serial port when in SPI master mode and serial data input when in SPI slave mode. 39 MISO I/O ct – Serial data input for SPI style serial port when in SPI master mode and serial data output when in SPI slave mode. VDD6 P – 3.3V supply. GND6 G – Ground. GPIO3 I/O – This pin is dedicated as general I/O. 43 GPIO4 I/O – This pin is dedicated as general I/O. 44 GPIO5 I/O – This pin is dedicated as general I/O. 40 41 e t e l 42 O o s b Pin description (continued) u d o Pr ) (s Function ) s ( ct u d o r P e t e l o s b O 1. XTI and XTO are not 5V tolerant 7/25 Electrical specifications 2 TDA7502 Electrical specifications Table 2. Absolute maximum ratings Symbol Parameter Vdd DC supply voltage Vin Digital input voltage (XTI and XTO only) Value Unit -0.5 to 4.6 V -0.5 to (VDD +0.5) V 6.5 V (1) Vin Digital input voltage Tj Operating junction temperature range -40 to 125 °C Storage temperature -55 to 150 °C Tstg ) s ( ct 1. When the IC is powered. Warning: Table 3. u d o Operation at or beyond these limit may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. r P e t e l o Thermal data Symbol Parameter Rth j-amb (1) Thermal resistance junction to ambient )- 1. In still air. Table 4. u d o Parameter e t e ol bs O Pr Parameter Maximum current Note: 50MHz internal DSP clock Table 6. Pll characteristics Symbol Parameter Lock time Fvco (1) VCO frequency (2) 1. Depending on VCO output frequency. 2. Fdsp = Fvco/2 when PLL is running 8/25 Unit 68 °C/W Min. Typ. Max. Unit 3.15 3.3 3.45 V Min. Typ. Max. Unit 250 mA Max. Unit 3 ms 140 MHz Current consumption Symbol Idd Test condition 3.3V power supply voltage Table 5. Value Recommended DC operating conditions Symbol Vdd s ( t c s b O Test condition @3.3V and Tj =125°C Test condition Min. @3.3V and Tj = 125°C 70 Typ. TDA7502 Table 7. Electrical specifications Oscillator characteristics Symbol Fosc Parameter Max oscillator frequency (XTI) Table 8. Test condition Min. @ 3.3V and Tj = 125°C 8 Typ. Max. Unit 12.5 MHz Max. Unit General interface electrical characteristics Symbol Parameter Test Condition Min. Typ. lil Low level input current without pullup device Vi = 0V (1) 1 μA lih High level input current without pullup device Vi = Vdd (1) 1 μA Ioz Tri-state output leakage without pull up/down device Vo = 0V or Vdd (1) 1 5V tolerant tri-state output leakage without pull up/down device Vo = 0V or Vdd (1) I/O latch-up current V < 0V, V > Vdd IozFT Ilatchup Electrostatic protection Vesd Vo = 5.5V Leakage , 1μA r P e 200 (2) t e l o uc od 1 ) s ( t μA 1 μA 3 μA mA 1500 V 1. The leakage currents are generally very small,