TDA75610SEP-HLX

TDA75610SEP 4 x 45 W power amplifier with full I2C diagnostics, high efficiency and low voltage operation Datasheet - production data Standby/mute pin Linear thermal shutdown with multiple thermal warning ESD protection Very robust against misconnections Improved SVR suppression during battery transients Flexiwatt27 (Vertical exposed pad) Description Features The TDA75610SEP is a new quad bridge car radio amplifier, designed in BCD technology, in order to include a wide range of innovative features in a very compact and flexible device. Multipower BCD technology MOSFET output power stage DMOS power output High efficiency (class SB) High output power capability 4 x 25 W/4 @ 14.4 V, 1 kHz, 10% THD, 4 x 45 W max power 2 driving capability (64 W max power) Full I C bus driving: – Standby – Independent front/rear soft play/mute – Selectable gain 26 dB /16 dB (for low noise line output function) – High efficiency enable/disable – I C bus digital diagnostics (including DC and AC load detection) Flexible fault detection through integrated diagnostic DC offset detection Four independent short circuit protection Clipping detector pin with selectable threshold (2 %/10 %) The TDA75610SEP is equipped with the most complete diagnostics array that communicates the status of each speaker through the I2C bus. The dissipated output power under average listening condition is significantly reduced when compared to the conventional class AB solutions, thanks to the patented 'class SB' efficiency concept. TDA75610SEP has been designed to be very robust against several kinds of misconnections. It is moreover compliant to the most recent OEM specifications for low voltage operation (so called 'start-stop' battery profile during engine stop), helping car manufacturers to reduce the overall emissions and thus contributing to environment protection. The ST BCD in combination with 'class SB' efficiency and 'intelligent power' has been sold in million of units to most known car manufacturers, the TDA75610SEP is the last and most compact member of this power amplifiers family. Table 1. Device summary Order code Package Packing TDA75610SEP-HLX Flexiwatt27 (vertical exposed pad) Tube September 2014 This is information on a product in full production. DocIDXXXXXX Rev 1.3 1/39 www.st.com Contents TDA75610SEP Contents 1 Block diagram and application circuits . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 5 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 Typical electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Diagnostics functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 Turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 Permanent diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 Output DC offset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 AC diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Multiple faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 6 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 7 8 9 2/39 Faults availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Fast muting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Battery transitions management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 Low voltage operation (“start stop”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 Advanced battery management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Application suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1 Inputs impedance matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2 High efficiency introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.3 PC-board hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.4 Mounting instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DocIDXXXXXX Rev 1.3 TDA75610SEP Contents 9.1 I2C programming/reading sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2 Address selection and I2C disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.3 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.3.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.3.2 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.3.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.3.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10 Software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11 Examples of bytes sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DocIDXXXXXX Rev 1.3 3/39 3 List of tables TDA75610SEP List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. 4/39 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin list description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Double fault table for turn on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 IB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 IB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DB4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DocIDXXXXXX Rev 1.3 TDA75610SEP List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection diagram (top of view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Quiescent current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output power vs. supply voltage (4 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output power vs. supply voltage (2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Distortion vs. output power (4 , STD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Distortion vs. output power (4 , HI-EFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Distortion vs. output power (2 , STD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Distortion vs. output power (2 , HI-EFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Distortion vs. output power Vs = 6 V (4 , STD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Distortion vs. frequency (4 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Distortion vs. frequency (2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Crosstalk vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Supply voltage rejection vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power dissipation vs. average output power (audio program simulation, 4 ). . . . . . . . . . 16 Power dissipation vs. average output power (audio program simulation, 2 ). . . . . . . . . . 16 Total power dissipation and efficiency vs. output power (4 , HI-EFF, Sine) . . . . . . . . . . . 16 Total power dissipation and efficiency vs. output power (4 , STD, Sine) . . . . . . . . . . . . . 16 ITU R-ARM frequency response, weighting filter for transient pop. . . . . . . . . . . . . . . . . . . 16 Turn-on diagnostic: working principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SVR and output behavior (Case 1: without turn-on diagnostic) . . . . . . . . . . . . . . . . . . . . . 17 SVR and output pin behavior (Case 2: with turn-on diagnostic) . . . . . . . . . . . . . . . . . . . . . 18 Short circuit detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Load detection thresholds - high gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Load detection threshold - low gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Restart timing without diagnostic enable (permanent) - Each 1 mS time, a sampling of the fault is done . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Restart timing with diagnostic enable (permanent). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Current detection high: load impedance |Z| vs. output peak voltage . . . . . . . . . . . . . . . . . 21 Current detection low: load impedance |Z| vs. output peak voltage . . . . . . . . . . . . . . . . . . 21 Thermal foldback diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Worst case battery cranking curve sample 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Worst case battery cranking curve sample 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Upwards fast battery transitions diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Inputs impedance matching circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 High efficiency - basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Data validity on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Timing diagram on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Acknowledge on the I 2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Flexiwatt27 (vertical exp. pad) mechanical data and package dimensions . . . . . . . . . . . . 37 DocIDXXXXXX Rev 1.3 5/39 5 Block diagram and application circuits 1 TDA75610SEP Block diagram and application circuits Figure 1. Block diagram Figure 2. Application circuit 6/39 DocIDXXXXXX Rev 1.3 TDA75610SEP 2 Pin description Pin description For channel name reference: CH1 = LF, CH2 = LR, CH3 = RF and CH4 = RR. Figure 3. Pin connection diagram (top of view) Table 2. Pin list description Pin # Pin name Function 1 TAB 2 STBY - 3 PWGND2 4 OUT2- 5 CD 6 OUT2+ Channel 2, + output 7 VCC1 Supply voltage pin1 8 OUT1- Channel 1, - output 9 PWGND1 10 OUT1+ Standby pin Channel 2 output power ground Channel 2, - output Clip detector output pin Channel 1 output power ground Channel 1, + output DocIDXXXXXX Rev 1.3 7/39 38 Pin description TDA75610SEP Table 2. Pin list description (continued) 8/39 Pin # Pin name Function 11 SVR SVR pin 12 IN1 Input pin, channel 1 13 IN2 14 SGND Input pin, channel 2 15 IN4 Input pin, channel 4 16 IN3 Input pin, channel 3 17 AC GND 18 OUT3+ 19 PWGND3 20 OUT3- Channel 3, - output 21 VCC2 Supply voltage pin2 22 OUT4+ Channel 4, + output 23 CK 24 OUT4- 25 PWGND4 26 DATA 27 ADSEL Signal ground pin AC ground Channel 3, + output Channel 3 output power ground I2C bus clock/HE selector Channel 4, - output Channel 4 output power ground I2C bus data pin/gain selector Address selector pin/ I2C bus disable (legacy select) DocIDXXXXXX Rev 1.3 TDA75610SEP Electrical specifications 3 Electrical specifications  %FWSPYXIQE\MQYQVEXMRKW Table 3. Absolute maximum ratings Symbol Parameter Value Unit V Operating supply voltage(1) 18 V V DC supply voltage 28 V Peak supply voltage (for tmax = 50 ms) 50 V -0.3 to 0.3 V -0.3 to 6 V V GNDmax V V Ground pins voltage CK and DATA pin voltage V Clip detector voltage -0.3 to Vop V V STBY pin voltage -0.3 to Vop V I P T ,T Output peak current (not repetitive tmax = 100 ms) 8 Output peak current (repetitive f > 10 kHz) 6 Power dissipation T 85 W -55 to 150 °C -40 to 105 °C Storage and junction Tamb = 70°C temperature(2) Operative temperature range 1. For RL = 2 A the output current limit might be reached for VOP > 16 V; thus triggering self-protection. 2. A suitable dissipation system should be used to keep T j inside the specified limits.  8LIVQEPHEXE Table 4. Thermal data Symbol R Parameter Thermal resistance junction-to-case DocIDXXXXXX Rev 1.3 Max. Value Unit 1.3 °C/W 9/39 38 Electrical specifications  TDA75610SEP )PIGXVMGEPGLEVEGXIVMWXMGW Refer to the test circuit, VS = 14.4 V; RL = 4 ; f = 1 kHz; GV = 26 dB; Tamb = 25 °C; unless otherwise specified. ested at Tamb = 25 °C and Thot = 105 °C; functionality guaranteed for Tj = -40 °C to 150 °C. Table 5. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. RL = 4 6 - 18 RL = 2 6 - 16 (1) Unit General characteristics V Supply voltage range I Total quiescent drain current - - 155 250 mA Input impedance - 45 60 70 k IB1(D7) = 1 Signal attenuation -6 dB 7 - 8 IB1(D7) = 0 (default);(2) Signal attenuation -6 dB 5 - 5.8 R V Min. supply mute threshold V V V Offset voltage Mute & play -80 0 80 mV Vdth Dump threshold - 18.5 - 20.5 V I Standby current Vstandby = 0 - 1 5 µA SVR Supply voltage rejection f = 100 Hz to 10 kHz; V = 1 Vpk; R = 600 60 70 - dB T Turn on timing (Mute play transition) D2/D1 (IB1) 0 to 1 - 25 50 ms T Turn off timing (Play mute transition) D2/D1 (IB1) 1 to 0 - 25 50 ms THWARN1 Average junction temperature for TH warning 1 DB1 (D7) = 1 - 160 - THWARN2 Average junction temperature for TH warning 2 DB4 (D7) = 1 - 145 - THWARN3 Average junction temperature for TH warning 3 DB4 (D6) = 1 - 125 - - 45 - W 23 - 27 22 - W W - 44 34 68 - W W W - 5 - W °C Audio performances (3) s THD = 10 %, RL = 4 THD = 1 %, RL = 4 P Output power THD 10 % THD 1 % Max power@ 10/39 DocIDXXXXXX Rev 1.3 L TDA75610SEP Electrical specifications Table 5. Electrical characteristics (continued) Symbol THD Parameter Total harmonic distortion Test condition Min. Typ. Max. Unit P = 1 W to 10 W; STD mode HE MODE; P = 1.5 W HE MODE; P = 8 W - 0.015 0.05 0.1 0.1 0.1 0.5 % % % P = 1-10 W, f = 10 kHz - 0.15 0.5 % G = 16 dB; STD Mode V = 0.1 to 5 VRMS - 0.02 0.05 % C Cross talk f = 1 kHz to 10 kHz, R = 600 50 65 - dB G Voltage gain 1 - 25 26 27 dB G Voltage gain match 1 - -1 - 1 dB G Voltage gain 2 - 15 16 17 dB G Voltage gain match 2 - -1 - 1 dB E Output noise voltage 1 R = 600 - 45 60 µV E Output noise voltage 2 R = 600 ; GV = 16d B 20 Hz to 22 kHz - 20 30 µV BW Power bandwidth - 100 - - KHz Input CMRR VCM = 1 Vpk-pk; Rg = 0 - 70 - dB -7.5 - +7.5 mV -7.5 - +7.5 mV CMRR V During mute ON/OFF output offset voltage During standby ON/OFF output offset voltage 20 Hz to 22 kHz ITU R-ARM weighted (see Figure 20) Clip detector CD Clip det. high leakage current CD off / VCD = 6 V - 0 5 µA CD Clip det sat. voltage CD on; I - - 300 mV CD Clip det THD level D0 (IB1) = 1 5 10 15 % D0 (IB1) = 0 1 2 3 % = 1 mA Control pin characteristics V Standby/mute pin for standby - 0 - 1.2 V V Standby/mute pin for mute - 2.9 - 3.5 V V Standby/mute pin for operating - 4.5 - 18 V I Standby/mute pin current A Standby attenuation A Mute attenuation V = 4.5 V - 1 5 µA V < 1.2 V - 0 5 µA - 90 110 - dB - 80 100 - dB DocIDXXXXXX Rev 1.3 11/39 38 Electrical specifications TDA75610SEP Table 5. Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Turn on diagnostics 1 (Power amplifier mode) Pgnd Short to GND det. (below this limit, the Output is considered in short circuit to GND) - - 1.2 V Pvs Short to Vs det. (above this limit, the output is considered in short circuit to Vs) Vs -1.2 - - V Pnop Normal operation thresholds. (Within these limits, the output is considered without faults). 1.8 - Vs -1.8 V - - 0.5 Power amplifier in standby Lsc Shorted load det. Lop Open load det. 85 - - Lnop Normal load det. 1.5 - 45 - - 1.2 V Vs -1.2 - - V V Turn on diagnostics 2 (Line driver mode) Pgnd Pvs Short to GND det. (below this limit, the output is considered in Power amplifier in standby short circuit to GND) Short to Vs det. (above this limit, the output is considered in short circuit to Vs) Normal operation thresholds. (Within these limits, the output is considered without faults). - 1.8 - Vs -1.8 Lsc Shorted load det. - - - 1.5 Lop Open load det. - 330 - - Lnop Normal load det. - 7 - 180 - - 1.2 V Vs -1.2 - - V 1.8 - Vs -1.8 V Power amplifier mode - - 0.5 Line driver mode - - 1.5 ±1.5 ±2 ±2.5 Pnop Permanent diagnostics 2 (Power amplifier mode or line driver mode) Pgnd Pvs Pnop Short to GND det. (below this limit, the Output is considered in short circuit to GND) Short to Vs det. (above this Power amplifier in mute or play, limit, the output is considered in one or more short circuits short circuit to Vs) protection activated Normal operation thresholds. (Within these limits, the output is considered without faults). L Shorted load det. V Offset detection 12/39 Power amplifier in play, AC input signals = 0 DocIDXXXXXX Rev 1.3 V TDA75610SEP Electrical specifications Table 5. Electrical characteristics (continued) Symbol Parameter I Normal load current detection I Open load current detection I Normal load current detection I Open load current detection Test condition V < (V -5)pk, IB2 (D7) = 0 V < (V -5)pk, IB2 (D7) = 1 Min. Typ. Max. Unit 500 - - mA - - 250 mA 250 - - mA - - 125 mA - - 400 kHz I C bus interface S Clock frequency - V Input low voltage - - - 1.5 V V Input high voltage - 2.3 - - V 1. When VS > 16 V the output current limit is reached (triggering embedded internal protections). 2. In legacy mode only low threshold option is available. 3. Saturated square wave output. DocIDXXXXXX Rev 1.3 13/39 38 Electrical specifications  TDA75610SEP 8]TMGEPIPIGXVMGEPGLEVEGXIVMWXMGWGYVZIW Figure 4. Quiescent current vs. supply voltage Figure 5. (4 Figure 6. (2 Figure 7. Distortion vs. output power (4 , STD) Figure 9. Distortion vs. output power (2 , STD) ) Figure 8. Distortion vs. output power (4 , HI EFF) 14/39 ) DocIDXXXXXX Rev 1.3 TDA75610SEP Electrical specifications Figure 10. Distortion vs. output power (2 , HI EFF) Figure 12. Distortion vs. frequency (4 Figure 14. Crosstalk vs. frequency ) Figure 11. Distortion vs. output power Vs = 6 V (4 , STD) Figure 13. Distortion vs. frequency (2 ) Figure 15. Supply voltage rejection vs. frequency DocIDXXXXXX Rev 1.3 15/39 38 Electrical specifications TDA75610SEP Figure 16. Power dissipation vs. average output Figure 17. Power dissipation vs. average output power (audio program simulation, 2 ) power (audio program simulation, 4 ) Figure 18. Total power dissipation and efficiency vs. output power (4 , HI-EFF, Sine) Figure 19. Total power dissipation and efficiency vs. output power (4 , STD, Sine) Figure 20. ITU R-ARM frequency response, weighting filter for transient pop 16/39 DocIDXXXXXX Rev 1.3 TDA75610SEP Diagnostics functional description 4 Diagnostics functional description  8YVRSRHMEKRSWXMG It is recommended to activate this function at the turn-on (standby out) through an I 2C bus request. Detectable output faults are: SHORT TO GND SHORT TO VS SHORT ACROSS THE SPEAKER OPEN SPEAKER To verify if any of the above misconnections are in place, a subsonic (inaudible) current pulse (Figure 21) is internally generated, sent through the speaker(s) and sunk back.The Turn On diagnostic status is internally stored until a successive diagnostic pulse is requested (after a I2C reading). If the "standby out" and "diag. enable" commands are both given through a single programming step, the pulse takes place first (during the pulse the power stage stays 'off', showing high impedance at the outputs). Afterwards, when the amplifier is biased, the PERMANENT diagnostic takes place. The previous turn-on state is kept until a short appears at the outputs. Figure 21. Turn-on diagnostic: working principle Figure 22 and 23 show SVR and OUTPUT waveforms at the turn-on (standby out) with and without turn-on diagnostic. Figure 22. SVR and output behavior (Case 1: without turn-on diagnostic) DocIDXXXXXX Rev 1.3 17/39 38 Diagnostics functional description TDA75610SEP Figure 23. SVR and output pin behavior (Case 2: with turn-on diagnostic) The information related to the outputs status is read and memorized at the end of the current pulse plateau. The acquisition time is 100 ms (typ.). No audible noise is generated in the process. As for SHORT TO GND / Vs the fault-detection thresholds remain unchanged from 26 dB to 16 dB gain setting. They are as follows: Figure 24. Short circuit detection thresholds Concerning SHORT ACROSS THE SPEAKER / OPEN SPEAKER, the threshold varies from 26 dB to 16 dB gain setting, since different loads are expected (either normal speaker's impedance or high impedance). The values in case of 26 dB gain are as follows: Figure 25. Load detection thresholds - high gain setting If the Line-Driver mode (G v= 16 dB and Line Driver Mode diagnostic = 1) is selected, the same thresholds will change as follows: Figure 26. Load detection threshold - low gain setting 18/39 DocIDXXXXXX Rev 1.3 TDA75610SEP  Diagnostics functional description 4IVQERIRXHMEKRSWXMGW Detectable conventional faults are: – – Short to GND Short to Vs – Short across the speaker The following additional feature is provided: – Output offset detection The TDA75610SEP has 2 operating status: 1. RESTART mode. The diagnostic is not enabled. Each audio channel operates independently of each other. If any of the a.m. faults occurs, only the channel(s) interested is shut down. A check of the output status is made every 1 ms (Figure 27). Restart takes place when the overload is removed. 2. DIAGNOSTIC mode. It is enabled via I C bus and it self activates if an output overload (such as to cause the intervention of the short-circuit protection) occurs to the speakers outputs. Once activated, the diagnostics procedure develops as follows (Figure 28): – – To avoid momentary re-circulation spikes from giving erroneous diagnostics, a check of the output status is made after 1ms: if normal situation (no overloads) is detected, the diagnostic is not performed and the channel returns active. Instead, if an overload is detected during the check after 1 ms, then a diagnostic cycle having a duration of about 100 ms is started. – After a diagnostic cycle, the audio channel interested by the fault is switched to RESTART mode. The relevant data are stored inside the device and can be read by the microprocessor. When one cycle has terminated, the next one is activated by an I C reading. This is to ensure continuous diagnostics throughout the carradio operating time. – To check the status of the device a sampling system is needed. The timing is chosen at microprocessor level (over half a second is recommended). Figure 27. Restart timing without diagnostic enable (permanent) - Each 1 mS time, a sampling of the fault is done Figure 28. Restart timing with diagnostic enable (permanent) DocIDXXXXXX Rev 1.3 19/39 38 Diagnostics functional description  TDA75610SEP 3YXTYX('SJJWIXHIXIGXMSR Any DC output offset exceeding ±2 V are signalled out. This inconvenient might occur as a consequence of initially defective or aged and worn-out input capacitors feeding a DC component to the inputs, so putting the speakers at risk of overheating. This diagnostic has to be performed with low-level output AC signal (or Vin = 0). The test is run with selectable time duration by microprocessor (from a "start" to a "stop" command): – START = Last reading operation or setting IB1 - D5 - (OFFSET enable) to 1 – STOP = Actual reading operation Excess offset is signalled out if it is persistent of all the assigned testing time. This feature is disabled if any overloads leading to activation of the short-circuit protection occurs in the process.  %'HMEKRSWXMG It is targeted at detecting accidental disconnection of tweeters in 2-way speaker and, more in general, presence of capacitive (AC) coupled loads. This diagnostic is based on the notion that the overall speaker's impedance (woofer + parallel tweeter) will tend to increase towards high frequencies if the tweeter gets disconnected, because the remaining speaker (woofer) would be out of its operating range (high impedance). The diagnostic decision is made according to peak output current thresholds, and it is enabled by setting (IB2-D2) = 1. Two different detection levels are available: – High current threshold IB2 (D7) = 0 Iout > 500 mApk = normal status Iout < 250 mApk = open tweeter – Low current threshold IB2 (D7) = 1 Iout > 250 mApk = normal status Iout < 125 mApk = open tweeter To correctly implement this feature, it is necessary to briefly provide a signal tone (with the amplifier in "play") whose frequency and magnitude are such as to determine an output current higher than 500 mApk with IB2(D7) = 0 (higher than 250 mApk with IB2(D7) = 1) in normal conditions and lower than 250 mApk with IB2(D7) = 0 (lower than 125 mApk with IB2(D7)=1) should the parallel tweeter be missing. The test has to last for a minimum number of 3 sine cycles starting from the activation of the AC diagnostic function IB2) up to the I2C reading of the results (measuring period). To confirm presence of tweeter, it is necessary to find at least 3 current pulses over the above threadless over all the measuring period, else an "open tweeter" message will be issued. The frequency / magnitude setting of the test tone depends on the impedance characteristics of each specific speaker being used, with or without the tweeter connected (to be calculated case by case). High-frequency tones (> 10 kHz) or even ultrasonic signals are recommended for their negligible acoustic impact and also to maximize the impedance module's ratio between with tweeter-on and tweeter-off. Figure 29 and 30 shows the load impedance as a function of the peak output voltage and the relevant diagnostic fields. 20/39 DocIDXXXXXX Rev 1.3 TDA75610SEP Diagnostics functional description It is recommended to keep output voltage always below 8 V (high threshold case) or 4 V (low threshold case) to avoid the circuit to saturate (causing wrong detection cases). This feature is disabled if any overloads leading to activation of the short-circuit protection occurs in the process. Figure 29. Current detection high: load impedance |Z| vs. output peak voltage Figure 30. Current detection low: load impedance |Z| vs. output peak voltage DocIDXXXXXX Rev 1.3 21/39 38 Multiple faults 5 TDA75610SEP Multiple faults When more misconnections are simultaneously in place at the audio outputs, it is guaranteed that at least one of them is initially read out. The others are notified after successive cycles of I2C reading and faults removal, provided that the diagnostic is enabled. This is true for both kinds of diagnostic (Turn on and Permanent). The table below shows all the couples of double-fault possible. It should be taken into account that a short circuit with the 4 ohm speaker unconnected is considered as double fault. Table 6. Double fault table for turn on diagnostic S. GND S. Vs S. Across L. Open L. S. GND S. GND S. Vs + S. GND S. GND S. GND S. Vs / S. Vs S. Vs S. Vs S. Across L. / / S. Across L. N.A. Open L. / / / Open L. (*) In Permanent Diagnostic the table is the same, with only a difference concerning Open Load (*), which is not among the recognizable faults. Should an Open Load be present during the device's normal working, it would be detected at a subsequent Turn on Diagnostic cycle (i.e. at the successive Car Radio Turn on).  *EYPXWEZEMPEFMPMX] All the results coming from I2C bus, by read operations, are the consequence of measurements inside a defined period of time. If the fault is stable throughout the whole period, it will be sent out. To guarantee always resident functions, every kind of diagnostic cycles (Turn on, Permanent, Offset) will be reactivate after any I 2C reading operation. So, when the micro reads the I2C, a new cycle will be able to start, but the read data will come from the previous diag. cycle (i.e. The device is in Turn On state, with a short to Gnd, then the short is removed and micro reads I2C. The short to Gnd is still present in bytes, because it is the result of the previous cycle. If another I 2C reading operation occurs, the bytes do not show the short). In general to observe a change in Diagnostic bytes, two I 2C reading operations are necessary. 22/39 DocIDXXXXXX Rev 1.3 TDA75610SEP 6 Thermal protection Thermal protection Thermal protection is implemented through thermal foldback (Figure 31). Thermal foldback begins limiting the audio input to the amplifier stage as the junction temperatures rise above the normal operating range. This effectively limits the output power capability of the device thus reducing the temperature to acceptable levels without totally interrupting the operation of the device. The output power will decrease to the point at which thermal equilibrium is reached. Thermal equilibrium will be reached when the reduction in output power reduces the dissipated power such that the die temperature falls below the thermal foldback threshold. Should the device cool, the audio level will increase until a new thermal equilibrium is reached or the amplifier reaches full power. Thermal foldback will reduce the audio output level in a linear manner. Three thermal warning are available through the I2C bus data. After thermal shut down threshold is reached, the CD could toggle (as shown in Figure 31) or stay low, depending on signal level. Figure 31. Thermal foldback diagram  *EWXQYXMRK The muting time can be shortened to less than 1.5 ms by setting (IB2) D5 = 1. This option can be useful in transient battery situations (i.e. during car engine cranking) to quickly turnoff the amplifier to avoid any audible effects caused by noise/transients being injected by preamp stages. The bit must be set back to “0” shortly after the mute transition. DocIDXXXXXX Rev 1.3 23/39 38 Battery transitions management TDA75610SEP 7 Battery transitions management  0S[ZSPXEKISTIVEXMSRwWXEVXWXSTx The most recent OEM specifications are requiring automatic stop of car engine at traffic light, in order to reduce emissions of polluting substances. The TDA75610SEP, thanks to its innovating design, allows to go on playing sound when battery falls down to 6/7V during such conditions, without producing pop noise. The maximum system power will be reduced accordingly. Supported battery cranking curves are shown below, indicating the shape and durations of allowed battery transitions. Figure 32. Worst case battery cranking curve sample 1 V1 = 12 V; V2 = 6 V; V3 = 7 V; V4 = 8 V t1 = 2 ms; t2 = 50 ms; t3 = 5 ms; t4 = 300 ms; t5 =10 ms; t6 = 1 s; t7 = 2 ms Figure 33. Worst case battery cranking curve sample 2 V1 = 12 V; V2 = 6 V; V3 = 7 V t1 = 2 ms; t2 = 5 ms; t3 = 15 ms; t5 = 1 s; t6 = 50 ms 24/39 DocIDXXXXXX Rev 1.3 TDA75610SEP  Battery transitions management %HZERGIHFEXXIV]QEREKIQIRX In addition to compatibility with low Vbatt, the TDA75610SEP is able to sustain upwards fast battery transitions (like the one showed in Figure 34) without causing unwanted audible effect, thanks to the innovative circuit topology. Figure 34. Upwards fast battery transitions diagram DocIDXXXXXX Rev 1.3 25/39 38 Application suggestion TDA75610SEP 8 Application suggestion  -RTYXWMQTIHERGIQEXGLMRK Figure 35. Inputs impedance matching circuit The above is a simplified input stage where it is visible that the AC-GND impedance (60 k ) is the same as the input one. During battery variations the SVR voltage is moved and V IN and VAC-GND tracks it through the two R-C networks. Any differences of this two time constants can produce a differential input voltage, which can produce a noise. Consequently, any additional passive components at the inputs (other than the input capacitors) such as series resistance or R dividers must be compensated for at AC-GND level by connecting the same equivalent resistance in series to CAC-GND. A good 1:1 matching (ZAC-GND = ZIN) is therefore recommended to minimize pop. This rule applies to both "4-CH operation" and "2-CH operation", as any unused input has be ACgrounded (through the same CIN value). 26/39 DocIDXXXXXX Rev 1.3 TDA75610SEP  Application suggestion ,MKLIJJMGMIRG]MRXVSHYGXMSR Thanks to its operating principle, the TDA75610SEP obtains a substantial reduction of power dissipation from traditional class-AB amplifiers without being affected by the massive radiation effects and complex circuitry normally associated with class-D solutions. The high efficiency operating principle is based on the use of bridge structures which are connected by means of a power switch. In particular, as shown in Figure 1, Ch1 is linked to Ch2, while Ch3 to Ch4. The switch, controlled by a logic circuit which senses the input signals, is closed at low volumes (output power steadily lower than 2.5 W) and the system acts like a "single bridge" with double load. In this case, the total power dissipation is a quarter of a double bridge. Due to its structure, the highest efficiency level can be reached when symmetrical loads are applied on channels sharing the same switch. Figure 36. High efficiency - basic structure When the power demand increases to more than 2.5 W, the system behavior is switched back to a standard double bridge in order to guarantee the maximum output power, while in the 6 V start-stop devices the High Efficiency mode is automatically disabled at low V CC (7.3 V ±0.3 V). No need to re-program it when V CC goes back to normal levels. In the range 2-4 W (@ VCC = 14.4 V, RL = 4 ), with the High Efficiency mode, the dissipated power gets up to 50 % less than the value obtained with the standard mode. 8.3 PC-board hints The IC metal slug should not be electrically connected to a PCB signal ground path (SGND) in order to maximize rejection against any disturbances coming from Vbatt line (SVR). It is recommended either to connect it to a power ground (P-GND) path on PCB or electrically isolate it. In presence of a dedicated ground layer on PCB (no distinction between P-GND and SGND) any slug connection to the PCB ground should require no special care. DocIDXXXXXX Rev 1.3 27/39 38 Application suggestion 8.4 TDA75610SEP Mounting instructions It is recommended to contact the exposed pad package against the heatsink by providing a pressure on the center of the plastic body (i.e. by means of a metal spring, bar, clip, etc….). This method, rather than using side screws, would ensure a good thermal contact even without the use of any thermal substances/pads (additional details are contained in AN260). 28/39 DocIDXXXXXX Rev 1.3 I2C bus TDA75610SEP 9 I2C bus  -'TVSKVEQQMRKVIEHMRKWIUYIRGIW A correct turn on/off sequence with respect to the diagnostic timings and producing no audible noises could be as follows (after battery connection): – TURN-ON: PIN2 > 4.5 V --- 10 ms --- (STAND-BY OUT + DIAG ENABLE) --1 s (min) --- MUTING OUT – TURN-OFF: MUTING IN - wait for 50 ms - HW ST-BY IN (ST-BY pin – Car Radio Installation: PIN2 > 4.5 V --- 10 ms DIAG ENABLE (write) --- 200 ms --I2C read (repeat until All faults disappear). OFFSET TEST: Device in Play (no signal) -- OFFSET ENABLE - 30 ms - I2C reading (repeat I2C reading until high-offset message disappears). –  1.2 V) %HHVIWWWIPIGXMSRERH- 'HMWEFPI When the ADSEL/I2CDIS pin is left open the I2C bus is disabled and the device can be controlled by the STBY/MUTE pin. In this status (no - I2C bus) the CK pin enables the HIGH-EFFICIENCY MODE (0 = STD MODE; 1 = HE MODE) and the DATA pin sets the gain (0 = 26 dB; 1 = 16 dB). When the ADSEL/I2CDIS pin is connected to GND the I2C bus is active with address . To select the other I2C address a resistor must be connected to ADSEL/I2CDIS pin as following: 0 < R < 1 k : I2C bus active with address 11 k < R < 21 k : I2C bus active with address 40 k < R < 70 k : I2C bus active with address R > 120 k : Legacy mode (x: read/write bit sector)  -'FYWMRXIVJEGI Data transmission from microprocessor to the TDA75610SEP and viceversa takes place through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).  (EXEZEPMHMX] As shown by Figure 37, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. DocIDXXXXXX Rev 1.3 29/39 38 I2C bus  TDA75610SEP 7XEVXERHWXSTGSRHMXMSRW As shown by Figure 38 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.  &]XIJSVQEX Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.  %GORS[PIHKI The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 39). The receiver** has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. * Transmitter – – master (µP) when it writes an address to the TDA75610SEP slave (TDA75610SEP) when the µP reads a data byte from TDA75610SEP ** Receiver – – slave (TDA75610SEP) when the µP writes an address to the TDA75610SEP master (µP) when it reads a data byte from TDA75610SEP Figure 37. Data validity on the I2C bus Figure 38. Timing diagram on the I2C bus Figure 39. Acknowledge on the I2C bus 30/39 DocIDXXXXXX Rev 1.3 TDA75610SEP 10 Software specifications Software specifications All the functions of the TDA75610SEP are activated by I 2C interface. The bit 0 of the "ADDRESS BYTE" defines if the next bytes are write instruction (from µP to TDA75610SEP) or read instruction (from TDA75610SEP to µP). 'LMTEHHVIWW D7 1 D0 1 0 1 1 (1) (1) X D8 Hex 1. Address selector bit, please refer to address selection description on Chapter 9.2. X = 0 Write to device X = 1 Read from device If R/W = 0, the µP sends 2 "Instruction Bytes": IB1 and IB2. Table 7. IB1 Bit Instruction decoding bit D7 Supply transition mute threshold high (D7 = 1) Supply transition mute threshold low (D7 = 0) D6 Diagnostic enable (D6 = 1) Diagnostic defeat (D6 = 0) D5 Offset Detection enable (D5 = 1) Offset Detection defeat (D5 = 0) D4 Front Channel (CH1, CH3) Gain = 26 dB (D4 = 0) Gain = 16 dB (D4 = 1) D3 Rear Channel (CH2, CH4) Gain = 26 dB (D3 = 0) Gain = 16 dB (D3 = 1) D2 Mute front channels (D2 = 0) Unmute front channels (D2 = 1) D1 Mute rear channels (D1 = 0) Unmute rear channels (D1 = 1) D0 CD 2% (D0 = 0) CD 10% (D0 = 1) DocIDXXXXXX Rev 1.3 31/39 38 Software specifications TDA75610SEP Table 8. IB2 Bit Instruction decoding bit D7 Current detection threshold High th (D7 = 0) Low th (D7 =1) D6 0 D5 Normal muting time (D5 = 0) Fast muting time (D5 = 1) D4 Stand-by on - Amplifier not working - (D4 = 0) Stand-by off - Amplifier working - (D4 = 1) D3 Power amplifier mode diagnostic (D3 = 0) Line driver mode diagnostic (D3 = 1) D2 Current Detection Diagnostic Enabled (D2 =1) Current Detection Diagnostic Defeat (D2 =0) D1 Right Channel Power amplifier working in standard mode (D1 = 0) Power amplifier working in high efficiency mode (D1 = 1) D0 Left Channel Power amplifier working in standard mode (D0 = 0) Power amplifier working in high efficiency mode (D0 = 1) If R/W = 1, the TDA75610SEP sends 4 "Diagnostics Bytes" to P: DB1, DB2, DB3 and DB4. Table 9. DB1 Bit Instruction decoding bit D7 Thermal warning 1 active (D7 = 1), Tj = 160 °C (Typ) - D6 Diag. cycle not activated or not terminated (D6 = 0) Diag. cycle terminated (D6 = 1) - D5 Channel LF (CH1) Channel LF (CH1) Current detection IB2 (D7) = 0 Current detection IB2 (D7) = 1 Output peak current < 250 mA - Open load (D5 = 1) Output peak current < 125 mA - Open load (D5 = 1) Output peak current > 500 mA - Normal load (D5 = 0) D4 Channel LF (CH1) Turn-on diagnostic (D4 = 0) Permanent diagnostic (D4 = 1) - D3 Channel LF (CH1) Normal load (D3 = 0) Short load (D3 = 1) - D2 Channel LF (CH1) Turn-on diag.: No open load (D2 = 0) Open load detection (D2 = 1) Offset diag.: No output offset (D2 = 0) Output offset detection (D2 = 1) - 32/39 DocIDXXXXXX Rev 1.3 TDA75610SEP Software specifications Table 9. DB1 (continued) Bit Instruction decoding bit D1 Channel LF (CH1) No short to Vcc (D1 = 0) Short to Vcc (D1 = 1) - D0 Channel LF (CH1) No short to GND (D1 = 0) Short to GND (D1 = 1) - Table 10. DB2 Bit Instruction decoding bit D7 Offset detection not activated (D7 = 0) Offset detection activated (D7 = 1) - D6 X - D5 Channel LR (CH2) Channel LR (CH2) Current detection IB2 (D7) = 1 Current detection IB2 (D7) = 0 Output peak current < 250 mA - Open load (D5 = 1) Output peak current < 125 mA - Open load (D5 = 1) D4 Channel LR (CH2) Turn-on diagnostic (D4 = 0) Permanent diagnostic (D4 = 1) - D3 Channel LR (CH2) Normal load (D3 = 0) Short load (D3 = 1) - D2 Channel LR (CH2) Turn-on diag.: No open load (D2 = 0) Open load detection (D2 = 1) Permanent diag.: No output offset (D2 = 0) Output offset detection (D2 = 1) - D1 Channel LR (CH2) No short to Vcc (D1 = 0) Short to Vcc (D1 = 1) - D0 Channel LR (CH2) No short to GND (D1 = 0) Short to GND (D1 = 1) - DocIDXXXXXX Rev 1.3 33/39 38 Software specifications TDA75610SEP Table 11. DB3 Bit Instruction decoding bit D7 Standby status (= IB2 - D4) - D6 Diagnostic status (= IB1 - D6) - D5 Channel RF (CH3) Channel RF (CH3) Current detection IB2 (D7) = 1 Current detection IB2 (D7) = 0 Output peak current < 250 mA - Open load (D5 = 1) Output peak current < 125 mA - Open load (D5 = 1) D4 Channel RF (CH3) Turn-on diagnostic (D4 = 0) Permanent diagnostic (D4 = 1) - D3 Channel RF (CH3) Normal load (D3 = 0) Short load (D3 = 1) - D2 Channel RF (CH3) Turn-on diag.: No open load (D2 = 0) Open load detection (D2 = 1) Permanent diag.: No output offset (D2 = 0) Output offset detection (D2 = 1) - D1 Channel RF (CH3) No short to Vcc (D1 = 0) Short to Vcc (D1 = 1) - D0 Channel RF (CH3) No short to GND (D1 = 0) Short to GND (D1 = 1) - 34/39 DocIDXXXXXX Rev 1.3 TDA75610SEP Software specifications Table 12. DB4 Bit Instruction decoding bit D7 Thermal warning 2 active (D7 = 1), Tj = 145 °C (Typ) - D6 Thermal warning 3 active (D6 = 1) Tj = 125 °C (Typ) - D5 Channel RR (CH4) Channel RR (CH4) Current detection IB2 (D7) = 1 Current detection IB2 (D7) = 0 Output peak current < 250 mA - Open load (D5 = 1) Output peak current > 500 mA - Normal load (D5 = 0) D4 Channel RR (CH4) Turn-on diagnostic (D4 = 0) Permanent diagnostic (D4 = 1) - D3 Channel R (CH4) R Normal load (D3 = 0) Short load (D3 = 1) - D2 Channel RR (CH4) Turn-on diag.: No open load (D2 = 0) Open load detection (D2 = 1) Permanent diag.: No output offset (D2 = 0) Output offset detection (D2 = 1) - D1 Channel RR (CH4) No short to Vcc (D1 = 0) Short to Vcc (D1 = 1) - D0 Channel RR (CH4) No short to GND (D1 = 0) Short to GND (D1 = 1) - DocIDXXXXXX Rev 1.3 35/39 38 Examples of bytes sequence 11 TDA75610SEP Examples of bytes sequence 1 - Turn-On diagnostic - Write operation Start Address byte with D0 = 0 ACK IB1 with D6 = 1 ACK IB2 ACK STOP 2 - Turn-On diagnostic - Read operation Start Address byte with D0 = 1 ACK DB1 ACK DB2 ACK DB3 ACK DB4 ACK STOP The delay from 1 to 2 can be selected by software, starting from 1ms 3a - Turn-On of the power amplifier with 26dB gain, mute on, diagnostic defeat, CD = 2% . Start Address byte with D0 = 0 ACK IB1 ACK X0000000 IB2 ACK STOP XXX1XX11 3b - Turn-Off of the power amplifier Start Address byte with D0 = 0 ACK IB1 ACK X0XXXXXX IB2 ACK STOP XXX0XXXX 4 - Offset detection procedure enable Start Address byte with D0 = 0 ACK IB1 XX1XX11X ACK IB2 ACK STOP XXX1XXXX 5 - Offset detection procedure stop and reading operation (the results are valid only for the offset detection bits (D2 of the bytes DB1, DB2, DB3, DB4) . Start Address byte with D0 = 1 ACK DB1 ACK DB2 ACK DB3 ACK DB4 ACK STOP The purpose of this test is to check if a D.C. offset (2 V typ.) is present on the outputs, produced by input capacitor with anomalous leakage current or humidity between pins. The delay from 4 to 5 can be selected by software, starting from 1ms 36/39 DocIDXXXXXX Rev 1.3 TDA75610SEP 12 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 40. Flexiwatt27 (vertical exp. pad) mechanical data and package dimensions DocIDXXXXXX Rev 1.3 37/39 38 Revision history 13 TDA75610SEP Revision history Table 13. Document revision history 38/39 Date Revision Changes 17-Dec-2013 1 08-Apr-2014 1.1 Added Section 8.4: Mounting instructions on page 28. Updated Figure 40: Flexiwatt27 (vertical exp. pad) mechanical data and package dimensions on page 37. 28-Apr-2014 1.2 Updated Section 9.2: Address selection and I2C disable on page 29. 19-Sep-2014 1.3 Updated Section 9.1: I2C programming/reading sequences on page 29. Initial release. DocIDXXXXXX Rev 1.3 TDA75610SEP IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved DocIDXXXXXX Rev 1.3 39/39 39