TDA7563
MULTIFUNCTION QUAD POWER AMPLIFIER
WITH BUILT-IN DIAGNOSTICS FEATURES
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DMOS POWER OUTPUT
NON-SWITCHING HI-EFFICIENCY
HIGH OUTPUT POWER CAPABILITY 4x28W/
4Ω @ 14.4V, 1KHZ, 10% THD, 4x40W EIAJ
MAX. OUTPUT POWER 4x72W/2Ω
MULTIPOWER BCD TECHNOLOGY
MOSFET OUTPUT POWER STAGE
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FULL I2C BUS DRIVING:
– ST-BY
– INDEPENDENT FRONT/REAR SOFT PLAY/
MUTE
– SELECTABLE GAIN 30dB
– 16dB (FOR LOW NOISE LINE OUTPUT
FUNCTION)
– HIGH EFFICIENCY ENABLE/DISABLE
– I2C BUS DIGITAL DIAGNOSTICS
FULL FAULT PROTECTION
DC OFFSET DETECTION
FOUR INDEPENDENT SHORT CIRCUIT
PROTECTION
CLIPPING DETECTOR PIN WITH
SELECTABLE THRESHOLD (2%/10%)
ST-BY/MUTE PIN
LINEAR THERMAL SHUTDOWN
ESD PROTECTION
FLEXIWATT27
ORDERING NUMBER: TDA7563
DESCRIPTION
The TDA7563 is a new BCD technology Quad
Bridge type of car radio amplifier in Flexiwatt27
package specially intended for car radio applications. Thanks to the DMOS output stage the
TDA7563 has a very low distortion allowing a clear
powerful sound. Among the features, its superior
efficiency performance coming from the internal exclusive structure, makes it the most suitable device
to simplify the thermal management in high power
sets.The dissipated output power under average
listening condition is in fact reduced up to 50%
when compared to the level provided by conventional class AB solutions.This device is equipped
with a full diagnostics array that communicates the
status of each speaker through the I 2C bus.
BLOCK DIAGRAM
CLK
DATA
VCC1
VCC2
ST-BY/MUTE
Thermal
Protection
& Dump
I2CBUS
Mute1 Mute2
IN RF
Reference
CD_OUT
Clip
Detector
F
OUT RF+
16/30dB
IN RR
Short Circuit
Protection &
Diagnostic
OUT RF-
R
OUT RR+
16/30dB
IN LF
OUT RR-
Short Circuit
Protection &
Diagnostic
F
OUT LF+
16/30dB
IN LR
Short Circuit
Protection &
Diagnostic
R
OUT LFOUT LR+
16/30dB
Short Circuit
Protection &
Diagnostic
SVR
AC_GND
RF RR
LF LR
OUT LR-
TAB
S_GND
PW_GND
May 2003
1/20
TDA7563
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Vop
Operating Supply Voltage
18
V
VS
DC Supply Voltage
28
V
Peak Supply Voltage (for t = 50ms)
50
V
CK pin Voltage
6
V
Vpeak
VCK
Parameter
Data Pin Voltage
6
V
IO
Output Peak Current (not repetitive t = 100ms)
8
A
IO
Output Peak Current (repetitive f > 10Hz)
6
A
VDATA
Ptot
Power Dissipation Tcase = 70°C
85
W
-55 to 150
°C
Value
Unit
1
°C/W
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Tstg, Tj
Storage and Junction Temperature
THERMAL DATA
Symbol
Rth j-case
Parameter
Max.
Thermal Resistance Junction to case
PIN CONNECTION (Top view)
27
TAB
26
DATA
25
PW_GND RR
24
OUT RR-
23
CK
22
OUT RR+
21
VCC2
20
OUT RF-
19
PW_GND RF
18
OUT RF+
17
AC GND
16
IN RF
15
IN RR
14
S_GND
13
IN LR
12
IN LF
11
SVR
10
OUT LF+
9
PW_GND LF
8
OUT LF-
7
VCC1
6
OUT LR+
5
CD-OUT
4
OUT LR-
3
PW_GND LR
2
STBY
1
TAB
D00AU1230
2/20
TDA7563
Figure 1. Application Circuit
C7
3300µF
C8
0.1µF
Vcc1
V(4V .. VCC)
2
DATA
26
CLK
23
Vcc2
7
21
18
+
19
20
I2C BUS
22
OUT RF
+
25
C1 0.22µF
IN RF
16
24
OUT RR
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10
C2 0.22µF
IN RR
15
9
8
C3 0.22µF
IN LF
+
12
6
OUT LF
+
3
C4 0.22µF
IN LR
4
13
S-GND
14
17
11
5
1, 27
OUT LR
-
TAB
47K
C5
1µF
V
C6
10µF
D00AU1231A
CD OUT
3/20
TDA7563
ELECTRICAL CHARACTERISTICS
(Refer to the test circuit, VS = 14.4V; RL = 4Ω; f = 1KHz; GV = 30dB; Tamb = 25°C; unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
18
V
170
300
mA
POWER AMPLIFIER
VS
Supply Voltage Range
Id
Total Quiescent Drain Current
PO
Output Power
8
EIAJ (VS = 13.7V)
35
40
W
THD = 10%
THD = 1%
25
28
22
W
W
RL = 2Ω; EIAJ (VS = 13.7V)
RL = 2Ω; THD 10%
RL = 2Ω; THD 1%
RL = 2Ω; MAX POWER
55
40
62
46
35
72
W
W
W
W
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THD
Total Harmonic Distortion
CT
Cross Talk
RIN
Input Impedance
GV1
Voltage Gain 1
∆GV1
GV2
PO = 1W to 10W; STD MODE
HE MODE; PO = 1.5W
HE MODE; PO = 8W
0.03
0.02
0.15
0.1
0.1
0.5
%
%
%
PO = 1-10W, f = 10kHz
0.2
0.5
%
GV = 16dB; STD Mode
VO = 0.1 to 5VRMS
0.02
0.05
%
f = 1KHz to 10KHz, Rg = 600Ω
Voltage Gain Match 1
Voltage Gain Match 2
60
60
100
130
KΩ
29.5
30
30.5
dB
1
dB
16
16.5
dB
1
dB
-1
Voltage Gain 2
∆GV2
50
15.5
-1
dB
EIN1
Output Noise Voltage 1
Rg = 600Ω 20Hz to 22kHz
50
100
mV
EIN2
Output Noise Voltage 2
Rg = 600Ω; GV = 16dB
20Hz to 22kHz
15
30
mV
SVR
Supply Voltage Rejection
f = 100Hz to 10kHz; Vr = 1Vpk;
Rg = 600Ω
50
60
dB
BW
Power Bandwidth
100
ASB
Stand-by Attenuation
90
110
KHz
ISB
Stand-by Current
AM
Mute Attenuation
80
100
VOS
Offset Voltage
-100
0
VAM
Min. Supply Mute Threshold
7
7.5
8
V
TON
Turn ON Delay
D2/D1 (IB1) 0 to 1
5
20
ms
D2/D1 (IB1) 1 to 0
2
Mute & Play
20
µA
dB
100
mV
TOFF
Turn OFF Delay
20
ms
VSBY
St-By/Mute pin for St-By
0
1.5
V
VMU
St-By/Mute pin for Mute
3.5
5
V
VOP
St-By/Mute pin for Operating
IMU
St-By/Mute pin Current
VS
V
VSTBY/MUTE = 8.5V
7
20
40
µA
VSTBY/MUTE < 1.5V
0
10
µA
0
15
CDLK
Clip Det High Leakage Current
CD off
CDSAT
Clip Det Sat. Voltage
CD on; ICD = 1mA
CDTHD
Clip Det THD level
D0 (IB1) = 1
4/20
5
dB
300
5
10
µA
mV
15
%
TDA7563
ELECTRICAL CHARACTERISTICS (continued)
(Refer to the test circuit, VS = 14.4V; RL = 4Ω; f = 1KHz; GV = 30dB; Tamb = 25°C; unless otherwise specified.)
Symbol
Parameter
Test Condition
D0 (IB1) = 0
Min.
Typ.
Max.
Unit
1
2
3
%
1.2
V
TURN ON DIAGNOSTICS 1 (Power Amplifier Mode)
Pgnd
Short to GND det. (below this
limit, the Output is considered in
Short Circuit to GND)
Pvs
Short to Vs det. (above this limit,
the Output isconsidered in Short
Circuit to VS)
Vs -1.2
Pnop
Normal operation
thresholds.(Within these limits,
the Output is considered without
faults).
1.8
Power Amplifier in st-by
V
Vs -1.8
V
0.5
Ω
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Lsc
Shorted Load det.
Lop
Open Load det.
130
Lnop
Normal Load det.
1.5
Ω
70
Ω
1.2
V
TURN ON DIAGNOSTICS 2 (Line Driver Mode)
Pgnd
Short to GND det. (below this
limit, the Output is considered in
Short Circuit to GND)
Pvs
Short to Vs det. (above this limit,
the Output isconsidered in Short
Circuit to VS)
Vs -1.2
Pnop
Normal operation
thresholds.(Within these limits,
the Output is considered without
faults).
1.8
Lsc
Power Amplifier in st-by
V
Shorted Load det.
Lop
Open Load det.
400
Lnop
Normal Load det.
4.5
Vs -1.8
V
1.5
Ω
Ω
200
Ω
1.2
V
PERMANENT DIAGNOSTICS 2 (Power Amplifier Mode or Line Driver Mode)
Pgnd
Short to GND det. (below this
limit, the Output is considered in
Short Circuit to GND)
Pvs
Short to Vs det. (above this limit,
the Output is considered in Short
Circuit to VS)
Vs -1.2
Pnop
Normal operation thresholds.
(Within these limits, the Output is
considered without faults).
1.8
LSC
Shorted Load Det.
VO
Offset Detection
Power Amplifier in Mute or Play,
one or more short circuits
protection activated
V
Pow. Amp. mode
Line Driver mode
Power Amplifier in play,
AC Input signals = 0
±1.5
±2
Vs -1.8
V
0.5
Ω
1.5
Ω
±2.5
V
I2C BUS INTERFACE
SCL
Clock Frequency
400
KHz
VIL
Input Low Voltage
1.5
V
VIH
Input High Voltage
2.3
V
5/20
TDA7563
Figure 2. Quiescent Current vs. Supply Voltage
Figure 5. Distortion vs. Output Power (4Ω, STD)
THD (%)
Id (mA)
10
250
230
STANDARD MODE
Vs = 14.4 V
RL = 4 Ohm
Vin = 0
NO LOADS
210
1
190
170
f = 10 KHz
150
130
0.1
f = 1 KHz
110
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90
70
8
10
12
14
16
18
0.01
0.1
1
10
Vs (V)
Po (W)
Figure 3. Output Power vs. Supply Voltage (4Ω)
Figure 6. Distortion vs. Output Power (4Ω, HI-EFF)
Po (W)
THD (%)
70
10
65
Po-max
HI-EFF MODE
Vs = 14.4 V
RL = 4 Ohm
60
RL = 4 Ohm
f = 1 KHz
55
50
1
THD = 10 %
45
f = 10 KHz
40
0.1
35
30
f = 1 KHz
25
THD = 1 %
20
0.01
15
10
5
8
9
10
11
12
13
Vs (V)
14
15
16
17
18
Figure 4. Output Power vs. Supply Voltage (2Ω)
0.001
0.1
1
10
Po (W)
Figure 7. Distortion vs. Output Power (2Ω, STD)
Po (W)
THD (%)
100
10
90
HI-EFF MODE
Vs = 14.4 V
RL = 2 Ohm
Po-max
80
RL = 2 Ohm
f = 1 KHz
70
1
THD = 10 %
60
f = 10 KHz
50
40
0.1
f = 1 KHz
30
THD = 1 %
20
10
8
6/20
9
10
11
12
Vs (V)
13
14
15
16
0.01
0.1
1
10
Po (W)
TDA7563
Figure 11. Supply Voltage Rejection vs. Freq.
Figure 8. Distortion vs. Frequency (4Ω)
THD (%)
SVR (dB)
10
90
80
STANDARD MODE
Vs = 14.4 V
RL = 4 Ohm
Po = 4 W
1
70
60
50
0.1
STD & HE MODE
Rg = 600 Ohm
Vripple = 1 Vpk
40
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30
0.01
10
100
1000
10000
20
10
100
1000
f (Hz)
10000
f (Hz)
Figure 9. Distortion vs. Frequency (2Ω)
Figure 12. Power Dissipation & Efficiency vs.
Output Power (4Ω, STD, SINE)
n (%)
Ptot (W)
90
THD (%)
10
STANDARD MODE
Vs = 14.4 V
RL = 4 x 4 Ohm
f = 1 KHz SINE
80
1
70
STANDARD MODE
Vs = 14.4 V
RL = 2 Ohm
Po = 4 W
0.01
10
100
1000
10000
f (Hz)
Figure 10. Crosstalk vs. Frequency
60
50
50
Ptot
30
20
20
10
10
0
0
2
4
6
8
0
10 12 14 16 18 20 22 24 26 28 30
Po (W)
n (%)
90
HI-EFF MODE
Vs = 14.4 V
RL = 4 x 4 Ohm
f = 1 KHz SINE
80
80
70
70
90
80
n
60
60
50
70
60
50
Ptot
STANDARD MODE
RL = 4 Ohm
Po = 4 W
Rg = 600 Ohm
30
20
10
40
30
Ptot (W)
CROSSTALK (dB)
40
70
Figure 13. Power Dissipation & Efficiency vs.
Output Power (4W, HI-EFF, SINE)
90
50
80
60
40
0.1
90
n
100
1000
f (Hz)
10000
40
40
30
30
20
20
10
10
0
0.1
0
1
10
Po (W)
7/20
TDA7563
Figure 15. Power Dissipation vs. Average
Ouput Power (Audio Program
Simulation, 2Ω)
Figure 14. Power Dissipation vs. Average
Ouput Power (Audio Program
Simulation, 4Ω)
Ptot (W)
Ptot (W)
90
45
40
35
80
STD MODE
Vs = 14 V
RL = 4 x 4 Ohm
GAUSSIAN NOISE
70
Vs = 14 V
RL = 4 x 2 Ohm
GAUSSIAN NOISE
60
30
CLIP
START
25
20
STD MODE
50
CLIP
START
40
HI-EFF MODE
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15
30
10
20
5
10
HI-EFF MODE
0
0
0
1
2
Po (W)
3
4
5
0
1
2
3
4
5
Po (W)
6
7
8
9
DIAGNOSTICS FUNCTIONAL DESCRIPTION:
a) TURN-ON DIAGNOSTIC
It is activated at the turn-on (stand-by out) under I2Cbus request. Detectable output faults are:
– SHORT TO GND
– SHORT TO Vs
– SHORT ACROSS THE SPEAKER
– OPEN SPEAKER
To verify if any of the above misconnections are in place, a subsonic (inaudible) current pulse (fig. 16) is internally generated, sent through the speaker(s) and sunk back.The Turn On diagnostic status is internally stored
until a successive diagnostic pulse is requested (after a I2C reading).
If the "stand-by out" and "diag. enable" commands are both given through a single programming step, the pulse
takes place first (power stage still in stand-by mode, low, outputs= high impedance).
Afterwards, when the Amplifier is biased, the PERMANENT diagnostic takes place. The previous Turn On state
is kept until a short appears at the outputs.
Figure 16. Turn - On diagnostic: working principle
Vs~5V
Isource
I (mA)
Isource
Isink
CH+
CH-
Isink
~100mS
Measure time
8/20
t (ms)
TDA7563
Fig. 17 and 18 show SVR and OUTPUT waveforms at the turn-on (stand-by out) with and without TURN-ON
DIAGNOSTIC.
Figure 17. SVR and Output behaviour (CASE 1: without turn-on diagnostic)
Vsvr
Out
Permanent diagnostic
acquisition time (100mS Typ)
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t
Diagnostic Enable
(Permanent)
Bias (power amp turn-on)
I2CB DATA
FAULT
event
Read Data
Permanent Diagnostics data (output)
permitted time
Figure 18. SVR and Output pin behaviour (CASE 2: with turn-on diagnostic)
Vsvr
Out
Turn-on diagnostic
acquisition time (100mS Typ)
Permanent diagnostic
acquisition time (100mS Typ)
t
Diagnostic Enable
(Turn-on)
Turn-on Diagnostics data (output)
permitted time
Bias (power amp turn-on)
permitted time
Diagnostic Enable
(Permanent)
Read Data
FAULT
event
Permanent Diagnostics data (output)
permitted time
I2CB DATA
9/20
TDA7563
The information related to the outputs status is read and memorized at the end of the current pulse top. The
acquisition time is 100 ms (typ.). No audible noise is generated in the process. As for SHORT TO GND / Vs the
fault-detection thresholds remain unchanged from 30 dB to 16 dB gain setting. They are as follows:
S.C. to GND
0V
x
1.2V
Normal Operation
1.8V
x
VS-1.8V
S.C. to Vs
VS-1.2V
D01AU1253
VS
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Concerning SHORT ACROSS THE SPEAKER / OPEN SPEAKER, the threshold varies from 30 dB to 16 dB
gain setting, since different loads are expected (either normal speaker's impedance or high impedance). The
values in case of 30 dB gain are as follows:
S.C. across Load
0V
x
0.5Ω
Normal Operation
1.5Ω
x
Open Load
130Ω
70Ω
Infinite
D01AU1254
If the Line-Driver mode (Gv= 16 dB and Line Driver Mode diagnostic = 1) is selected, the same thresholds will
change as follows:
S.C. across Load
0Ω
1.5Ω
x
Normal Operation
4.5Ω
200Ω
x
Open Load
400Ω
infinite
D01AU1252
b) PERMANENT DIAGNOSTICS.
Detectable conventional faults are:
– SHORT TO GND
– SHORT TO Vs
– SHORT ACROSS THE SPEAKER
The following additional features are provided:
– OUTPUT OFFSET DETECTION
The TDA7563 has 2 operating statuses:
1 RESTART mode. The diagnostic is not enabled. Each audio channel operates independently from each
other. If any of the a.m. faults occurs, only the channel(s) interested is shut down. A check of the output
status is made every 1 ms (fig. 19). Restart takes place when the overload is removed.
2 DIAGNOSTIC mode. It is enabled via I2C bus and self activates if an output overload (such to cause
the intervention of the short-circuit protection) occurs to the speakers outputs . Once activated, the diagnostics procedure develops as follows (fig. 20):
10/20
TDA7563
– To avoid momentary re-circulation spikes from giving erroneous diagnostics, a check of the output status is made after 1ms: if normal situation (no overloads) is detected, the diagnostic is not performed and
the channel returns back active.
– Instead, if an overload is detected during the check after 1 ms, then a diagnostic cycle having a duration
of about 100 ms is started.
– After a diagnostic cycle, the audio channel interested by the fault is switched to RESTART mode. The
relevant data are stored inside the device and can be read by the microprocessor. When one cycle has
terminated, the next one is activated by an I2C reading. This is to ensure continuous diagnostics
throughout the car-radio operating time.
– To check the status of the device a sampling system is needed. The timing is chosen at microprocessor
level (over half a second is recommended).
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Figure 19. Restart timing without Diagnostic Enable (Permanent) - Each 1mS time, a sampling of
the fault is done
Out
1-2mS
1mS
1mS
1mS
1mS
t
Overcurrent and short
circuit protection intervention
(i.e. short circuit to GND)
Short circuit removed
Figure 20. Restart timing with Diagnostic Enable (Permanent)
1-2mS
100/200mS
1mS
1mS
t
Overcurrent and short
circuit protection intervention
(i.e. short circuit to GND)
Short circuit removed
OUTPUT DC OFFSET DETECTION
Any DC output offset exceeding +/- 2 V are signalled out. This inconvenient might occur as a consequence of
initially defective or aged and worn-out input capacitors feeding a DC component to the inputs, so putting the
speakers at risk of overheating.
This diagnostic has to be performed with low-level output AC signal (or Vin = 0).
The test is run with selectable time duration by microprocessor (from a "start" to a "stop" command):
– START = Last reading operation or setting IB1 - D5 - (OFFSET enable) to 1
11/20
TDA7563
– STOP = Actual reading operation
Excess offset is signalled out if persistent throughout the assigned testing time. This feature is disabled if any
overloads leading to activation of the short-circuit protection occurs in the process.
MULTIPLE FAULTS
When more misconnections are simultaneously in place at the audio outputs, it is guaranteed that at least one
of them is initially read out. The others are notified after successive cycles of I2C reading and faults removal,
provided that the diagnostic is enabled. This is true for both kinds of diagnostic (Turn on and Permanent).
The table below shows all the couples of double-fault possible. It should be taken into account that a short circuit
with the 4 ohm speaker unconnected is considered as double fault.
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Double fault table for Turn On Diagnostic
S. GND (so)
S. GND (sk)
S. Vs
S. Across L.
S. GND (so)
S. GND
S. GND
S. Vs + S. GND
S. GND
Open L.
S. GND
S. GND (sk)
/
S. GND
S. Vs
S. GND
Open L. (*)
S. Vs
/
/
S. Vs
S. Vs
S. Vs
S. Across L.
/
/
/
S. Across L.
N.A.
Open L.
/
/
/
/
Open L. (*)
S. GND (so) / S. GND (sk) in the above table make a distinction according to which of the 2 outputs is shorted
to ground (test-current source side= so, test-current sink side = sk). More precisely, in Channels LF and RR, so
= CH+, sk = CH-; in Channels LR and RF, so = CH-, sk = CH+ .
In Permanent Diagnostic the table is the same, with only a difference concerning Open Load(*) , which is not
among the recognisable faults. Should an Open Load be present during the device's normal working, it would
be detected at a subsequent Turn on Diagnostic cycle (i.e. at the successive Car Radio Turn on).
FAULTS AVAILABILITY
All the results coming from I2Cbus, by read operations, are the consequence of measurements inside a defined
period of time. If the fault is stable throughout the whole period, it will be sent out.
To guarantee always resident functions, every kind of diagnostic cycles (Turn on, Permanent, Offset) will be
reactivate after any I2C reading operation. So, when the micro reads the I2C, a new cycle will be able to start,
but the read data will come from the previous diag. cycle (i.e. The device is in Turn On state, with a short to Gnd,
then the short is removed and micro reads I2C. The short to Gnd is still present in bytes, because it is the result
of the previous cycle. If another I2C reading operation occurs, the bytes do not show the short). In general to
observe a change in Diagnostic bytes, two I2C reading operations are necessary.
THERMAL PROTECTION
Thermal protection is implemented through thermal foldback (fig. 21). Thermal foldback begins limiting the audio
input to the amplifier stage as the junction temperatures rise above the normal operating range. This effectively
limits the output power capability of the device thus reducing the temperature to acceptable levels without totally
interrupting the operation of the device. The output power will decrease to the point at which thermal equilibrium
is reached. Thermal equilibrium will be reached when the reduction in output power reduces the dissipated power such that the die temperature falls below the thermal foldback threshold. Should the device cool, the audio
level will increase until a new thermal equilibrium is reached or the amplifier reaches full power. Thermal foldback will reduce the audio output level in a linear manner.
12/20
TDA7563
Figure 21. Thermal Foldback Diagram
TH. WARN.
ON
Vout
TH. SH.
START
Vout
TH. SH.
END
Tj ( °C)
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< TSD
CD out
> TSD (with same input
signal)
Tj ( °C)
Tj ( °C)
I2C PROGRAMMING/READING SEQUENCES
A correct turn on/off sequence respectful of the diagnostic timings and producing no audible noises could be as
follows (after battery connection):
TURN-ON: PIN2 > 7V --- 10ms --- (STAND-BY OUT + DIAG ENABLE) --- 500 ms (min) --- MUTING OUT
TURN-OFF: MUTING IN --- 20 ms --- (DIAG DISABLE + STAND-BY IN) --- 10ms --- PIN2 = 0
Car Radio Installation: PIN2 > 7V --- 10ms DIAG ENABLE (write) --- 200 ms --- I2C read (repeat until All faults
disappear).
OFFSET TEST: Device in Play (no signal) -- OFFSET ENABLE - 30ms - I2C reading (repeat I2C reading until
high-offset message disappears).
13/20
TDA7563
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7563 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).
Data Validity
As shown by fig. 22, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and Stop Conditions
As shown by fig. 23 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
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Acknowledge
The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 24).
The receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so
that the SDAline is stable LOW during this clock pulse.
* Transmitter
– master (µP) when it writes an address to the TDA7563
– slave (TDA7563) when the µP reads a data byte from TDA7563
** Receiver
– slave (TDA7563) when the µP writes an address to the TDA7563
– master (µP) when it reads a data byte from TDA7563
Figure 22. Data Validity on the I2CBUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Figure 23. Timing Diagram on the I2CBUS
SCL
I2CBUS
SDA
D99AU1032
START
STOP
Figure 24. Acknowledge on the I2CBUS
SCL
1
2
3
7
8
9
SDA
MSB
START
14/20
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
TDA7563
SOFTWARE SPECIFICATIONS
All the functions of the TDA7563 are activated by I2C interface.
The bit 0 of the "ADDRESS BYTE" defines if the next bytes are write instruction (from µP to TDA7563) or read
instruction (from TDA7563 to µP).
Chip Address:
D7
D0
1
1
0
1
1
0
0
X
D8 Hex
X = 0 Write to device
X = 1 Read from device
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If R/W = 0, the µP sends 2 "Instruction Bytes": IB1 and IB2.
IB1
D7
X
D6
Diagnostic enable (D6 = 1)
Diagnostic defeat (D6 = 0)
D5
Offset Detection enable (D5 = 1)
Offset Detection defeat (D5 = 0)
D4
Front Channel
Gain = 30dB (D4 = 0)
Gain = 16dB (D4 = 1)
D3
Rear Channel
Gain = 30dB (D3 = 0)
Gain = 16dB (D3 = 1)
D2
Mute front channels (D2 = 0)
Unmute front channels (D2 = 1)
D1
Mute rear channels (D1 = 0)
Unmute rear channels (D1 = 1)
D0
CD 2% (D0 = 0)
CD 10% (D0 = 1)
D7
X
D6
used for testing
D5
used for testing
D4
Stand-by on - Amplifier not working - (D4 = 0)Stand-by off - Amplifier working - (D4 = 1)
D3
Power amplifier mode diagnostic (D3 = 0)Line driver mode diagnostic (D3 = 1)
D2
X
D1
Right ChannelPower amplifier working in standard mode (D1 = 0)Power amplifier working in high
efficiency mode (D1 = 1)
D0
Left ChannelPower amplifier working in standard mode (D0 = 0)Power amplifier working in high efficiency
mode (D0 = 1)
IB2
15/20
TDA7563
If R/W = 1, the TDA7563 sends 4 "Diagnostics Bytes" to µP: DB1, DB2, DB3 and DB4.
DB1
D7
Thermal warning active (D7 = 1)
D6
Diag. cycle not activated or not terminated (D6 = 0)
Diag. cycle terminated (D6 = 1)
D5
X
D4
Channel LF
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
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D3
Channel LF
Normal load (D3 = 0)
Short load (D3 = 1)
D2
Channel LF
Turn-on diag.: No open load (D2 = 0)
Open load detection (D2 = 1)
Offset diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
D1
Channel LF
No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
D0
Channel LFNo short to GND (D1 = 0)Short to GND (D1 = 1)
D7
Offset detection not activated (D7 = 0)
Offset detection activated (D7 = 1)
D6
X
D5
X
D4
Channel LR
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
D3
Channel LR
Normal load (D3 = 0)
Short load (D3 = 1)
D2
Channel LR
Turn-on diag.: No open load (D2 = 0)
Open load detection (D2 = 1)
Permanent diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
D1
Channel LRNo short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
D0
Channel LRNo short to GND (D1 = 0)
Short to GND (D1 = 1)
DB2
16/20
TDA7563
B3
D7
Stand-by status (= IB1 - D4)
D6
Diagnostic status (= IB1 - D6)
D5
X
D4
Channel RF
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
D3
Channel RF
Normal load (D3 = 0)
Short load (D3 = 1)
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D2
Channel RF
Turn-on diag.: No open load (D2 = 0)
Open load detection (D2 = 1)
Permanent diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
D1
Channel RF
No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
D0
Channel RF
No short to GND (D1 = 0)
Short to GND (D1 = 1)
D7
X
D6
X
D5
X
D4
Channel RR
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
D3
Channel R
RNormal load (D3 = 0)
Short load (D3 = 1)
D2
Channel RR
Turn-on diag.: No open load (D2 = 0)
Open load detection (D2 = 1)
Permanent diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
D1
Channel RR
No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
D0
Channel RR
No short to GND (D1 = 0)
Short to GND (D1 = 1)
DB4
17/20
TDA7563
Examples of bytes sequence
1 - Turn-On diagnostic - Write operation
Start
Address byte with D0 = 0
ACK
IB1 with D6 = 1
ACK
IB2
ACK
STOP
2 - Turn-On diagnostic - Read operation
Start
Address byte with D0 = 1
ACK
DB1
ACK
DB2
ACK
DB3
ACK
DB4
ACK
STOP
The delay from 1 to 2 can be selected by software, starting from T.B.D. ms
3a - Turn-On of the power amplifier with 30dB gain, mute on, diagnostic defeat, CD = 2%.
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Start
Address byte with D0 = 0
ACK
IB1
ACK
X0000000
IB2
ACK
STOP
ACK
STOP
ACK
STOP
XXX1XX11
3b - Turn-Off of the power amplifier
Start
Address byte with D0 = 0
ACK
IB1
ACK
X0XXXXXX
IB2
XXX0XXXX
4 - Offset detection procedure enable
Start
Address byte with D0 = 0
ACK
IB1
ACK
XX1XX11X
IB2
XXX1XXXX
5 - Offset detection procedure stop and reading operation (the results are valid only for the offset detection bits
(D2 of the bytes DB1, DB2, DB3, DB4).
Start
■
■
Address byte with D0 = 1
ACK
DB1
ACK
DB2
ACK
DB3
ACK
DB4
ACK
STOP
The purpose of this test is to check if a D.C. offset (2V typ.) is present on the outputs, produced by input
capacitor with anomalous leackage current or humidity between pins.
The delay from 4 to 5 can be selected by software, starting from T.B.D. ms
18/20
TDA7563
DIM.
MIN.
4.45
1.80
A
B
C
D
E
F (1)
G
G1
H (2)
H1
H2
H3
L (2)
L1
L2 (2)
L3
L4
L5
M
M1
N
O
R
R1
R2
R3
R4
V
V1
V2
V3
0.75
0.37
0.80
25.75
28.90
22.07
18.57
15.50
7.70
mm
TYP.
4.50
1.90
1.40
0.90
0.39
1.00
26.00
29.23
17.00
12.80
0.80
22.47
18.97
15.70
7.85
5
3.5
4.00
4.00
2.20
2
1.70
0.5
0.3
1.25
0.50
MAX.
4.65
2.00
MIN.
0.175
0.070
1.05
0.42
0.57
1.20
26.25
29.30
0.029
0.014
22.87
19.37
15.90
7.95
0.869
0.731
0.610
0.303
4.30
4.40
0.145
0.142
0.031
1.014
1.139
inch
TYP.
0.177
0.074
0.055
0.035
0.015
0.040
1.023
1.150
0.669
0.503
0.031
0.884
0.747
0.618
0.309
0.197
0.138
0.157
0.157
0.086
0.079
0.067
0.02
0.12
0.049
0.019
MAX.
0.183
0.079
OUTLINE AND
MECHANICAL DATA
0.041
0.016
0.022
0.047
1.033
1.153
0.904
0.762
0.626
0.313
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Flexiwatt27
(vertical)
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3.70
3.60
0.169
0.173
5˚ (Typ.)
3˚ (Typ.)
20˚ (Typ.)
45˚ (Typ.)
(1): dam-bar protusion not included
(2): molding protusion included
V
C
B
V
H
H1
V3
A
H2
O
H3
R3
L4
R4
V1
R2
L2
N
L3
R
L
L1
V1
V2
R2
D
R1
L5
Pin 1
R1
R1
E
G
G1
F
FLEX27ME
M
M1
7139011
19/20
TDA7563
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2003 STMicroelectronics - All Rights Reserved
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20/20
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