TDA7567PD
4 x 50 W differential quad power amplifier
with built-in diagnostics features
Features
■
Multipower BCD technology
■
MOSFET output power stage
■
DMOS power output
■
Differential Input
■
New high efficiency (class SB)
■
High output power capability 4x28 W/4 @
14.4 V, 1 kHz, 10% THD, 4x50 W MAX power
■
Max. output power 4x72 W/2
■
Full I2C bus driving:
– Standby
– Independent front/rear soft play/mute
– Selectable gain 26 dB /16 dB (for low noise
line output function)
– High efficiency enable/disable
– I2C bus digital diagnostics (including DC
and AC load detection)
PowerSO36
■
Operates both in I2C and non-I2C bus mode
■
Two selectable I2C bus addresses
■
Full fault protection
■
DC offset detection
■
Four independent short circuit protection
■
Clipping detector pin with selectable threshold
(2 %/10 %)
■
Standby/mute pin
■
Linear thermal shutdown with multiple thermal
warning
■
ESD protection
Description
The TDA7567PD is a new BCD technology quad
bridge power amplifier in PowerSO36 package
specially intended for automotive applications.
Thanks to the DMOS output stage the
TDA7567PD has a very low distortion allowing a
clear powerful sound. Among the features, its
superior efficiency performance coming from the
internal exclusive structure, makes it the most
suitable device to simplify the thermal
management in high power sets.
The dissipated output power under average
listening condition is in fact reduced up to 50 %
when compared to the level provided by
conventional class AB solutions.
This device is equipped with a full diagnostics
array that communicates the status of each
speaker through the I2C bus.
The I2C bus can be disabled and the device can
be controlled by standby/mute pin.
Table 1. Device summary
Order code
Package
Packing
TDA7567PD
PowerSO36
Tube
TDA7567PDTR
PowerSO36
Tape and reel
September 2013
Doc ID 16903 Rev 2
1/30
www.st.com
1
Contents
TDA7567PD
Contents
1
Block, application and pins connection diagrams . . . . . . . . . . . . . . . . . 6
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
4
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Diagnostics functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Permanent diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3
Output DC offset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
AC diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Multiple faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Faults availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
Fast muting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Address selection and I2C disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8
I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1
I2C programming/reading sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.2
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.2.1
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.2.2
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.2.3
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.2.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9
Software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10
Examples of bytes sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/30
Doc ID 16903 Rev 2
TDA7567PD
Contents
11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Doc ID 16903 Rev 2
3/30
List of tables
TDA7567PD
List of tables
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
4/30
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Double fault table for turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
IB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DB4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Doc ID 16903 Rev 2
TDA7567PD
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pins connection diagram (top of view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ITU R-ARM frequency response, weighting filter for transient pop. . . . . . . . . . . . . . . . . . . 11
Turn-on diagnostic: working principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SVR and output behavior (case 1: without turn-on diagnostic). . . . . . . . . . . . . . . . . . . . . . 12
SVR and output pin behavior (case 2: with turn-on diagnostic) . . . . . . . . . . . . . . . . . . . . . 13
Short circuit detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Load detection thresholds - high gain setting 26 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Load detection thresholds - low gain setting 16 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Restart timing without diagnostic enable (permanent) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Restart timing with diagnostic enable (permanent). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Current detection high: load impedance |Z| vs. output peak voltage . . . . . . . . . . . . . . . . . 16
Current detection low: load impedance |Z| vs. output peak voltage . . . . . . . . . . . . . . . . . . 16
Thermal foldback diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data validity on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Timing diagram on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Acknowledge on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PowerSO36 (slug up) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . 28
Doc ID 16903 Rev 2
5/30
Block, application and pins connection diagrams
TDA7567PD
1
Block, application and pins connection diagrams
Figure 1.
Block diagram
CLK
DATA
VCC
ST-BY/MUTE
ADSEL/I2CDIS
Thermal
Protection
& Dump
I2CBUS
Mute1 Mute2
CD
Clip
ADsel
Detector
OUT 3+
IN 3 +
16/26dB
IN 3 Short Circuit
Protection &
Diagnostic
OUT 3-
OUT 4+
IN 4 +
16/26dB
IN 4 -
OUT 4-
Short Circuit
Protection &
Diagnostic
OUT 1+
IN 1 +
16/26dB
IN 1 -
Short Circuit
OUT 1-
Protection &
Diagnostic
OUT 2+
IN 2+
16/26dB
IN 2 -
Short Circuit
OUT 2-
Protection &
Diagnostic
TAB
SVR
PWGND
6/30
Doc ID 16903 Rev 2
SGND
TDA7567PD
VCC
C7
3300F
VCC
C8
0.1F
VCC
Application diagram
VCC
Figure 2.
Block, application and pins connection diagrams
V(4V .. VCC)
STBY
19 12 36
11
6
33
+
34
35
I2C BUS
CLK
IN 3 +
IN 3 IN 4 +
IN 4 IN 1 +
IN 1 IN 2 +
IN 2 -
OUT 3
7
DATA
2
C1 0.22 F
C2 0.22F
C3 0.22 F
C4 0.22F
C5 0.22 F
C6 0.22F
C7 0.22 F
C8 0.22F
SGND
3
+
OUT 4
4
31
8
32
22
30
+
OUT 1
21
20
28
25
15
23
13
27
10
26
9
24
29
18
SVR
+
OUT 2
-
1
ADSEL/I2CDIS
TAB
47K
V
C6
10F
CD
Figure 3.
Pins connection diagram (top of view)
VCC
36
1
TAB
OUT3-
35
2
CK_HE-selector
PWGND
34
3
OUT4+
OUT3+
33
4
PWGND
IN3-
32
5
N.C.
IN3+
31
6
VCC
IN4+
30
7
DATA_Gain-selector
SGND
29
8
OUT4-
IN4-
28
9
ADSEL/I2CDIS
IN2+
27
10
OUT2-
IN2-
26
11
STBY
IN1+
25
12
VCC
SVR
24
13
PWGND
IN1-
23
14
N.C.
OUT1+
22
15
OUT2+
PWGND
21
16
N.C.
OUT1-
20
17
N.C.
VCC
19
18
CD
D06AU1641B
Doc ID 16903 Rev 2
7/30
Electrical specifications
TDA7567PD
2
Electrical specifications
2.1
Absolute maximum ratings
Table 2.
Absolute maximum ratings
Symbol
Value
Unit
Vop
Operating supply voltage
18
V
VS
DC supply voltage
28
V
Vpeak
Peak supply voltage (for t = 50 ms)
50
V
VCK
CK pin voltage
6
V
Data pin voltage
6
V
IO
Output peak current (not repetitive t = 100 ms)
8
A
IO
Output peak current (repetitive f > 10 Hz)
6
A
Power dissipation Tcase = 70 °C
85
W
-55 to 150
°C
Value
Unit
1
°C/W
VDATA
Ptot
Tstg, Tj
2.2
Parameter
Storage and junction temperature
Thermal data
Table 3.
Thermal Data
Symbol
Rth j-case
2.3
Parameter
Thermal resistance junction-to-case
Max.
Electrical characteristics
Refer to the test circuit, VS = 14.4 V; RL = 4 ; f = 1 kHz; GV = 26 dB; Tamb = 25 °C; unless
otherwise specified.
Table 4.
Electrical characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Power amplifier
VS
Supply voltage range
-
8
-
18
V
Id
Total quiescent drain current
-
-
180
300
mA
MAX power (VS = 15.2 V, square
wave input (2 Vrms))
-
50
-
W
25
20
28
22
-
W
W
-
50
40
75
-
W
W
W
PO
Output power
THD = 10 %
THD = 1 %
RL = 2 ; THD 10 %
RL = 2 ; THD 1 %
RL = 2 ; max. power
8/30
Doc ID 16903 Rev 2
TDA7567PD
Table 4.
Symbol
THD
Electrical specifications
Electrical characteristics (continued)
Parameter
Total harmonic distortion
Test condition
Min.
Typ.
Max.
Unit
PO = 1 W to 10 W; STD MODE
HE MODE; PO = 1.5 W
HE MODE; PO = 8 W
-
0.03
0.02
0.15
0.1
0.1
0.8
%
%
%
PO = 1-10 W, f = 10 kHz
-
0.2
0.5
%
GV = 16 dB; STD Mode
VO = 0.1 to 5 VRMS
-
0.02
0.05
%
CT
Cross talk
f = 1 kHz to 10 kHz, Rg = 600
50
60
-
dB
RIN
Input Impedance
-
60
100
130
K
GV1
Voltage gain 1
-
25
26
27
dB
Voltage gain match 1
-
-1
-
1
dB
Voltage gain 2
-
15
16
17
dB
GV2
Voltage gain match 2
-
-1
-
1
dB
EIN1
Output noise voltage 1
Rg = 600 20 Hz to 22 kHz
-
-
100
µV
EIN2
Output noise voltage 2
Rg = 600 ; GV = 16 dB
20 Hz to 22 kHz
-
-
30
µV
SVR
Supply voltage rejection
f = 100 Hz to 10 kHz; Vr = 1 Vpk;
Rg = 600
50
60
-
dB
BW
Power bandwidth
-
100
-
-
KHz
ASB
Standby attenuation
-
90
110
-
dB
ISB
Standby current
Vst-by = 0
-
1
10
µA
AM
Mute attenuation
-
80
100
-
dB
VOS
Offset voltage
Mute and play
-70
0
70
mV
VAM
Min. supply mute threshold
-
7
7.5
8
V
TON
Turn ON delay
D2/D1 (IB1) 0 to 1
-
15
40
ms
TOFF
Turn OFF delay
D2/D1 (IB1) 1 to 0
-
15
40
ms
VSBY
Standby/mute pin for standby -
0
-
1.5
V
VMU
Standby/mute pin for mute
-
3.5
-
5
V
VOP
Standby/mute pin for
operating
-
7
-
VS
V
20
40
A
Standby/mute pin current
Vst-by/mute = 8.5 V
-
IMU
Vst-by/mute < 1.5 V
-
0
5
A
GV1
GV2
CDLK
Clip det high leakage current
CD off / VCD = 6 V
-
0
5
A
CDSAT
Clip det sat. voltage
CD on; ICD = 1 mA
-
-
300
mV
D0 (IB1) = 1
5
10
15
%
CDTHD
Clip det THD level
D0 (IB1) = 0
1
2
3.5
%
Doc ID 16903 Rev 2
9/30
Electrical specifications
Table 4.
Symbol
VOS
TDA7567PD
Electrical characteristics (continued)
Parameter
Test condition
Min.
Typ.
Max.
Unit
During mute ON/OFF output
offset voltage
During standby ON/OFF
output offset voltage
ITU R-ARM weighted (full wave
rectified, standby pin linear
transition = 5.55 V to 6.45 V in 80
ms, @25 °C,
VS = 14.4V) see Figure 4
-7.5
-
+7.5
mV
-7.5
-
+7.5
mV
STD mode selector
ADSEL pin floating
-
-
1.5
V
HE mode selector
ADSEL pin floating
2.3
-
High gain selector
ADSEL pin floating
Low gain selector
ADSEL pin floating
CK_HE
DATA_gain
V
-
1.5
V
2.3
-
-
V
Turn on diagnostics 1 (power amplifier mode)
Pgnd
Short to GND det. (Below this
limit, the output is considered
in short circuit to GND)
-
-
1.2
V
Pvs
Short to VS det. (Above this
limit, the output is considered
in short circuit to VS)
Vs -1.2
-
-
V
1.8
-
Vs -1.8
V
-
-
0.5
Pnop
Normal operation
thresholds.(Within these
limits, the output is
considered without faults).
Power amplifier in standby
Lsc
Shorted load det.
Lop
Open load det.
85
-
Lnop
Normal load det.
1.5
-
45
-
-
1.2
V
Turn on diagnostics 2 (line driver mode)
Pgnd
Short to GND det. (Below this
limit, the output is considered Power amplifier in standby
in short circuit to GND)
Pvs
Short to Vs det. (Above this
limit, the output is considered in short circuit to VS)
Vs -1.2
-
-
V
Pnop
Normal operation thresholds.
(Within these limits, the
output is considered without
faults).
1.8
-
Vs -1.8
V
Lsc
Shorted Load det.
-
-
-
1.5
Lop
Open Load det.
-
330
-
-
Lnop
Normal Load det.
-
7
-
180
-
-
1.2
V
Permanent diagnostics 2 (Power amplifier mode or line driver mode)
Pgnd
10/30
Short to GND det. (Below this Power amplifier in mute or play,
limit, the output is considered one or more short circuits
in short circuit to GND)
protection activated
Doc ID 16903 Rev 2
TDA7567PD
Table 4.
Electrical specifications
Electrical characteristics (continued)
Symbol
Pvs
Pnop
Parameter
Test condition
Min.
Typ.
Max.
Unit
Vs -1.2
-
-
V
1.8
-
Vs -1.8
V
Power amplifier mode
-
-
0.5
Line driver mode
-
-
1.5
±1.5
±2
±2.5
V
Short to Vs det. (Above this
limit, the output is considered
in short circuit to VS)
Power amplifier in mute or play,
Normal operation thresholds. one or more short circuits
protection activated
(Within these limits, the
output is considered without
faults).
LSC
Shorted load det.
VO
Offset detection
INLH
Normal load current detection VO < (VS - 5)pk IB2 (D7) = 0
500
-
-
mA
INLL
Normal load current detection VO < (VS - 5)pk IB2 (D7) = 1
300
-
-
mA
IOLH
Open load current detection
VO < (VS - 5)pk IB2 (D7) = 0
-
-
250
mA
IOLL
Open load current detection
VO < (VS - 5)pk IB2 (D7) =1
-
-
125
mA
Power amplifier in play,
AC Input signals = 0
I2C bus interface
SCL
Clock frequency
-
-
-
400
kHz
VIL
Input low voltage
-
-
-
1.5
V
VIH
Input high voltage
-
2.3
-
-
V
Figure 4.
ITU R-ARM frequency response, weighting filter for transient pop
Output attenuation (dB)
10
0
-10
-20
-30
-40
-50
10
100
1000
Hz
Doc ID 16903 Rev 2
10000
100000
AC00343
11/30
Diagnostics functional description
TDA7567PD
3
Diagnostics functional description
3.1
Turn-on diagnostic
It is activated at the turn-on (standby out) under I2C bus request. Detectable output faults
are:
●
Short to GND
●
Short to Vs
●
Short across the speaker
●
Open speaker
To verify if any of the above misconnections are in place, a subsonic (inaudible) current
pulse (Figure 5) is internally generated, sent through the speaker(s) and sunk back. The
turn-on diagnostic status is internally stored until a successive diagnostic pulse is requested
(after a I2C reading).
If the "standby out" and "diagnostic enable" commands are both given through a single
programming step, the pulse takes place first (power stage still in standby mode, low,
outputs= high impedance).
Afterwards, when the amplifier is biased, the PERMANENT diagnostic takes place. The
previous turn-on state is kept until a short appears at the outputs.
Figure 5.
Turn-on diagnostic: working principle
Vs~5V
Isource
I (mA)
Isource
CH+
Isink
CHIsink
~100mS
t (ms)
Measure time
Figure 6 and 7 show SVR and output waveforms at the turn-on (standby out) with and
without turn-on diagnostic.
Figure 6.
SVR and output behavior (case 1: without turn-on diagnostic)
Vsvr
Out
Permanent diagnostic
acquisition time (100mS Typ)
Bias (power amp turn-on)
I2CB DATA
12/30
t
Diagnostic Enable
(Permanent)
FAULT
event
Permanent Diagnostics data (output)
permitted time
Doc ID 16903 Rev 2
Read Data
TDA7567PD
Figure 7.
Diagnostics functional description
SVR and output pin behavior (case 2: with turn-on diagnostic)
Vsvr
Out
Turn-on diagnostic
acquisition time (100mS Typ)
Permanent diagnostic
acquisition time (100mS Typ)
Turn-on Diagnostics data (output)
permitted time
Diagnostic Enable
(Turn-on)
Bias (power amp turn-on)
permitted time
FAULT
event
Diagnostic Enable
(Permanent)
Read Data
t
Permanent Diagnostics data (output)
permitted time
I2CB DATA
The information related to the outputs status is read and memorized at the end of the
current pulse top. The acquisition time is 100 ms (typ.). No audible noise is generated in the
process. As for short to GND / Vs the fault-detection thresholds remain unchanged from 26
dB to 16 dB gain setting. They are as follows:
Figure 8.
Short circuit detection thresholds
S.C. to GND
0V
x
1.2V
Normal Operation
1.8V
x
VS-1.8V
S.C. to Vs
VS-1.2V
D01AU1253
VS
Concerning short across the speaker / open speaker, the threshold varies from 26 dB to
16 dB gain setting, since different loads are expected (either normal speaker's impedance
or high impedance). The values in case of 26 dB gain are as follows:
Figure 9.
Load detection thresholds - high gain setting 26 dB
S.C. across Load
0V
x
0.5Ω
Normal Operation
1.5Ω
x
Open Load
85Ω
45Ω
Infinite
AC00060
If the line driver mode (Gv = 16 dB and line driver mode diagnostic = 1) is selected, the
same thresholds will change as follows:
Figure 10. Load detection thresholds - low gain setting 16 dB
S.C. across Load
0Ω
1.5Ω
x
Normal Operation
7Ω
Doc ID 16903 Rev 2
180Ω
x
Open Load
330Ω
infinite
13/30
Diagnostics functional description
3.2
TDA7567PD
Permanent diagnostics
Detectable conventional faults are:
–
Short to GND
–
Short to Vs
–
Short across the speaker
The following additional features are provided:
–
Output offset detection
The TDA7567PD has 2 operating status:
1.
RESTART mode. The diagnostic is not enabled. Each audio channel operates
independently from each other. If any of the a.m. faults occurs, only the channel(s)
interested is shut down. A check of the output status is made every 1 ms (Figure 11).
Restart takes place when the overload is removed.
2.
DIAGNOSTIC mode. It is enabled via I2C bus and self activates if an output overload
(such to cause the intervention of the short-circuit protection) occurs to the speakers
outputs. Once activated, the diagnostics procedure develops as follows (Figure 12):
–
To avoid momentary re-circulation spikes from giving erroneous diagnostics, a
check of the output status is made after 1ms: if normal situation (no overloads) is
detected, the diagnostic is not performed and the channel returns back active.
–
Instead, if an overload is detected during the check after 1 ms, then a diagnostic
cycle having a duration of about 100 ms is started.
–
After a diagnostic cycle, the audio channel interested by the fault is switched to
RESTART mode. The relevant data are stored inside the device and can be read
by the microprocessor. When one cycle has terminated, the next one is activated
by an I2C reading. This is to ensure continuous diagnostics throughout the carradio operating time.
–
To check the status of the device a sampling system is needed. The timing is
chosen at microprocessor level (over half a second is recommended).
Figure 11. Restart timing without diagnostic enable (permanent) - Each 1ms time, a
sampling of the fault is done
Out
1-2mS
1mS
1mS
1mS
1mS
t
Overcurrent and short
circuit protection intervention
(i.e. short circuit to GND)
Short circuit removed
Figure 12. Restart timing with diagnostic enable (permanent)
1-2mS
100/200mS
1mS
1mS
t
Overcurrent and short
circuit protection intervention
(i.e. short circuit to GND)
14/30
Short circuit removed
Doc ID 16903 Rev 2
TDA7567PD
3.3
Diagnostics functional description
Output DC offset detection
Any DC output offset exceeding ±2 V are signalled out. This inconvenient might occur as a
consequence of initially defective or aged and worn-out input capacitors feeding a DC
component to the inputs, so putting the speakers at risk of overheating.
This diagnostic has to be performed with low-level output AC signal (or Vin = 0).
The test is run with selectable time duration by microprocessor (from a "start" to a "stop"
command):
–
START = Last reading operation or setting IB1 - D5 - (OFFSET enable) to 1
–
STOP = Actual reading operation
Excess offset is signalled out if persistent throughout the assigned testing time. This feature
is disabled if any overloads leading to activation of the short-circuit protection occurs in the
process.
3.4
AC diagnostic
It is targeted at detecting accidental disconnection of tweeters in 2-way speaker and, more
in general, presence of capacitively (AC) coupled loads.
This diagnostic is based on the notion that the overall speaker's impedance (woofer +
parallel tweeter) will tend to increase towards high frequencies if the tweeter gets
disconnected, because the remaining speaker (woofer) would be out of its operating range
(high impedance). The diagnostic decision is made according to peak output current
thresholds, and it is enabled by setting (IB2-D2) = 1.
Two different detection levels are available:
●
●
High current threshold IB2 (D7) = 0
–
Iout > 500 mApk = NORMAL STATUS
–
Iout < 300 mApk = OPEN TWEETER
Low current threshold IB2 (D7) = 1
–
Iout > 250 mApk = NORMAL STATUS
–
Iout < 125 mApk = OPEN TWEETER
To correctly implement this feature, it is necessary to briefly provide a signal tone (with the
amplifier in "play") whose frequency and magnitude are such to determine an output current
higher than 500 mApk with IB2(D7)=0 (higher than 250 mApk with IB2(D7)=1) in normal
conditions and lower than 250 mApk with IB2(D7)=0 (lower than 125 mApk with IB2(D7)=1)
should the parallel tweeter be missing.
The test has to last for a minimum number of 3 sine cycles starting from the activation of the
AC diagnostic function IB2) up to the I2C reading of the results (measuring period). To
confirm presence of tweeter, it is necessary to find at least 3 current pulses over the above
thresholds over all the measuring period, else an "open tweeter" message will be issued.
The frequency / magnitude setting of the test tone depends on the impedance
characteristics of each specific speaker being used, with or without the tweeter connected
(to be calculated case by case). High-frequency tones (> 10 kHz) or even ultrasonic signals
are recommended for their negligible acoustic impact and also to maximize the impedance
module's ratio between with tweeter-on and tweeter-off.
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Diagnostics functional description
TDA7567PD
Figure 13 shows the load impedance as a function of the peak output voltage and the
relevant diagnostic fields.
This feature is disabled if any overloads leading to activation of the short-circuit protection
occurs in the process.
Figure 13. Current detection high: load impedance |Z| vs. output peak voltage
Load |z| (Ohm)
50
Iout (peak) 500mA
10
IB2(D7) = 0
High current detection area
(Normal load)
D5 = 0 of the DBx bytes
5
3
2
1
1
2
3
4
5
6
7
8
Vout (Peak)
Figure 14. Current detection low: load impedance |Z| vs. output peak voltage
Load |z| (Ohm)
50
Iout (peak) 250mA
10
IB2(D7) = 1
High current detection area
(Normal load)
D5 = 0 of the DBx bytes
5
3
2
1
0.5
1
1.5
2
2.5
Vout (Peak)
16/30
Doc ID 16903 Rev 2
3
3.5
4
TDA7567PD
4
Multiple faults
Multiple faults
When more misconnections are simultaneously in place at the audio outputs, it is
guaranteed that at least one of them is initially read out. The others are notified after
successive cycles of I2C reading and faults removal, provided that the diagnostic is enabled.
This is true for both kinds of diagnostic (Turn-on and Permanent).
The table below shows all the couples of double-fault possible. It should be taken into
account that a short circuit with the 4 ohm speaker unconnected is considered as double
fault.
Table 5.
Double fault table for turn-on diagnostic
S. GND (so)
S. GND (sk)
S. Vs
S. Across L.
Open L.
S. GND (so)
S. GND
S. GND
S. Vs + S.
GND
S. GND
S. GND
S. GND (sk)
/
S. GND
S. Vs
S. GND
Open L. (*)
S. Vs
/
/
S. Vs
S. Vs
S. Vs
S. Across L.
/
/
/
S. Across L.
N.A.
Open L.
/
/
/
/
Open L. (*)
S. GND (so) / S. GND (sk) in the above table make a distinction according to which of the 2
outputs is shorted to ground (test-current source side= so, test-current sink side = sk). More
precisely, in Channels CH3 and CH2, so = CH+, sk = CH-; in Channels CH4 and CH1, so =
CH-, sk = CH+.
In Permanent Diagnostic the table is the same, with only a difference concerning Open
Load(*), which is not among the recognizable faults. Should an Open Load be present
during the device's normal working, it would be detected at a subsequent Turn on Diagnostic
cycle (i.e. at the successive Car Radio Turn on).
4.1
Faults availability
All the results coming from I2Cb us, by read operations, are the consequence of
measurements inside a defined period of time. If the fault is stable throughout the whole
period, it will be sent out.
To guarantee always resident functions, every kind of diagnostic cycles (Turn on,
Permanent, Offset) will be reactivate after any I2C reading operation. So, when the micro
reads the I2C, a new cycle will be able to start, but the read data will come from the previous
diag. cycle (i.e. The device is in turn-on state, with a short to GND, then the short is removed
and micro reads I2C. The short to GND is still present in bytes, because it is the result of the
previous cycle. If another I2C reading operation occurs, the bytes do not show the short). In
general to observe a change in Diagnostic bytes, two I2C reading operations are necessary.
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Thermal protection
5
TDA7567PD
Thermal protection
Thermal protection is implemented through thermal foldback (Figure 15).
Thermal foldback begins limiting the audio input to the amplifier stage as the junction
temperatures rise above the normal operating range. This effectively limits the output power
capability of the device thus reducing the temperature to acceptable levels without totally
interrupting the operation of the device.
The output power will decrease to the point at which thermal equilibrium is reached.
Thermal equilibrium will be reached when the reduction in output power reduces the
dissipated power such that the die temperature falls below the thermal foldback threshold.
Should the device cool, the audio level will increase until a new thermal equilibrium is
reached or the amplifier reaches full power. Thermal foldback will reduce the audio output
level in a linear manner.
Three Thermal warning are available through the I2C bus data.
Figure 15. Thermal foldback diagram
TH. WARN.
ON
Vout
TH. SH.
START
Vout
< TSD
CD out
TH. SH.
END
> TSD (with same input
signal)
Tj ( °C)
Tj ( °C)
Tj ( °C)
18/30
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TDA7567PD
6
Fast muting
Fast muting
The muting time can be shortened to less than 1.5 ms by setting (IB2) D5 = 1. This option
can be useful in transient battery situations (i.e. during car engine cranking) to quickly
turnoff the amplifier for avoiding any audible effects caused by noise/transients being
injected by preamp stages. The bit must be set back to “0” shortly after the mute transition.
Doc ID 16903 Rev 2
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Address selection and I2C disable
7
TDA7567PD
Address selection and I2C disable
When the ADSEL/I2CDIS pin is left open the I2C bus is disabled and the device can be
controlled by the STBY/MUTE pin.
In this status (no - I2C bus) the CK pin enables the HIGH-EFFICIENCY MODE (0 = STD
MODE; 1 = HE MODE) and the DATA pin sets the gain (0 = 26 dB; 1 = 16 dB).
When the ADSEL/I2CDIS pin is connected to GND the I2C bus is active with address
.
To select the other I2C address a resistor must be connected to ADSEL/I2CDIS pin as
following:
0 7V --- 10ms DIAG ENABLE (write) --- 200 ms --- I2C read
(repeat until All faults disappear).
●
Offset test: Device in Play (no signal) -- OFFSET ENABLE - 30 ms - I2C reading (repeat
I2C reading until high-offset message disappears).
I2C bus interface
Data transmission from microprocessor to the TDA7567PD and viceversa takes place
through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up
resistors to positive supply voltage must be connected).
8.2.1
Data validity
As shown by Figure 16, the data on the SDA line must be stable during the high period of
the clock. The HIGH and LOW state of the data line can only change when the clock signal
on the SCL line is LOW.
8.2.2
Start and stop conditions
As shown by Figure 17 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH.
8.2.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
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I2C bus
8.2.4
TDA7567PD
Acknowledge
The transmitter puts a resistive high level on the SDA line during the acknowledge clock
pulse (see Figure 18). The receiver the acknowledges has to pull-down (low) the SDA line
during the acknowledge clock pulse, so that the SDA line is stable low during this clock
pulse.
Transmitter:
●
master (µP) when it writes an address to the TDA7567PD
●
slave (TDA7567PD) when the µP reads a data byte from TDA7567PD
Receiver:
●
slave (TDA7567PD) when the µP writes an address to the TDA7567PD
●
master (µP) when it reads a data byte from TDA7567PD
Figure 16. Data validity on the I2C bus
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Figure 17. Timing diagram on the I2C bus
SCL
I2CBUS
SDA
D99AU1032
START
STOP
Figure 18. Acknowledge on the I2C bus
SCL
1
2
3
7
8
9
SDA
MSB
START
22/30
D99AU1033
Doc ID 16903 Rev 2
ACKNOWLEDGMENT
FROM RECEIVER
TDA7567PD
9
Software specifications
Software specifications
All the functions of the TDA7567PD are activated by I2C interface.
The bit 0 of the "Address Byte" defines if the next bytes are write instruction (from µP to
TDA7567PD) or read instruction (from TDA7567PD to µP).
Chip address
D7
D0
1
1
0
1
1
0
(1)
X
D8 Hex
1. Address selector bit, please refer to address selection description on Chapter 7.
X = 0 Write to device
X = 1 Read from device
If R/W = 0, the µP sends 2 "Instruction Bytes": IB1 and IB2.
Table 6.
IB1
Bit
Instruction decoding bit
D7
0
D6
Diagnostic enable (D6 = 1)
Diagnostic defeat (D6 = 0)
D5
Offset detection enable (D5 = 1)
Offset detection defeat (D5 = 0)
D4
Front channel
Gain = 26 dB (D4 = 0)
Gain = 16 dB (D4 = 1)
D3
Rear channel
Gain = 26dB (D3 = 0)
Gain = 16dB (D3 = 1)
D2
Mute front channels (D2 = 0)
Unmute front channels (D2 = 1)
D1
Mute rear channels (D1 = 0)
Unmute rear channels (D1 = 1)
D0
CD 2% (D0 = 0)
CD 10% (D0 = 1)
Table 7.
IB2
Bit
Instruction decoding bit
D7
Current detection threshold
High th (D7 = 0)
Low th (D7 =1)
D6
0
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Software specifications
Table 7.
TDA7567PD
IB2 (continued)
Bit
Instruction decoding bit
D5
Normal muting time (D5 = 0)
Fast muting time (D5 = 1)
D4
Standby on - Amplifier not working - (D4 = 0)
Standby off - Amplifier working - (D4 = 1)
D3
Power amplifier mode diagnostic (D3 = 0)
Line driver mode diagnostic (D3 = 1)
D2
Current detection diagnostic enabled (D2 =1)
Current detection diagnostic defeat (D2 =0)
D1
Right channel power amplifier working in standard mode (D1 = 0)
Power amplifier working in high efficiency mode (D1 = 1)
D0
Left channel power amplifier working in standard mode (D0 = 0)
Power amplifier working in high efficiency mode (D0 = 1)
If R/W = 1, the TDA7567PD sends 4 "Diagnostics Bytes" to µP: DB1, DB2, DB3 and DB4.
Table 8.
DB1
Bit
Instruction decoding bit
D7
Thermal warning 1 active (D7 = 1) T = 140 °C
D6
Diag. cycle not activated or not terminated (D6 = 0)
Diag. cycle terminated (D6 = 1)
D5
Channel CH3
current detection IB2 (D7) = 0
Output peak current < 300 mA - Open load (D5 = 1)
Output peak current > 500 mA - Normal load (D5 = 0)
D4
Channel CH3
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
D3
Channel CH3
Normal load (D3 = 0)
Short load (D3 = 1)
D2
Channel CH3
Turn-on diag.: No open load (D2 = 0)
Open load detection (D2 = 1)
Offset diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
D1
Channel CH3
No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
D0
Channel CH3
No short to GND (D1 = 0)
Short to GND (D1 = 1)
24/30
Channel CH3
current detection IB2 (D7) = 1
Output peak current < 125 mA - Open load (D5 = 1)
Output peak current > 250 mA - Normal load (D5 = 0)
Doc ID 16903 Rev 2
TDA7567PD
Table 9.
Software specifications
DB2
Bit
Instruction decoding bit
D7
Offset detection not activated (D7 = 0)
Offset detection activated (D7 = 1)
D6
X
D5
Channel CH4
current detection IB2 (D7) = 0
Output peak current < 300 mA - Open load (D5 = 1)
Output peak current > 500 mA - Normal load (D5 = 0)
D4
Channel CH4
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
D3
Channel CH4
Normal load (D3 = 0)
Short load (D3 = 1)
D2
Channel CH4
Turn-on diag.: No open load (D2 = 0)
Open load detection (D2 = 1)
Permanent diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
D1
Channel CH4
No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
D0
Channel CH4
No short to GND (D1 = 0)
Short to GND (D1 = 1)
Table 10.
Channel CH4
current detection IB2 (D7) = 1
Output peak current < 125 mA - Open load (D5 = 1)
Output peak current > 250 mA - Normal load (D5 = 0)
DB3
Bit
Instruction decoding bit
D7
Standby status (= IB1 - D4)
D6
Diagnostic status (= IB1 - D6)
D5
Channel CH1
current detection IB2 (D7) = 0
Output peak current < 300 mA - Open load (D5 = 1)
Output peak current > 500 mA - Normal load (D5 = 0)
D4
Channel CH1
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
D3
Channel CH1
Normal load (D3 = 0)
Short load (D3 = 1)
Channel CH1
current detection IB2 (D7) = 1
Output peak current < 125 mA - Open load (D5 = 1)
Output peak current > 250 mA - Normal load (D5 = 0)
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25/30
Software specifications
Table 10.
TDA7567PD
DB3 (continued)
Bit
Instruction decoding bit
D2
Channel CH1
Turn-on diag.: No open load (D2 = 0)
Open load detection (D2 = 1)
Permanent diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
D1
Channel CH1
No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
D0
Channel CH1
No short to GND (D1 = 0)
Short to GND (D1 = 1)
Table 11.
DB4
Bit
Instruction decoding bit
D7
Thermal warning 2 active (D7 =1) Tj =133°C
D6
Thermal warning 3 active (D6 =1) Tj =118°C
D5
Channel CH2
current detection IB2 (D7) = 0
Output peak current < 300 mA - Open load (D5 = 1)
Output peak current > 500 mA - Normal load (D5 = 0)
D4
Channel CH2
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
D3
Channel CH2
Normal load (D3 = 0)
Short load (D3 = 1)
D2
Channel CH2
Turn-on diag.: No open load (D2 = 0)
Open load detection (D2 = 1)
Permanent diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
D1
Channel CH2
No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
D0
Channel CH2
No short to GND (D1 = 0)
Short to GND (D1 = 1)
26/30
Channel CH2
current detection IB2 (D7) = 1
Output peak current < 125mA - Open load (D5 = 1)
Output peak current > 250 mA - Normal load (D5 = 0)
Doc ID 16903 Rev 2
TDA7567PD
10
Examples of bytes sequence
Examples of bytes sequence
1 - Turn-on diagnostic - Write operation
Start
Address byte with D0 = 0
ACK
IB1 with D6 = 1
ACK
IB2
ACK
STOP
2 - Turn-on diagnostic - Read operation
Start Address byte with D0 = 1 ACK DB1
ACK DB2 ACK DB3 ACK DB4 ACK STOP
The delay from 1 to 2 can be selected by software, starting from 200 ms
3a - Turn-on of the power amplifier with 26 dB gain, mute on, diagnostic defeat, CD = 2 %
.
Start
Address byte with D0 = 0
ACK
IB1
ACK
X0000000
IB2
ACK
STOP
ACK
STOP
ACK
STOP
XXX1XX11
3b - Turn-off of the power amplifier
Start
Address byte with D0 = 0
ACK
IB1
ACK
X0XXXXXX
IB2
XXX0XXXX
4 - Offset detection procedure enable
Start
Address byte with D0 = 0
ACK
IB1
XX1XX11X
ACK
IB2
XXX1XXXX
5 - Offset detection procedure stop and reading operation (the results are valid only for the
offset detection bits (D2 of the bytes DB1, DB2, DB3, DB4)
.
Start Address byte with D0 = 1 ACK DB1
ACK
DB2 ACK DB3 ACK DB4 ACK STOP
●
The purpose of this test is to check if a D.C. offset (2 V typ.) is present on the outputs,
produced by input capacitor with anomalous leakage current or humidity between pins.
●
The delay from 4 to 5 can be selected by software, starting from 30 ms
Doc ID 16903 Rev 2
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Package information
11
TDA7567PD
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 19. PowerSO36 (slug up) mechanical data and package dimensions
DIM.
A
A2
A4
A5
a1
b
c
D
D1
D2
E
E1
E2
E3
E4
e
e3
G
H
h
L
N
s
MIN.
3.270
3.100
0.800
0.030
0.220
0.230
15.800
9.400
13.900
10.900
5.800
2.900
0
15.500
0.800
-
mm
TYP.
0.200
1.000
0.650
11.050
-
MAX.
3.410
3.180
1.000
-0.040
0.380
0.320
16.000
9.800
14.500
11.100
2.900
6.200
3.200
0.075
15.900
1.100
1.100
10˚
8˚
MIN.
0.1287
0.1220
0.0315
0.0012
0.0087
0.0091
0.6220
0.3701
0.5472
0.4291
0.2283
0.1142
0
0.6102
0.0315
-
inch
TYP.
0.0079
0.0394
0.0256
0.4350
-
MAX.
0.1343
0.1252
0.0394
-0.0016
0.0150
0.0126
0.6299
0.3858
0.5709
0.4370
0.1142
0.2441
0.1260
0.0031
0.6260
0.0433
0.0433
10˚
8˚
OUTLINE AND
MECHANICAL DATA
PowerSO36 (SLUG UP)
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”).
(2) No intrusion allowed inwards the leads.
7183931 G
28/30
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TDA7567PD
12
Revision history
Revision history
Table 12.
Document revision history
Date
Revision
Changes
11-Dec-2009
1
Initial release.
18-Sep-2013
2
Updated Disclaimer.
Doc ID 16903 Rev 2
29/30
TDA7567PD
Please Read Carefully:
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
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