TDA7569BDLVPD
4 x 50 W differential power amplifier with full I2C diagnostics,
high efficiency and low voltage operation
Datasheet - production data
Clipping detector pin with selectable threshold
(2 %/10 %)
Standby/mute pin
Linear thermal shutdown with multiple thermal
warning
'!0'03
ESD protection
3RZHU62 VOXJXS
Very robust against any kind of misconnection
Features
Improved SVR suppression during battery
transients
Multipower BCD technology
Capable to play down to 6 V (e.g. “Start-stop”)
MOSFET output power stage
Description
DMOS power output
Differential input
Class SB high efficiency
High output power capability:
– 4x28 W/4 Ω @ 14.4 V, f = 1 kHz, 10% THD
– 4x50 W/2 Ω @ 14.4 V, f = 1 kHz, 10% THD
Max power 4 x 75 W / 2 Ω
Full I2C bus driving:
– Standby
– Independent front/rear soft play/mute
– Selectable gain 26 dB /16 dB (for low noise
line output function)
– High efficiency enable/disable
– I2C bus digital diagnostics (including DC
bus AC load detection)
Fault detection through integrated diagnostics
DC offset detection
Four independent short circuit protection
The TDA7569BDLVPD is the most advanced
BCD technology quad bridge car radio amplifier,
including a wide range of innovative features.
The TDA7569BDLVPD is equipped with the most
complete diagnostics array that communicates
the status of each speaker through the I2C bus.
The differential input stage improves the
disturbance rejection.
The dissipated output power under average
listening condition is significantly reduced when
compared to the conventional class AB solutions,
thanks to the innovative internal design. Moreover
it has been designed to be very robust against
several kinds of misconnections.
It is moreover compliant to the most recent OEM
specifications for low voltage operation (so called
'start-stop' battery profile during engine stop),
helping car manufacturers to reduce the overall
emissions and thus contributing to environment
protection.
Table 1. Device summary
Order code
Package
Packing
TDA7569BDLVPD
PowerSO36
Tube
TDA7569BDLVPDTR
PowerSO36
Tape and reel
September 2014
This is information on a product in full production.
DocID024174 Rev 6
1/37
www.st.com
Contents
TDA7569BDLVPD
Contents
1
Block diagram and application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
5
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Diagnostics functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
Permanent diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3
Output DC offset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4
AC diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Multiple faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1
6
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1
7
8
2/37
Fast muting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Battery transition management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1
Low voltage (“start stop”) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2
Advanced battery management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Application suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.1
9
Faults availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
High efficiency introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.1
I2C programming/reading sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.2
Address selection and I2C disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.3
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DocID024174 Rev 6
TDA7569BDLVPD
Contents
9.3.1
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.3.2
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.3.3
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.3.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10
Software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11
Examples of bytes sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
12
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DocID024174 Rev 6
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3
List of tables
TDA7569BDLVPD
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
4/37
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin list description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Double fault table for turn on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
IB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
IB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DB4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DocID024174 Rev 6
TDA7569BDLVPD
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection diagram (top of view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Quiescent current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output power vs. supply voltage (4 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Distortion vs. output power (4 Ω, STD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Distortion vs. output power (4 Ω, HI-EFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Distortion vs. output power (2 Ω, STD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Distortion vs. output power (2 Ω, HI-EFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Distortion vs. frequency (2 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Distortion vs. output power Vs = 6 V (4 Ω, STD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Distortion vs. frequency (4 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Crosstalk vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Supply voltage rejection vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power dissipation vs. average output power (audio program simulation, 2 Ω). . . . . . . . . . 15
Power dissipation vs. average output power (audio program simulation, 4 Ω). . . . . . . . . . 16
Total power dissipation and efficiency vs. output power (4 Ω, HI-EFF, Sine). . . . . . . . . . . 16
Total power dissipation and efficiency vs. output power (4 Ω, STD, Sine) . . . . . . . . . . . . . 16
ITU R-ARM frequency response, weighting filter for transient pop. . . . . . . . . . . . . . . . . . . 16
Turn - on diagnostic: working principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SVR and output behavior (Case 1: without turn-on diagnostic) . . . . . . . . . . . . . . . . . . . . . 17
SVR and output pin behavior (Case 2: with turn-on diagnostic) . . . . . . . . . . . . . . . . . . . . . 18
Short circuit detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Load detection thresholds - high gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Load detection threshold - low gain setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Restart timing without diagnostic enable (permanent) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Restart timing with diagnostic enable (permanent). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Current detection high: load impedance |Z| vs. output peak voltage . . . . . . . . . . . . . . . . . 21
Current detection low: load impedance |Z| vs. output peak voltage . . . . . . . . . . . . . . . . . . 21
Thermal foldback diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Worst case battery cranking curve sample 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Worst case battery cranking curve sample 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Upwards fast battery transitions diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
High efficiency - basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data validity on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Timing diagram on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Acknowledge on the I2C bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PowerSO36 (slug up) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . 35
DocID024174 Rev 6
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5
Block diagram and application circuit
1
TDA7569BDLVPD
Block diagram and application circuit
Figure 1. Block diagram
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Figure 2. Application circuit
6
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6/37
DocID024174 Rev 6
'!0'03
TDA7569BDLVPD
2
Pin description
Pin description
Figure 3. Pin connection diagram (top of view)
/54
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For channel name reference: CH1 = LF, CH2 = LR, CH3 = RF, CH4 = RR.
Table 2. Pin list description
Pin #
Pin name
Function
1
TAB
2
OUT4+
3
CK
4
PWGND4
5
NC
6
VCC4
Supply voltage pin 4
7
DATA
I2C bus data pin/gain selector
8
OUT4-
Channel 4, - output
9
ADSEL
Address selector pin/ I2C bus disable (legacy select)
10
OUT2-
Channel 2, - output
11
STBY
Standby pin
12
VCC2
Supply voltage pin 2
13
PWGND2
14
NC
Not connected
15
NC
Not connected
16
CD
Clip detector output pin
Channel 4, + output
I2C bus clock/HE selector
Channel 4 output power ground
Not connected
Channel 2 output power ground
DocID024174 Rev 6
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36
Pin description
TDA7569BDLVPD
Table 2. Pin list description (continued)
8/37
Pin #
Pin name
Function
17
OUT2+
18
NC
19
OUT1-
Channel 1, - output
20
VCC1
Supply voltage pin1
21
PWGND1
22
OUT1+
23
IN1-
Channel 1, -input
24
SVR
SVR pin
25
IN1+
Channel 1, +input
26
IN2-
Channel 2, -input
27
IN2+
Channel 2, +input
28
IN4-
Channel 4, -input
29
SGND
Signal ground pin
30
IN4+
Channel 4, +input
31
IN3+
Channel 3, +input
32
IN3-
Channel 3, -input
33
OUT3+
34
PWGND3
35
VCC3
Supply voltage pin 3
36
OUT3-
Channel 3, - output
Channel 2, + output
Not connected
Channel 1 output power ground
Channel 1, + output
Channel 3, + output
Channel 3 output power ground
DocID024174 Rev 6
TDA7569BDLVPD
Electrical specifications
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol
Parameter
(1)
Value
Unit
18
V
Vop
Operating supply voltage
VS
DC supply voltage
28
V
Peak supply voltage (for tmax = 50 ms)
50
V
Ground pins voltage
-0.3 to 0.3
V
CK, CD and DATA pin voltage
-0.3 to 5.5
V
STBY pin voltage
-0.3 to Vop
V
Vpeak
GNDmax
VCK, VDATA,
VCD
Vstby
IO
Ptot
Tstg, Tj
Tamb
Output peak current (not repetitive tmax = 100ms)
8
Output peak current (repetitive f > 10 kHz)
6
Power dissipation Tcase = 70°C (2)
80
W
-55 to 150
°C
-40 to 105
°C
Storage and junction
temperature(3)
Operative temperature range
A
1. For RL = 2 Ω, the output current limit can be reached at Vop >16 V (internal self-protections can be
triggered).
2. This is max theoretical value, for power dissipation in real application conditions please refer to curves
reported in Section 3.4: Electrical characteristics curves.
3. A suitable heatsink/dissipation system should be used to keep Tj inside the specified limits.
3.2
Thermal data
Table 4. Thermal data
Symbol
Rth j-case
Parameter
Thermal resistance junction-to-case
DocID024174 Rev 6
Max.
Value
Unit
1
°C/W
9/37
36
Electrical specifications
3.3
TDA7569BDLVPD
Electrical characteristics
Refer to the test circuit, VS = 14.4 V; RL = 4 Ω; f = 1 kHz; GV = 26 dB; Tamb = 25 °C; unless
otherwise specified.
Tested at Tamb = 25 °C and Thot = 105 °C; functionality guaranteed for Tj = -40 °C to 150 °C.
Table 5. Electrical characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
RL = 4 Ω
6
-
18
V
RL = 2 Ω
6
-
16(1)
V
General characteristics
VS
Supply voltage range
Id
Total quiescent drain current
-
-
160
250
mA
RIN
Input impedance (differential)
-
90
115
140
K
IB1(D7) = 1;
Signal attenuation -6 dB
7
-
8
IB1(D7) = 0 (default);(2)
Signal attenuation -6 dB
5
-
5.8
VAM
Min. supply mute threshold
V
VOS
Offset voltage
Mute & play
-80
-
80
mV
Vdth
Dump threshold
-
18.5
-
20.5
V
ISB
Standby current
Vstandby = 0
-
1
5
μA
SVR
Supply voltage rejection
f = 100 Hz to 10 kHz; Vr = 1 Vpk;
Rg = 600 Ω
60
70
-
dB
TON
Turn on timing (Mute play
transition)
D2/D1 (IB1) 0 to 1
-
25
40
ms
TOFF
Turn off timing (Play mute
transition)
D2/D1 (IB1) 1 to 0
-
25
40
ms
THWARN1
Average junction temperature for
DB1 (D7) = 1
TH warning 1
-
160
-
THWARN2
Average junction temperature for
DB4 (D7) = 1
TH warning 2
-
145
-
THWARN3
Average junction temperature for
DB4 (D6) = 1
TH warning 3
-
125
-
-
50
-
W
THD = 10 %, RL = 4 Ω
THD = 1 %, RL = 4 Ω
25
20
28
22
-
W
W
RL = 2 Ω; THD 10 %
RL = 2 Ω; THD 1 %
RL = 2 Ω; Max. power(3) Vs = 14.4 V
40
32
60
50
40
75
-
W
W
W
-
6
-
W
°C
Audio performances
Max. power(3) Vs = 15.2V, RL = 4
PO
Output power
Max power@ Vs = 6 V, RL = 4 Ω
10/37
DocID024174 Rev 6
TDA7569BDLVPD
Electrical specifications
Table 5. Electrical characteristics (continued)
Symbol
THD
Parameter
Total harmonic distortion
Test condition
Min.
Typ.
Max.
Unit
PO = 1 W to 10 W; STD mode
HE MODE; PO = 1.5 W
HE MODE; PO = 8 W
-
0.015
0.05
0.1
0.1
0.1
0.5
%
%
%
PO = 1-10 W, f = 10 kHz
-
0.15
0.5
%
GV = 16 dB; STD Mode
VO = 0.1 to 5 VRMS
-
0.02
0.05
%
CT
Cross talk
f = 1 kHz to 10 kHz, Rg = 600 Ω
50
70
-
dB
GV1
Voltage gain 1
-
25
26
27
dB
Voltage gain match 1
-
-1
-
1
dB
Voltage gain 2
-
15
16
17
dB
GV2
Voltage gain match 2
-
-1
-
1
dB
EIN1
Output noise voltage 1
Rg = 600 Ω 20 Hz to 22 kHz
-
45
60
μV
EIN2
Output noise voltage 2
Rg = 600 Ω; GV = 16d B
20 Hz to 22 kHz
-
20
30
μV
BW
Power bandwidth
-
100
-
-
kHz
Input CMRR
VCM = 1 Vpk-pk; Rg = 0 Ω
-
70
-
dB
Standby to Mute and
Mute to Standby transition
Tamb = 25 °C,
ITU-R 2K, Csvr = 10 μF
Vs = 14.4 V
-7.5
-
+7.5
mV
Mute to Play transition
Tamb = 25 °C,
ITU-R 2K, Vs = 14.4 V (4)
-7.5
-
+7.5
mV
Play to Mute transition
Tamb = 25 °C,
ITU-R 2K, Vs = 14.4 V (5)
-7.5
-
+7.5
mV
GV1
GV2
CMRR
ΔVOITU
ITU Pop filter output voltage
Clip detector
CDLK
Clip det. high leakage current
CD off / VCD = 5.5 V
-
0
5
μA
CDSAT
Clip det sat. voltage
CD on; ICD = 1 mA
-
-
300
mV
CDTHD
Clip det THD level
D0 (IB1) = 1
5
10
15
%
D0 (IB1) = 0
1
2
3
%
Control pin characteristics
VSBY
Standby/mute pin for standby
-
0
-
1.2
V
VMU
Standby/mute pin for mute
-
2.9
-
3.5
V
VOP
Standby/mute pin for operating
-
4.5
-
18
V
DocID024174 Rev 6
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Electrical specifications
TDA7569BDLVPD
Table 5. Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Vst-by/mute = 4.5 V
-
1
5
μA
Vst-by/mute < 1.2 V
-
0
5
μA
IMU
Standby/mute pin current
ASB
Standby attenuation
-
90
110
-
dB
AM
Mute attenuation
-
80
100
-
dB
Turn on diagnostics 1 (Power amplifier mode)
Pgnd
Short to GND det. (below this
limit, the Output is considered in
short circuit to GND)
-
-
1.2
V
Pvs
Short to Vs det. (above this limit,
the output is considered in short
circuit to Vs)
Vs -1.2
-
-
V
1.8
-
Vs -1.8
V
-
-
0.5
Ω
Pnop
Power amplifier in standby
Normal operation thresholds.
(Within these limits, the output is
considered without faults).
Lsc
Shorted load det.
Lop
Open load det.
85
-
-
Ω
Lnop
Normal load det.
1.5
-
45
Ω
-
-
1.2
V
Turn on diagnostics 2 (Line driver mode)
Pgnd
Short to GND det. (below this
limit, the output is considered in
short circuit to GND)
Power amplifier in standby
Pvs
Short to Vs det. (above this limit,
the output is considered in short circuit to Vs)
Vs -1.2
-
-
V
Pnop
Normal operation thresholds.
(Within these limits, the output is considered without faults).
1.8
-
Vs -1.8
V
Lsc
Shorted load det.
-
-
-
1.5
Ω
Lop
Open load det.
-
330
-
-
Ω
Lnop
Normal load det.
-
7
-
180
Ω
-
-
1.2
V
Vs -1.2
-
-
V
1.8
-
Vs -1.8
V
Permanent diagnostics 2 (Power amplifier mode or line driver mode)
Pgnd
Pvs
Pnop
12/37
Short to GND det. (below this
limit, the Output is considered in
short circuit to GND)
Short to Vs det. (above this limit, Power amplifier in mute or play,
the output is considered in short one or more short circuits
circuit to Vs)
protection activated
Normal operation thresholds.
(Within these limits, the output is
considered without faults).
DocID024174 Rev 6
TDA7569BDLVPD
Electrical specifications
Table 5. Electrical characteristics (continued)
Symbol
Parameter
LSC
Shorted load det.
VO
Offset detection
INLH
Normal load current detection
IOLH
Open load current detection
INLL
Normal load current detection
IOLL
Open load current detection
Test condition
Min.
Typ.
Max.
Unit
Power amplifier mode
-
-
0.5
Ω
Line driver mode
-
-
1.5
Ω
±1.5
±2
±2.5
V
500
-
-
mA
-
-
250
mA
250
-
-
mA
-
-
125
mA
Power amplifier in play,
AC input signals = 0
VO < (VS-5)pk, IB2 (D7) = 0
VO < (VS-5)pk, IB2 (D7) = 1
I2C bus interface
SCL
Clock frequency
-
-
-
400
kHz
VIL
Input low voltage
-
-
-
1.5
V
VIH
Input high voltage
-
2.3
-
-
V
1. When VS > 16 V the output current limit is reached (triggering embedded internal protections).
2. In legacy mode only low threshold option is available.
3. Saturated square wave output.
4. Voltage ramp on STBY pin:
from 3.3 V to 4.2 V in t ≥ 40 ms.
In case of I2C mode command IB1(D1) = 1 (Mute → Unmute rear channels) and/or IB1(D2) = 1 (Mute → Unmute front
channels) must be transmitted before to start the voltage ramp on STBY pin.
5. Voltage ramp on STBY pin:
from 4.05 V to 3.55 V in t ≥ 40 ms.
In case of I2C mode command IB1(D1) = 0 Unmute → Mute rear channels) and/or IB1(D2) = 0 (Unmute → Mute front
channels) must be NOT transmitted before to start the voltage ramp on STBY pin.
DocID024174 Rev 6
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36
Electrical specifications
3.4
TDA7569BDLVPD
Electrical characteristics curves
Figure 4. Quiescent current vs. supply voltage
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Figure 6. Distortion vs. output power (4 Ω, STD) Figure 7. Distortion vs. output power (4 Ω, HIEFF)
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Figure 8. Distortion vs. output power (2 Ω, STD)
Figure 9. Distortion vs. output power (2 Ω, HIEFF)
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Electrical specifications
Figure 10. Distortion vs. frequency (2 Ω)
Figure 11. Distortion vs. output power Vs = 6 V
(4 Ω, STD)
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Figure 12. Distortion vs. frequency (4 Ω)
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Figure 13. Crosstalk vs. frequency
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Figure 14. Supply voltage rejection vs.
frequency
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Figure 15. Power dissipation vs. average output
power (audio program simulation, 2 Ω)
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Electrical specifications
TDA7569BDLVPD
Figure 16. Power dissipation vs. average output
power (audio program simulation, 4 Ω)
Figure 17. Total power dissipation and
efficiency vs. output power (4 Ω, HI-EFF, Sine)
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Figure 19. ITU R-ARM frequency response,
weighting filter for transient pop
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Figure 18. Total power dissipation and
efficiency vs. output power (4 Ω, STD, Sine)
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DocID024174 Rev 6
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TDA7569BDLVPD
Diagnostics functional description
4
Diagnostics functional description
4.1
Turn-on diagnostic
It is strongly recommended to activate this feature at turn-on (standby out) with I2C bus
request. Detectable output faults are:
SHORT TO GND
SHORT TO Vs
SHORT ACROSS THE SPEAKER
OPEN SPEAKER
To verify if any of the above misconnections are in place, a subsonic (inaudible) current
pulse (Figure 20) is internally generated, sent through the speaker(s) and sunk back.The
Turn On diagnostic status is internally stored until a successive diagnostic pulse is
requested (after a I2C reading).
If the "standby out" and "diag. enable" commands are both given through a single
programming step, the pulse takes place first (the power stage stays 'off' during the pules,
showing high impedance at the outputs).
Afterwards, when the Amplifier is biased, the PERMANENT diagnostic takes place. The
previous turn-on state is kept until a short appears at the outputs.
Figure 20. Turn - on diagnostic: working principle
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Figure 21 and 22 show SVR and OUTPUT waveforms at the turn-on (standby out) with and
without turn-on diagnostic.
Figure 21. SVR and output behavior (Case 1: without turn-on diagnostic)
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Diagnostics functional description
TDA7569BDLVPD
Figure 22. SVR and output pin behavior (Case 2: with turn-on diagnostic)
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The information related to the outputs status is read and memorized at the end of the
current pulse plateau. The acquisition time is 100 ms (typ.). No audible noise is generated in
the process. As for SHORT TO GND / Vs the fault-detection thresholds remain unchanged
from 26 dB to 16 dB gain setting. They are as follows:
Figure 23. Short circuit detection thresholds
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Concerning SHORT ACROSS THE SPEAKER / OPEN SPEAKER, the threshold varies
from 26 dB to 16 dB gain setting, since different loads are expected (either normal speaker's
impedance or high impedance). The values in case of 26 dB gain are as follows:
Figure 24. Load detection thresholds - high gain setting
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If the Line-Driver mode (Gv= 16 dB and Line Driver Mode diagnostic = 1) is selected, the
same thresholds will change as follows:
Figure 25. Load detection threshold - low gain setting
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DocID024174 Rev 6
TDA7569BDLVPD
4.2
Diagnostics functional description
Permanent diagnostics
Detectable conventional faults are:
Short to GND
Short to Vs
Short across the speaker
The following additional feature is provided:
Output offset detection
The TDA7569BDLVPD has 2 operating status:
1. RESTART mode. The diagnostic is not enabled. Each audio channel operates
independently of each other. If any of the a.m. faults occurs, only the channel(s)
interested is shut down. A check of the output status is made every 1 ms (Figure 26).
Restart takes place when the overload is removed.
2. DIAGNOSTIC mode. It is enabled via I2C bus and it self activates if an output overload
(such as to cause the intervention of the short-circuit protection) occurs to the speakers
outputs. Once activated, the diagnostics procedure develops as follows (Figure 27):
–
To avoid momentary re-circulation spikes from giving erroneous diagnostics, a
check of the output status is made after 1ms: if normal situation (no overloads) is
detected, the diagnostic is not performed and the channel returns active.
–
Instead, if an overload is detected during the check after 1 ms, then a diagnostic
cycle having a duration of about 100 ms is started.
–
After a diagnostic cycle, the audio channel interested by the fault is switched to
RESTART mode. The relevant data are stored inside the device and can be read
by the microprocessor. When one cycle has terminated, the next one is activated
by an I2C reading. This is to ensure continuous diagnostics throughout the carradio operating time.
–
To check the status of the device a sampling system is needed. The timing is
chosen at microprocessor level (over half a second is recommended).
Figure 26. Restart timing without diagnostic enable (permanent) - Each 1 mS
time, a sampling of the fault is done
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Figure 27. Restart timing with diagnostic enable (permanent)
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DocID024174 Rev 6
19/37
36
Diagnostics functional description
4.3
TDA7569BDLVPD
Output DC offset detection
Any DC output offset exceeding ±2 V are signalled out. This inconvenient might occur as a
consequence of initially defective or aged and worn-out input capacitors feeding a DC
component to the inputs, so putting the speakers at risk of overheating.
This diagnostic has to be performed with low-level output AC signal (or Vin = 0).
The test is run with selectable time duration by microprocessor (from a "start" to a "stop"
command):
START = Last reading operation or setting IB1 - D5 - (OFFSET enable) to 1
STOP = Actual reading operation
Excess offset is signalled out if it is persistent for all the assigned testing time. This feature is
disabled if any overloads leading to activation of the short-circuit protection occurs in the
process.
4.4
AC diagnostic
It is targeted at detecting accidental disconnection of tweeters in 2-way speaker and, more
in general, presence of capacitive (AC) coupled loads.
This diagnostic is based on the notion that the overall speaker's impedance (woofer +
parallel tweeter) will tend to increase towards high frequencies if the tweeter gets
disconnected, because the remaining speaker (woofer) would be out of its operating range
(high impedance). The diagnostic decision is made according to peak output current
thresholds, and it is enabled by setting (IB2-D2) = 1. Two different detection levels are
available:
High current threshold IB2 (D7) = 0
Iout > 500 mApk = normal status
Iout < 250 mApk = open tweeter
Low current threshold IB2 (D7) = 1
Iout > 250 mApk = normal status
Iout < 125 mApk = open tweeter
To correctly implement this feature, it is necessary to briefly provide a signal tone (with the
amplifier in "play") whose frequency and magnitude are such as to produce an output
current higher than 500 mApk with IB2(D7) = 0 (higher than 250 mApk with IB2(D7) = 1) in
normal conditions and lower than 250 mApk with IB2(D7) = 0 (lower than 125 mApk with
IB2(D7) =1) when the parallel tweeter is missing/disconnected.
The test has to last for a minimum number of 3 sine cycles starting from the activation of the
AC diagnostic function IB2 up to the I2C reading of the results (measuring period). To
confirm the presence of tweeter, it is necessary to find at least 3 current pulses over the
above threshold during the measuring period, else an "open tweeter" message will be
issued.
The frequency / magnitude setting of the test tone depends on the impedance
characteristics of each specific speaker being used, with or without the tweeter connected
(to be calculated case by case). High-frequency tones (> 10 kHz) or even ultrasonic signals
are recommended for their negligible acoustic impact and also to maximize the impedance
module's ratio between with tweeter-on and tweeter-off.
20/37
DocID024174 Rev 6
TDA7569BDLVPD
Diagnostics functional description
Figure 28 and 29 shows the load impedance as a function of the peak output voltage and
the relevant diagnostic fields.
It is recommended to keep the output voltage always below 8 V (high threshold case) or 4 V
(low threshold case), to avoid the circuit to saturate (causing wrong detection cases).
This feature is disabled if any overloads leading to activation of the short-circuit protection
occurs in the process.
Figure 28. Current detection high: load impedance |Z| vs. output peak voltage
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Multiple faults
5
TDA7569BDLVPD
Multiple faults
When more misconnections are simultaneously in place at the audio outputs, it is
guaranteed that at least one of them is initially read out. The others are notified after
successive cycles of I2C reading and faults removal, provided that the diagnostic is enabled.
This is true for both kinds of diagnostic (Turn on and Permanent).
The table below shows all the couples of double-fault possible. It should be taken into
account that a short circuit with the 4 ohm speaker unconnected is considered as double
fault.
Table 6. Double fault table for turn on diagnostic
S. GND
S. Vs
S. Across L.
Open L.
S. GND
S. GND
S. Vs + S. GND
S. GND
S. GND
S. Vs
/
S. Vs
S. Vs
S. Vs
S. Across L.
/
/
S. Across L.
N.A.
Open L.
/
/
/
Open L. (*)
In Permanent Diagnostic the table is the same, with only a difference concerning Open
Load(*), which is not among the recognizable faults. Should an Open Load be present
during the device's normal working, it would be detected at a subsequent Turn on
Diagnostic cycle (i.e. at the successive Car Radio Turn on).
5.1
Faults availability
All the results coming from I2C bus, by read operations, are the consequence of
measurements inside a defined period of time. If the fault is stable throughout the whole
period, it will be sent out.
To guarantee always resident functions, every kind of diagnostic cycles (Turn-on,
Permanent, Offset) will be reactivate after any I2C reading operation. So, when the micro
reads the I2C, a new cycle will be able to start, but the read data will come from the previous
diag. cycle (i.e. The device is in Turn-on state, with a short to GND, then the short is
removed and micro reads I2C. The short to GND is still present in bytes, because it is the
result of the previous cycle. If another I2C reading operation occurs, the bytes do not show
the short). In general to observe a change in Diagnostic bytes, two I2C reading operations
are necessary.
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TDA7569BDLVPD
6
Thermal protection
Thermal protection
Thermal protection is implemented through thermal foldback (Figure 30).
Thermal foldback begins limiting the audio input to the amplifier stage as the junction
temperatures rise above the normal operating range. This effectively limits the output power
capability of the device thus reducing the temperature to acceptable levels without totally
interrupting the operation of the device.
The output power will decrease to the point at which thermal equilibrium is reached.
Thermal equilibrium will be reached when the reduction in output power reduces the
dissipated power such that the die temperature falls below the thermal foldback threshold.
Should the device cool, the audio level will increase until a new thermal equilibrium is
reached or the amplifier reaches full power. Thermal foldback will reduce the audio output
level in a linear manner.
Three Thermal warning are available through the I2C bus data. After thermal shut down
threshold is reached, the CD could toggle (as shown in Figure 30) or stay low, depending on
signal level.
Figure 30. Thermal foldback diagram
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Fast muting
The muting time can be shortened to less than 1.5ms by setting (IB2) D5 = 1. This option
can be useful in transient battery situations (i.e. during car engine cranking) to quickly
turnoff the amplifier to avoid any audible effects caused by noise/transients being injected
by preamp stages. The bit must be set back to “0” shortly after the mute transition.
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Battery transition management
TDA7569BDLVPD
7
Battery transition management
7.1
Low voltage (“start stop”) operation
The most recent OEM specifications are requiring automatic stop of car engine at traffic
light, in order to reduce emissions of polluting substances. The TDA7569BDLVPD, thanks to
its innovating design, is able to play music when battery falls down to 6/7V during such
conditions, without producing audible pop noise. The maximum system power will be
reduced accordingly.
Worst case battery cranking curves are shown below, indicating the shape and durations of
allowed battery transitions
Figure 31. Worst case battery cranking curve sample 1
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V1 = 12 V; V2 = 6 V; V3 = 7 V; V4 = 8 V
t1 = 2 ms; t2 = 50 ms; t3 = 5 ms; t4 = 300 ms; t5 =10 ms; t6 = 1 s; t7 = 2 ms
Figure 32. Worst case battery cranking curve sample 2
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V1 = 12 V; V2 = 6 V; V3 = 7 V
t1 = 2 ms; t2 = 5 ms; t3 = 15 ms; t5 = 1 s; t6 = 50 ms
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TDA7569BDLVPD
7.2
Battery transition management
Advanced battery management
In addition to compatibility with low Vbatt, the TDA7569BDLVPD is able to substain upwards
fast battery transitions (like the one showed in Figure 33) without causing unwanted audible
effect, thanks to the innovative circuit topology.
Figure 33. Upwards fast battery transitions diagram
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36
Application suggestions
TDA7569BDLVPD
8
Application suggestions
8.1
High efficiency introduction
Thanks to its operating principle, the TDA7569BDLVPD obtains a substantial reduction of
power dissipation from traditional class-AB amplifiers without being affected by the massive
radiation effects and complex circuitry normally associated with class-D solutions.
The high efficiency operating principle is based on the use of bridge structures which are
connected by means of a power switch. In particular, as shown in Figure 1, Ch1 is linked to
Ch2, while Ch3 to Ch4. The switch, controlled by a logic circuit which senses the input
signals, is closed at low volumes (output power steadily lower than 2.5 W) and the system
acts like a "single bridge" with double load. In this case, the total power dissipation is a
quarter of a double bridge.
Due to its structure, the highest efficiency level can be reached when symmetrical loads are
applied on channels sharing the same switch.
Figure 34. High efficiency - basic structure
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When the power demand increases to more than 2.5 W, the system behavior is switched
back to a standard double bridge in order to guarantee the maximum output power, while in
the 6 V start-stop devices the High Efficiency mode is automatically disabled at low VCC
(7.3 V ±0.3 V). No need to re-program it when VCC goes back to normal levels.
The results show (Figure 19) that in the range 2-4 W (@ VCC = 14.4 V, RL = 4 Ω), with the
High Efficiency mode, the dissipated power gets up to 50 % less than the value obtained
with the standard mode.
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DocID024174 Rev 6
I2C bus
TDA7569BDLVPD
9
I2C bus
9.1
I2C programming/reading sequences
A correct turn on/off sequence with respect to the diagnostic timings and producing no
audible noises could be as follows (after battery connection):
TURN-ON: PIN2 > 4.5V --- 10ms --- (STAND-BY OUT + DIAG ENABLE) --- 1 s (min) -- MUTING OUT
TURN-OFF: MUTING IN - wait for 50 ms - HW ST-BY IN (ST-BY pin ≤ 1.2 V)
Car Radio Installation: PIN2 > 4.5 V --- 10ms DIAG ENABLE (write) --- 200 ms --- I2C
read (repeat until All faults disappear).
OFFSET TEST: Device in Play (no signal) -- OFFSET ENABLE - 30ms - I2C reading
(repeat I2C reading until high-offset message disappears).
9.2
Address selection and I2C disable
When the ADSEL/I2CDIS pin is left open the I2C bus is disabled and the device can be
controlled by the STBY/MUTE pin.
In this status (no - I2C bus) the CK pin enables the HIGH-EFFICIENCY MODE (0 = STD
MODE; 1 = HE MODE) and the DATA pin sets the gain (0 = 26 dB; 1 = 16 dB).
When the ADSEL/I2CDIS pin is connected to GND the I2C bus is active with address
.
To select the other I2C address a resistor must be connected to ADSEL/I2CDIS pin as
following:
0 < R < 1 kΩ: I2C bus active with address
11 < R < 21 kΩ: I2C bus active with address
40 < R < 70 kΩ: I2C bus active with address
R > 120 kΩ: Legacy mode
(x: read/write bit sector)
9.3
I2C bus interface
Data transmission from microprocessor to the TDA7569BDLVPD and viceversa takes place
through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up
resistors to positive supply voltage must be connected).
9.3.1
Data validity
As shown by Figure 35, the data on the SDA line must be stable during the high period of
the clock. The HIGH and LOW state of the data line can only change when the clock signal
on the SCL line is LOW.
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36
I2C bus
9.3.2
TDA7569BDLVPD
Start and stop conditions
As shown by Figure 36 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH.
9.3.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
9.3.4
Acknowledge
The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 37). The receiver** has to pull-down (LOW) the SDA line during the
acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse.
* Transmitter
–
master (μP) when it writes an address to the TDA7569BDLVPD
–
slave (TDA7569BDLVPD) when the μP reads a data byte from TDA7569BDLVPD
** Receiver
–
slave (TDA7569BDLVPD) when the μP writes an address to the
TDA7569BDLVPD
–
master (μP) when it reads a data byte from TDA7569BDLVPD
Figure 35. Data validity on the I2C bus
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Figure 36. Timing diagram on the I2C bus
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Figure 37. Acknowledge on the I2C bus
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28/37
DocID024174 Rev 6
*$3*36
TDA7569BDLVPD
10
Software specifications
Software specifications
All the functions of the TDA7569BDLVPD are activated by I2C interface.
The bit 0 of the "ADDRESS BYTE" defines if the next bytes are write instruction (from μP to
TDA7569BDLVPD) or read instruction (from TDA7569BDLVPD to μP).
Chip address
D7
1
D0
1
0
1
1
(*)
(*)
X
D8 Hex
X = 0 Write to device
X = 1 Read from device
If R/W = 0, the μP sends 2 "Instruction Bytes": IB1 and IB2.
(*) address selector bit, please refer to address selection description on Section 9.2.
Table 7. IB1
Bit
Instruction decoding bit
D7
Supply transition mute threshold high (D7 = 1) (8 V)
Supply transition mute threshold low (D7 = 0) (6 V)
D6
Diagnostic enable (D6 = 1)
Diagnostic defeat (D6 = 0)
D5
Offset Detection enable (D5 = 1)
Offset Detection defeat (D5 = 0)
D4
Front Channel
Gain = 26 dB (D4 = 0)
Gain = 16 dB (D4 = 1)
D3
Rear Channel
Gain = 26 dB (D3 = 0)
Gain = 16 dB (D3 = 1)
D2
Mute front channels (D2 = 0)
Unmute front channels (D2 = 1)
D1
Mute rear channels (D1 = 0)
Unmute rear channels (D1 = 1)
D0
CD 2% (D0 = 0)
CD 10% (D0 = 1)
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36
Software specifications
TDA7569BDLVPD
Table 8. IB2
Bit
Instruction decoding bit
D7
Current detection threshold
High th (D7 = 0)
Low th (D7 =1)
D6
0
D5
Normal muting time (D5 = 0)
Fast muting time (D5 = 1)
D4
Stand-by on - Amplifier not working - (D4 = 0)
Stand-by off - Amplifier working - (D4 = 1)
D3
Power amplifier mode diagnostic (D3 = 0)
Line driver mode diagnostic (D3 = 1)
D2
Current Detection Diagnostic Enabled (D2 =1)
Current Detection Diagnostic Defeat (D2 =0)
D1
Right Channel Power amplifier working in standard mode (D1 = 0)
Power amplifier working in high efficiency mode (D1 = 1)
D0
Left Channel Power amplifier working in standard mode (D0 = 0)
Power amplifier working in high efficiency mode (D0 = 1)
If R/W = 1, the TDA7569BDLVPD sends 4 "Diagnostics Bytes" to μP: DB1, DB2, DB3 and
DB4.
Table 9. DB1
Bit
Instruction decoding bit
D7
Thermal warning 1 active (D7 = 1), Tj = 160°C
D6
Diag. cycle not activated or not terminated (D6 = 0)
Diag. cycle terminated (D6 = 1)
D5
Channel LF (CH1)
Current detection IB2 (D7) = 0
Output peak current < 250 mA - Open load (D5 = 1)
Output peak current > 500 mA - Normal load (D5 = 0)
Channel LF (CH1)
Current detection IB2 (D7) = 1
Output peak current < 125 mA - Open load (D5 = 1)
Output peak current > 250 mA - Normal load (D5 = 0)
D4
Channel LF (CH1)
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
-
D3
Channel LF (CH1)
Normal load (D3 = 0)
Short load (D3 = 1)
-
D2
Channel LF (CH1)
Turn-on diag.: No open load (D2 = 0)
Open load detection (D2 = 1)
Offset diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
-
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-
DocID024174 Rev 6
TDA7569BDLVPD
Software specifications
Table 9. DB1 (continued)
Bit
Instruction decoding bit
D1
Channel LF (CH1)
No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
-
D0
Channel LF (CH1)
No short to GND (D1 = 0)
Short to GND (D1 = 1)
-
Table 10. DB2
Bit
Instruction decoding bit
D7
Offset detection not activated (D7 = 0)
Offset detection activated (D7 = 1)
-
D6
X
-
D5
Channel LR (CH2)
Current detection IB2 (D7) = 0
Output peak current < 250 mA - Open load (D5 = 1)
Output peak current > 500 mA - Normal load (D5 = 0)
Channel LR (CH2)
Current detection IB2 (D7) = 1
Output peak current < 125 mA - Open load (D5 = 1)
Output peak current > 250 mA - Normal load (D5 = 0)
D4
Channel LR (CH2)
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
-
D3
Channel LR (CH2)
Normal load (D3 = 0)
Short load (D3 = 1)
-
D2
Channel LR (CH2)
Turn-on diag.: No open load (D2 = 0)
Open load detection (D2 = 1)
Permanent diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
-
D1
Channel LR (CH2)
No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
-
D0
Channel LR (CH2)
No short to GND (D1 = 0)
Short to GND (D1 = 1)
-
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36
Software specifications
TDA7569BDLVPD
Table 11. DB3
Bit
Instruction decoding bit
D7
Standby status (= IB2 - D4)
-
D6
Diagnostic status (= IB1 - D6)
-
D5
Channel RF (CH3)
Current detection IB2 (D7) = 0
Output peak current < 250 mA - Open load (D5 = 1)
Output peak current > 500 mA - Normal load (D5 = 0)
Channel RF (CH3)
Current detection IB2 (D7) = 1
Output peak current < 125 mA - Open load (D5 = 1)
Output peak current > 250 mA - Normal load (D5 = 0)
D4
Channel RF (CH3)
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
-
D3
Channel RF (CH3)
Normal load (D3 = 0)
Short load (D3 = 1)
-
D2
Channel RF (CH3)
Turn-on diag.: No open load (D2 = 0)
Open load detection (D2 = 1)
Permanent diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
-
D1
Channel RF (CH3)
No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
-
D0
Channel RF (CH3)
No short to GND (D1 = 0)
Short to GND (D1 = 1)
-
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DocID024174 Rev 6
TDA7569BDLVPD
Software specifications
Table 12. DB4
Bit
Instruction decoding bit
D7
Thermal warning 2 active (D7 = 1), Tj = 145°C
-
D6
Thermal warning 3 active (D6 = 1) Tj = 125°C
-
D5
Channel RR (CH4)
Current detection IB2 (D7) = 0
Output peak current < 250 mA - Open load (D5 = 1)
Output peak current > 500 mA - Normal load (D5 = 0)
Channel RR (CH4)
Current detection IB2 (D7) = 1
Output peak current < 125 mA - Open load (D5 = 1)
Output peak current > 250 mA - Normal load (D5 = 0)
D4
Channel RR (CH4)
Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
-
D3
Channel R (CH4)
R Normal load (D3 = 0)
Short load (D3 = 1)
-
D2
Channel RR (CH4)
Turn-on diag.: No open load (D2 = 0)
Open load detection (D2 = 1)
Permanent diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
-
D1
Channel RR (CH4)
No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
-
D0
Channel RR (CH4)
No short to GND (D1 = 0)
Short to GND (D1 = 1)
-
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36
Examples of bytes sequence
11
TDA7569BDLVPD
Examples of bytes sequence
1 - Turn-On diagnostic - Write operation
Start
Address byte with D0 = 0
ACK
IB1 with D6 = 1
ACK
IB2
ACK
STOP
2 - Turn-On diagnostic - Read operation
Start Address byte with D0 = 1 ACK
DB1 ACK
DB2 ACK DB3 ACK DB4 ACK STOP
The delay from 1 to 2 can be selected by software, starting from 1ms
3a - Turn-On of the power amplifier with 26 dB gain, mute on, diagnostic defeat, CD = 2%
.
Start
Address byte with D0 = 0
ACK
IB1
ACK
X0000000
IB2
ACK
STOP
ACK
STOP
ACK
STOP
XXX1XX11
3b - Turn-Off of the power amplifier
Start
Address byte with D0 = 0
ACK
IB1
ACK
X0XXXXXX
IB2
XXX0XXXX
4 - Offset detection procedure enable
Start
Address byte with D0 = 0
ACK
IB1
ACK
XX1XX11X
IB2
XXX1XXXX
5 - Offset detection procedure stop and reading operation (the results are valid only for the
offset detection bits (D2 of the bytes DB1, DB2, DB3, DB4)
.
Start Address byte with D0 = 1 ACK DB1 ACK
34/37
DB2 ACK
DB3 ACK DB4 ACK STOP
The purpose of this test is to check if a D.C. offset (2V typ.) is present on the outputs,
produced by input capacitor with anomalous leakage current or humidity between pins.
The delay from 4 to 5 can be selected by software, starting from 1ms
DocID024174 Rev 6
TDA7569BDLVPD
12
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 38. PowerSO36 (slug up) mechanical data and package dimensions
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DocID024174 Rev 6
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36
Revision history
13
TDA7569BDLVPD
Revision history
Table 13. Document revision history
36/37
Date
Revision
Changes
18-Jan-2013
1
Initial release.
25-Jan-2013
2
Updated Section 8.1: High efficiency introduction on page 26.
18-Sep-2013
3
Updated Disclaimer.
04-Oct-2013
4
Updated Table 5: Electrical characteristics.
Updated Section 9.3.4: Acknowledge on page 28.
12-Mar-2014
5
Updated Figure 2 note (*); Table 5: Electrical characteristics
(ΔVOITU parameter on page 11).
18-Sep-2014
6
Updated Section 9.1: I2C programming/reading sequences on
page 27.
DocID024174 Rev 6
TDA7569BDLVPD
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2014 STMicroelectronics – All rights reserved
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