TDA7572TR

TDA7572 200 W mono bridge PWM amplifier with built-in step-up converter Features ■ Input stage and gain compressor ■ Over-modulation protection and current limiting ■ Modulator ■ DAC ■ Step-up ■ Mode control ■ Diagnostics / safety ■ Power control HiQUAD-64 Broad operating voltage is supported, allowing operation from both 14 V and 42 V automotive power buses, as well as from split supplies for consumer electronics use. Description TDA7572 is a highly integrated, highly versatile, semi-custom IC switch mode audio amplifier. It integrates audio signal processing and power amplification tailored for standalone remote bass box applications, while providing versatility for full bandwidth operation in either automotive or consumer audio environments. It's configured as one full bridge channel, using two clocked PWM modulators driving external, complementary FET's. Table 1. A current mode control boost converter controller is provided to allow high power operation in a 14 V environment. Turn-on and turn-off transients are minimized by soft muting/unmuting and careful control of offsets within the IC. Digital Audio input is supported by an integrated one channel DAC. Sophisticated diagnostics and protection provide fault reporting via I2C and power shutdown for safety related faults. TDA7572 is packaged in a HiQUAD-64 package. Device summary Order code Package Packing TDA7572 HiQUAD-64 Tray September 2013 Doc ID 13875 Rev 2 1/64 www.st.com 1 Contents TDA7572 Contents 1 Detailed features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 5 6 Operating voltage and current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.2 Under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.3 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.4 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3.5 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3.6 Gate drive and output stage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3.7 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Voltage booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4.1 Digital to analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4.2 I/O pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4.3 Operational amplifier cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4.4 Shunt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4.5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I2C and mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 Input control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 Faults 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3 Faults 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.5 Modulator register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.6 Testing register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Input stage and gain compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 2/64 4.3.1 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Doc ID 13875 Rev 2 TDA7572 Contents 6.2 7 Gain compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.1 Setting in I2C bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.2 Soft-mute function, without pre-limiter . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 FET drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2 Anti-pop shunt driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9 Step-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.1 Faults during operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.1.1 DC offset across the speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.1.2 Die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1.3 External temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1.4 Output clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1.5 Output over-current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1.6 Power supply overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.1.7 Fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.1.8 Faults during power-up: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12 Under voltage lock out (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13 14 12.1 VSP-UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.2 V14 - UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.3 SVR - UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Start-up procedures, modulator turn-on after a tristate condition . . . 56 13.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.2 Tristate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 14.1 Single supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 14.2 Split supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Doc ID 13875 Rev 2 3/64 Contents TDA7572 14.3 THD+N step-up on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 15 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4/64 Doc ID 13875 Rev 2 TDA7572 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin list by argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating voltage and current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Gate drive and output stage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Voltage booster. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Digital to analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I/O pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Op. amp. cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Shunt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Analog operating characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power-up mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 I2C chip address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Example of write instruction with increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Example of read instruction with increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Input control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Faults 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Faults 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Modulator register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Testing register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Distortion versus gain step size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Sets the maximum release rate of the gain compressor. . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Sets the maximum attack rate of the gain compressor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Attack/release rate and gain compression effort selection . . . . . . . . . . . . . . . . . . . . . . . . . 39 PWMClock table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Doc ID 13875 Rev 2 5/64 List of figures TDA7572 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. 6/64 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mute by external command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Mute by I2C bus command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Modulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Current sourced by the shunt pin in NO I2C bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DAC circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Two interpolator structure diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I2S format diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Step-up application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Threshold of current limiting diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Single supply evaluation board schematic.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Single supply evaluation PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Split supply evaluation board schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Split supply evaluation PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 THD+N step-up on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 HiQUAD-64 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Doc ID 13875 Rev 2 TDA7572 1 Detailed features Detailed features ● ● Input Stage and Gain Compressor – Differential, high CMRR, analog input – Programmable input attenuation/gain to support up to four drive levels – Noiseless Gain compression of up to 16 dB with programmable attack and decay. – Compressor controlled by monitoring estimated THD – Soft mute / un-mute for pop control Over-modulation Protection and Current Limiting – Adaptive pulse injection prevents missing pulses due to over modulation which maximizes useful output swing. – ● ● ● ● ● Programmable current limiting based on FET VDS Modulator – Optimized for low distortion at low switching frequency (approximation 110 kHz) – Dual Clocked PWM modulators for 3 state switching – External gain control / internal integrator components – Controls 4 external FETS with switching optimized for low EMI – Oscillation frequency selectable by I2C – Anti-pop shunt driver DAC – 18bit, mono – I2S inputs 38-48 kHz, 96 kHz, 192 kHz – Hybrid architecture, area optimized for Bass – Full bandwidth supported by off loading the interpolator function – Synchronization with modulator Step-Up – On board STEP-UP step up converter, synchronized to the modulator frequency – Drives external NFET switch – Externally compensated – Soft start and current limiting Mode Control – Critical modes controllable by mode pins for bus-less operation – I2C provides additional mode control Diagnostics / Safety – Offset, short, open, overcurrent, over temperature – I2C used to report errors, and for configuration control – Faults pin used to report errors in bus-less environment – Clipping reported at a separate pin – Abnormal supply current detection disables input power for fail safe operation – Output current limiting – Power control – Latching control of an external PMOS power switch for safety related faults. – Power is switched off for safety related faults of abnormal supply current, excessive internal or external temperature, or persistent output stage over-current that fails to be controlled by the pulse-by-pulse current limiting method Doc ID 13875 Rev 2 7/64 Interface description 2 TDA7572 Interface description I2C bus and mode control pins are use to control operation. Default values of all the operating modes are deterministic, some of these values are intrinsic to the IC and some are determined by configurations pins. The configuration pins are read at power-up and copied into registers, which may later be modified using the I2C bus, if one is present. This allows varied operation in an environment where NO I2C bus is present, while allowing full control and override of pin programmed modes when used with I2C. MOD1 DACM DACP SCL / InputLevel1 PLL / InLevel0 WS / CLIP_L Regulators DC/DC Converter SDA / SCR_ENB DGND VDIG VM2.5 VP2.5 BSTVSource BSTVSense CSense BSTGate V14Sense Block diagram V14 Figure 1. LSD1SourceSensing LSD1GateDrive PWM Channel 1 DAC Pulse Inj . ISSENP ISSENM LSD1GateSensing +Vs current protection Integrator HB1OutFilter HB1Out Mode 0 Mode 1 Automute Voltage Setting ILimit threshold Mode sel . and Mute LOGIC Drivers Mute HSD1GateSensing HSD1GateDrive Prot. & supply HSD1SourceSensing Vs/2 or SVR VSP_Pow1 I2C data / attack sel. I2C clock I2Cbus HSD2SourceSensing PWM Channel 2 Addr 0 / Fault / CLIP_L UVLO HSD2GateDrive Pulse Inj . Addr1 / CompEnable NTC HSD2GateSensing Integrator Thermal management VSP_Pow2 HB2Out ShuntDrive TestC Diagnostics + clipdet LSD2OutFilter Diff -to-S.E. Compressor and Limiter Channel 1 Oscillators Drivers LSD2GateSensing -1 LSD2GateDrive Protections LSD2SourceSensing Iset 8/64 Doc ID 13875 Rev 2 VSM1,2,3,4 MOD2 InvOut InvIn AOUT INM INP OscOut DITH -sel CLKin -out Controls and Diagnostics AC00014 TDA7572 Pins description 64 63 62 61 60 59 VP2.5 Mode1 Mode0 AutoMuteVSetting MUTE_L VSM3 VSM4 ADDR1/CompEnable ADDR0/Fault/Clip_L I2CDATA/AttackSel I2CLK Pins connection (top view) IlimitThresh Figure 2. 58 57 56 55 54 53 Iset 1 52 SVR TestC 2 51 VM2.5 LSD2SS 3 50 VDIG LSD2GD 4 49 DGND LSD2GS 5 48 NTC HB2OutFilt 6 47 SCL/InLevel1 HB2Out 7 46 WS/Clip_L HSD2GS 8 45 SDA/SCR_ENB HSD2GD 9 44 PLL/InLevel10 10 43 ShuntDriver HSD2SS VSP_POW2 11 42 DITH VSP_POW1 12 41 CLKIN/Out HSD1SS 13 40 OscOut HSD1GD 14 39 MOD2 HSD1GS 15 38 MOD1 HB1Out 16 37 InvOut HB1OutFilt 17 36 InvIn LSD1GS 18 35 AOUT LSD1GD 19 34 INP LSD1SS 20 33 INM Doc ID 13875 Rev 2 DAC1 DAC2 ISSENP ISSENM VSM1 27 28 29 30 31 32 BSTVSense VSM2 V14 V14Sense CSense BSTGate 21 22 23 24 25 26 BSTSource 3 Pins description AC00013 9/64 Pins description Table 2. TDA7572 Pin list by argument Pin # Pin name Description 11 VSP_POW2 Positive supply power for low power, non gate-drive functions with a separate bonding to power the gate drive of modulator two 53 VP2.5 +2.5 V analog supply output 51 VM2.5 -2.5 V analog supply output 50 VDIG 5 V logic supply decoupling 49 DGND Digital gnd 52 SVR 55 Mode0 Mode control bit0, selects standby/normal/ I2C/diagnostic operation 54 Mode1 Mode control bit1, selects standby/normal/ I2C/diagnostic operation 57 MUTE_L 56 AutoMuteVSetting On/off circuitry Vs/2 analog reference filter capacitor. Reference for input stage. Mute input and / or timing cap, assertion level low Auto-mute voltage setting Input/gain compressor 34 INP Non inverting audio input 33 INM Inverting audio input 35 AOUT - - Input stage gain selection – see PLL pin in DAC Section 8 - - Compressor attack/decay select – see I2C data pin in DAC Section 8 Compressed audio output Inverter 36 InvIn 37 InvOut Inverter input Inverter output Modulator 64 IlimitThresh Output stage current limiting trip voltage set point 32 LVLSFT Gain program pin for SVR to HVCC level shifting 38 MOD1 20 LSD1SS Low-side1 Source Sensing 19 LSD1GD Low-side1 Gate Drive 18 LSD1GS Low-side1 Gate sense 17 HB1OutFilt 16 HB1Out Half-bridge1 output, HSD 1 drain sense, LSD1 Drain Sense 15 HSD1GS High-side1 Gate sense 14 HSD1GD High-side1 Gate Drive 13 HSD1SS High-side1 Source sense 12 VSP_POW1 10/64 Modulator1 Inverting / Summing node Half bridge1 post-LC filter – for diagnostics Positive supply voltage connection for gate drive circuitry Doc ID 13875 Rev 2 TDA7572 Table 2. Pins description Pin list by argument (continued) Pin # Pin name Description 39 MOD2 10 HSD2SS Highside2 Source sense 9 HSD2GD Highside2 Gate Drive 8 HSD2GS Highside2 Gate sense 7 HB2Out Half-bridge2 output, HSD 1 drain sense, LSD1 Drain Sense 6 HB2OutFilt 5 LSD2GS Lowside2 Gate sense 4 LSD2GD Lowside2 Gate Drive 3 LSD2SS Lowside2 Source Sense 27 VSM1 Die tab connection to lowest supply voltage – gnd for single ended supplies, negative supply for split supplies 26 VSM2 Die tab connection to lowest supply voltage – gnd for single ended supplies, negative supply for split supplies 58 VSM3 Die tab connection to lowest supply voltage – gnd for single ended supplies, negative supply for split supplies 59 VSM4 Die tab connection to lowest supply voltage – gnd for single ended supplies, negative supply for split supplies 43 ShuntDriver Shunt driver 28 BSTVSense Voltage feedback input for voltage booster 22 BSTSource Boost converter NFET source 21 BSTGate Boost converter NFET gate drive 23 CSense Inverting input for booster current sensing and digital test enable (operating when is more then about 3V under the V14 pin level) 24 V14Sense 25 V14 Modulator2 Inverting / Summing node Half bridge2 post-LC filter – for diagnostics DC-DC Non-inverting input for booster current sensing Power for boost converter gate drive and Output LSD’s Oscillator 41 CLKIN/Out Clock input 42 DITH Dither capacitor 40 OscOut Oscillator output Diagnostics / Bus 62 I2CDATA/AttackSel 63 I2CLK I2C data (I2C mode) Compressor aggressiveness selection (non-bus mode) I2C clock Doc ID 13875 Rev 2 11/64 Pins description Table 2. Pin # TDA7572 Pin list by argument (continued) Pin name Description I2 2 61 ADDR0/Fault/Clip_L C address set (I C mode) Fault output in non bus mode (non-bus mode) Clipping indicator, assertion level low, (when DAC is enabled) 60 ADDR1/CompEnable I2C address set (I2C mode) Compressor Enable/disable (non-bus mode) 48 NTC Connection for NTC thermistor 2 TestC Test cap used to generate the slow current pulses 1 ISet 30 ISSENP Supply non-inverting current sense 29 ISSENM Supply inverting current sense Program pin for current level used in Short/Open test DAC I2S Word select / Clipping indicator, assertion level low (non-DAC mode) 46 WS / Clip_L 45 SDA/SCR_ENB 47 SCL/ InLevel1 I2C serial data bit clock/ Input Level selection bit1 (non-DAC mode) 44 PLL/InLevel0 DAC clock PLL filter/ Input Level selection bit 0 (non-DAC mode) 31 DAC2 DAC output voltage p 32 DAC1 DAC output voltage n Table 3. I2C serial data / SCR ENABLE (non DAC mode) Pin list Pin # Pin name 1 Iset 2 TestC 3 LSD2SS Lowside2 source sense 4 LSD2GD Lowside2 Gate Drive 5 LSD2GS Lowside2 Gate sense 6 HB2OutFilt 7 HB2Out Half-bridge2 output, HSD 1 drain sense, LSD1 Drain Sense 8 HSD2GS Highside2 Gate sense 9 HSD2GD Highside2 Gate Drive 10 HSD2SS Highside2 Source sense 11 VSP_POW2 Positive supply power for low power, non gate-drive functions with a separate bonding to power the gate drive of modulator two 12 VSP_POW1 Positive supply voltage connection for gate drive circuitry 13 HSD1SS Highside1 Source sense 14 HSD1GD Highside1 Gate Drive 15 HSD1GS Highside1 Gate sense 12/64 Description Program pin for current level used in Short/Open test Test cap used to generate the slow current pulses Half bridge2 post-LC filter – for diagnostics Doc ID 13875 Rev 2 TDA7572 Table 3. Pins description Pin list (continued) Pin # Pin name Description 16 HB1Out 17 HB1OutFilt 18 LSD1GS Low-side1 Gate sense 19 LSD1GD Low-side1 Gate Drive 20 LSD1SS Low-side1 Source Sensing 21 BSTGate Boost Converter NFET gate drive 22 BSTSource 23 CSense 24 V14Sense 25 V14 26 VSM2 Die tab connection to lowest supply voltage – gnd for single ended supplies, negative supply for split supplies 27 VSM1 Die tab connection to lowest supply voltage – gnd for single ended supplies, negative supply for split supplies 28 BSTVSense 29 ISSENM Supply inverting current sense 30 ISSENP Supply non-inverting current sense 31 DAC2 Half VCC (VSP- VSM)/2 Used for output stage reference. 32 DAC1 Gain program pin for SVR to HVCC level shifting 33 INM Inverting audio input 34 INP Non inverting audio input 35 AOUT 36 InvIn 37 InvOut Inverter Output 38 MOD1 Modulator1 Inverting / Summing node 39 MOD2 Modulator2 Inverting / Summing node 40 OscOut Oscillator output 41 CLKIN/Out 42 DITH 43 ShuntDriver Shunt Driver 44 PLL/InLevel0 DAC clock PLL filter/ Input Level selection bit 0 (non-DAC mode) 45 SDA/SCR_ENB 46 WS / Clip_L 47 SCL/ InLevel1 48 NTC Half-bridge1 output, HSD 1 drain sense, LSD1 Drain Sense Half bridge1 post-LC filter – for diagnostics Boost Converter NFET Source Inverting input for Booster Current Sensing and Digital Test Enable (operating when is more then about 3V under the V14 pin level) Non-inverting input for Booster Current Sensing Power for Boost converter gate drive and Output LSD’s Voltage feedback input for Voltage Booster Compressed Audio Output Inverter input Clock input Dither capacitor I2C serial data / SCR ENABLE (non DAC mode) I2S Word select / Clipping indicator, assertion level low (non-DAC mode) I2C serial data bit clock/ Input Level selection bit1 (non-DAC mode) Connection for NTC thermistor Doc ID 13875 Rev 2 13/64 Pins description Table 3. TDA7572 Pin list (continued) Pin # Pin name 49 DGND GND logic supply decoupling 50 VDIG 5V logic supply decoupling 51 VM2.5 -2.5 V analog supply output 52 SVR 53 VP2.5 +2.5 V analog supply output 54 Mode1 Mode control bit1, selects standby/normal/I2C/diagnostic operation 55 Mode0 Mode control bit0, selects standby/normal/ I2C/diagnostic operation 56 AutoMuteVSetting 57 MUTE_L 58 VSM3 Die tab connection to lowest supply voltage – gnd for single ended supplies, negative supply for split supplies 59 VSM4 Die tab connection to lowest supply voltage – gnd for single ended supplies, negative supply for split supplies 60 ADDR1/CompEnable I2C address set (I2C mode) Compressor Enable/disable (non-bus mode) 61 ADDR0/Fault/Clip_L I2C address set (I2C mode) Fault output in non bus mode (non-bus mode) Clipping indicator, assertion level low, (when DAC is enabled) 62 I2CDATA/AttackSel 63 I2CLK 64 IlimitThresh 14/64 Description Vs/2 analog reference filter capacitor. Reference for input stage. Auto-Mute Voltage Setting Mute input and / or timing cap, assertion level low I2C data (I2C mode) Compressor aggressiveness selection (non-bus mode) I2C Clock Output stage Current Limiting trip voltage setpoint Doc ID 13875 Rev 2 TDA7572 Electrical specifications 4 Electrical specifications 4.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol VSP Parameters Test conditions Min. Max. Units VSM -0.6 VSM +58 V - 68 V VS—0.6 6V V Supply voltage - Vpeak Peak supply voltage (VS+ - VS-) time  50 ms VDATA Data pin voltage w.r.t Dgnd TJ Junction temperature - -40 150 C TStg Storage temperature - -55 150 C Power dissipation Any operating condition For thermal budgeting - 2.5 W PDMAX 4.2 Thermal data Table 5. Thermal data Symbol Rth j-case 4.3 Parameters Thermal resistance junction-to-case Value Units 3 °C/W Electrical characteristics Unless otherwise specified, all ratings below are for -40 °C < TJ < 125 °C, VSP = 42 V, VSM = 0V and the application circuit of Figure 12. Operation of the IC above this junction temperature will continue without audible artifacts until thermal shutdown, but these parameters are not guaranteed to be within the specifications below. FPWM =110 kHz, Booster not enabled. 4.3.1 Operating voltage and current Table 6. Operating voltage and current Symbol VSP42 VSP14 Parameters Test conditions Min. Typ. Max. 42 58 Operating voltage 42 V automotive range Normal operation without audible defects required Single ended supply 42 V configuration, VSM=0 30 Operating voltage 14.4 V automotive range Normal operation without audible defects required Single ended supply 14 V configuration, VSM=0 9 Doc ID 13875 Rev 2 Units V 14.4 - 15/64 Electrical specifications Table 6. Operating voltage and current (continued) Symbol VSPLIT TDA7572 Parameters Operating voltage VSP VSM split supply rails Test conditions Min. Typ. Max. Units 8 48 58 V - - 50 at T = 85 °C 10 at T = 25 °C A - 13 20 - 15 25 V14 - 15 - VSP - 20 - Normal operation required Split supply application configuration, VSMVSVR+4 Stand-by current IC in standby, Mode 0, and Mode 1 low Vs = 42 V Itristate Tristate current V14 Outputs tristated Booster not running, VSP Fpwm = nominal IMUTE Mute mode current Istdby MUTE asserted, 4.3.2 Under voltage lockout Table 7. Under voltage lockout Symbol mA Test conditions Min. Typ. Max. Units Voltage limit respect to the SVR pin Allowed voltage range on Automute pin 0.5 - 2.1 V Auto-mute supply voltage VSP Mute is forced if VSP-VSVR or VSVR-VSM is less than this value Vautomute VSetting-VSVR=VVSVR -15 % VVSVR* +15 % 7 V VPO- Auto-tristate supply voltage VSP negative slope The IC is set in tristate if VSP-VSM is less than this value Vautomute VSetting-VSVR=VVSVR -15 % VVSVR *12 +15 % V VPO+ Auto-tristate supply voltage VSP positive slope The IC is set out from tristate if VSP-VSM is higher than this value Vautomute VSetting-VSVR=VVSVR -15 % VVSVR *13 +15 % V VU The IC is set in tristate if VSP-VSM Auto-tristate supply is more than this value voltage VSP Relative maximum value Vautomute VSetting-VSVR=VVSVR -15 % VVSVR* +15 % 48 V VUC Auto-tristate supply voltage VSP Absolute maximum value The IC is set in tristate if VSP-VSM is higher than this value 60 63 66 V Auto-tristate supply voltage V14 negative slope The IC is kept in tristate if 14 V VSM become lower than this value 5.5 - 7 V VLimAM Parameters mA AutomuteVSetting pin voltage limit VSP UVLO VAM V14 – UVLO V14- 16/64 Doc ID 13875 Rev 2 TDA7572 Electrical specifications Table 7. Under voltage lockout (continued) Symbol Parameters Test conditions The IC is goes out from tristate if 14 V-VSM become higher than this value Min. Typ. Max. Units 6.5 - 8 V 0.8 - - V V14+ Auto-tristate supply voltage V14 positive slope V14h Auto-tristate 14V voltage Comparator hysteresis for autohysteresis tristate threshold V14su Step-up tristate The step-up is in tristate when voltage lower than this threshold 5 - 8 V V14mute- Auto-mute supply voltage V14 negative slope The IC goes in mute if 14 V-VSM become lower than this value V14+ 0.7 V - V14+ 1.2 V V V14mute+ Auto-mute supply voltage V14 positive slope The IC goes in play if 14 V-VSM become higher than this value V14V+ + 40 mV - V14V+ + 170 mV V Vsvr- Auto-tristate SVR voltage negative slope The IC is kept in tristate if VSvr VSM become less than this value Vautomute VSetting-VSVR=VVSVR -15 % 5.2 x VVSVR +15 % V Vsvr+ Auto-tristate SVR voltage positive slope The IC is goes out from tristate if VSvr - VSM become higher than this value Vautomute VSetting-VSVR=VVSVR -15 % 6 x VVSVR +15 % V VPOH Auto-tristate SVR voltage hysteresis Comparator hysteresis for autotristate threshold Vautomute VSetting-VSVR=VVSVR 0.40 x VVSVR - 1.2V x VVSVR V Test conditions Min. Typ. Max. Units INLEVEL1=0, INLEVEL0=0 -30% 22 +30% INLEVEL1=0, INLEVEL0=1 -30% 12 +30% INLEVEL1=1, INLEVEL0=0 -30% 24 +30% INLEVEL1=1, INLEVEL0=1 -30% 12 +30% INLEVEL1=0, INLEVEL0=0 -30% 17 +30% INLEVEL1=0, INLEVEL0=1 -30% 12 +30% INLEVEL1=1, INLEVEL0=0 -30% 17 +30% INLEVEL1=1, INLEVEL0=1 -30% 12 +30% SVR – UVLO 4.3.3 Input stage Table 8. Input stage Symbol Parameters Input differential amplifier/ gain attenuator RIN, No compress ion Input resistance RIN max compress ion k Doc ID 13875 Rev 2 17/64 Electrical specifications Table 8. TDA7572 Input stage (continued) Symbol Parameters VInMax Input clipping level Voltage level of the input that trespassed cause clipping in the preamplifier Test conditions Min. Typ. Max. Units INLEVEL1=0, INLEVEL0=0 2 - - VRMS INLEVEL1=0, INLEVEL0=1 7 - - VRMS INLEVEL1=1, INLEVEL0=0 2.6 - - VRMS INLEVEL1=1, INLEVEL0=1 9.5 - - VRMS AIN_0 (VAOUT-VSVR) / (VInP-VinM) INLEVEL1=0, INLEVEL0=0, no compression -4 -3 -2 dB AIN_2 (VAOUT- VSVR) / (VInP-VinM) INLEVEL1=0, INLEVEL0=1, no compression -15 -14 -13 dB AIN_1 (VAOUT- VSVR) / (VInP-VinM) INLEVEL1=1, INLEVEL0=0 no compression -6.3 -5.3 -4.3 dB AIN_3 (VAOUT- VSVR) / (VInP-VinM) INLEVEL1=1, INLEVEL0=1, no compression -17.6 -16.6 -15.6 dB Input stage gain VoutH AOUT output voltage swing With respect to SVR, 10 K loading to a buffered version of SVR 2 - - V VoutL AOUT output swing With respect to SVR, 10 K loading to a buffered version of SVR - - -2 V Vin=1 Vrms, f=20-20 kHz, INLEVEL1=0, INLEVEL0=0, no compression - 0.01 0.05 % Output slew rate Vin=1KHz square wave, 2 Vpp, INLEVEL1=0, INLEVEL0=0, no compression Time to transition from 10 % to 90 % - - 8 µs AOUT clip detector Duty cycle of the Clipping signal when there is 5 % distortion at the output of AOUT, f=1 kHz, RL =10 kohm 15 - 25 % Frequency response Vin=1Vrms, INLEVEL1=0, INLEVEL0=0 20 - - kHz Common mode rejection ratio VCM=1 VRMS @1 kHz CMRR= AVDIFF/AVCM INLEVEL1=0, INLEVEL0=0 No compressor 47 - - dB AOUTTHD THD - - f-3dB CMRR 18/64 Doc ID 13875 Rev 2 TDA7572 Table 8. Electrical specifications Input stage (continued) Symbol CG Parameters Test conditions Min. Typ. Max. Units VCM=1VRMS @1 kHz INLEVEL1=0, INLEVEL0=0 No compressor 51 - - dB VCM=1 VRMS @1 kHz INLEVEL1=1, INLEVEL0=0 No compressor 51 - - dB VCM=1 VRMS @1 kHz INLEVEL1=0, INLEVEL0=1 No compressor 51 - - dB VCM=1 VRMS @1 kHz INLEVEL1=1, INLEVEL0=1 No compressor 51 - - dB Common gain PSRR Power supply rejection, Vsp supply freq < 10 kHz 60 80 Voffset Output offset VOffset with respect to SVR Rin=100 ohms, Mute state -4 0 +4 mV Noise Noise at output of this stage f = 20-20 kHz, Rinput = 100 ohm A weighting - 7 10 µVRMS INLEVEL1 = 0, INLEVEL0 = 0 -21 -19 -17 INLEVEL1 = 0, INLEVEL0 = 1 -30 -28 -26 INLEVEL1 = 1, INLEVEL0 = 0 -25 -23 -21 INLEVEL1 = 1, INLEVEL0 = 1 -34 -32 -30 - INLEVEL1 = 0, INLEVEL0 = 0 0.5-0.25 0.5 0.5+ 0.25 - INLEVEL1 = 0, INLEVEL0 = 1 0.440.25 0.44 0.44+ 0.25 - INLEVEL1 = 1, INLEVEL0 = 0 0.550.25 0.55 0.55+ 0.25 - INLEVEL1 = 1, INLEVEL0 = 1 0.480.25 0.48 0.48+ 0.25 - Gain Change ZC comparator offset (in the diff. – S.E. block) offset Observed at AOUT pin ZC crossing must be detected within 50mV of the actual zero crossing, -80 - 80 mV - Gain Change ZC comparator offset (in the diff. – S.E. block) offset Observed at InvOut pin ZC crossing must be detected -220 - +220 mV Eno dB Gain compressor - Maximum attenuation dB Attenuation step size dB Doc ID 13875 Rev 2 19/64 Electrical specifications Table 8. TDA7572 Input stage (continued) Symbol Parameters Test conditions Min. Typ. Max. Units 90 - - dB Mute - Mute attenuation Mute pin voltage = Dgnd Vin=1 Vrms - Charge current Mute Pin Voltage(57) = 1.5 V -30% 100 +30% µA - Discharge current Mute Pin Voltage(57) = 1.5 V -30% 100 +30% µA - Mute threshold Maximum voltage where we must be in complete mute - - 1.5 V - Unmute threshold - 2.5 - - V - Mute to unmute transition voltage - 0.2 0.3 0.44 V - Vol IC in mute mode, FastMute=1 Iout=0 - - Digital GND + 0.1 V - Voh IC in unmute, Iout=0 - - V - Fast mute Resistance FASTMUTE =1 Vmutepin =1.5 V 550 680 Ohm 20/64 Doc ID 13875 Rev 2 VDIGITAL0.1 420 TDA7572 Electrical specifications 4.3.4 Oscillator Table 9. Oscillator Symbol Parameters Test conditions Min. Typ. Max. Units PWMCLOCK=[0 1] 100K 120 140K PWMCLOCK=[1 0] - FPWM_NOM *2 - PWMCLOCK=[0 0] - FPWM_NOM /2 - 48 50 52 % Internal oscillator FPWM_NOM Switching frequency kHz Duty cycle - VCLK_High Maximum voltage level Clock output high value Load = 20 kohm and 100 pF to buffered SVR VP25-0.1 - VP25 V VCLK_Low Minimum voltage level Clock output low value Load = 20 kohm and 100 pF to buffered SVR VM25-0.1 - VM25 V VCLK-P-P Peak-peak voltage Load = 20 kohm and 100 pF to SVR -10% 4.7 +10% V CLKDC - Dither cap charge current Dither pin voltage = 2.5 V ±30% 100 ±30% µA - Dither cap discharge current - ±30% 100 ±30% µA - Peak-peak dither voltage swing - 1.4 1.6 1.7 V - Dither external clock determination Voltage at the dither pin at to select external clock function VDIG-0.2 - - V - No dither Voltage at the dither pin at which no dither will occur - - VDGND +0.2 V - Peak FPWM increase due to dither Cdither = 100 nF +8 +10 +12 % - Peak FPWM decrease due Cdither = 100 nF to dither -8 -10 -12 % - Triangular peak value VGND+ 1V - VDIG1V - - Doc ID 13875 Rev 2 21/64 Electrical specifications 4.3.5 Modulator Table 10. Modulator Symbol TDA7572 Parameters Test conditions Min. Typ. Max. Units -2.5 - +2.5 mV Integrator operational amplifier Int_Voff Input offset voltage - Int_ibias Input bias current Guaranteed by design - - 500 nA Maximum duty cycle Vsp =1 4.4V - - 1.1 µs Min. Typ. Max. Units - - 1.75 0.080 V 7 9.2 - - V - - VSP-7 VSP-9.2 V VSP1.75 VSP0.080 - - V Toff 4.3.6 Gate drive and output stage control Table 11. Gate drive and output stage control Symbol Parameters Test conditions VOL_LSD LSG low voltage Isink = 0.5 A Isink = 20 mA VOH_LSD LSG high voltage Isource = 0.5 A Isource = 20 mA VOL_HSD HSG low voltage Isink = 0.5 A Isink = 20 mA Isource = 0.5 A VOH_HSD HSG high voltage Isource = 20 mA - HSG low Z drive tdelay After a commutation 2 - 10 µs - LSG low Z drive tdelay After a commutation 2 - 10 µs - HSG HiZ sink current VHSG=VSP t > 10 µs - - 150 mA - LSG HiZ source current VLSG=VSM, t > 10 µs - - 150 mA 0.3 - 1.1 V Overcurrent sensing IlimThresh Range of Ilim Trthresh - Vilim Engagement of the current limiting VlimitTreshold = 1 V w.r.t. VM2p5 Vlim* 3.0 - Vlim* 5.0 V Vitrip Start of cycle by cycle current limiting -15% Vlim * 6.0 +15% V Vilim Anti-shoo through PVGS_ON PFET gate voltage that will block NFET enhancement -2.5 - - V PVGS_OFF PFET gate voltage that will allow NFET enhancement - - -3.5 V 22/64 Doc ID 13875 Rev 2 TDA7572 Table 11. Electrical specifications Gate drive and output stage control (continued) Symbol Parameters Test conditions Min. Typ. Max. Units NVGS_ON NFET gate voltage that will block PFET enhancement 2.5 - - V NVGS_OFF NFET gate voltage that will allow PFET enhancement - - 3.5 V Min. Typ. Max. -15 % 2.45/ (3*Riset) +15 % -15 % 15 +15 % 4.3.7 Diagnostics Table 12. Diagnostics Symbol Parameters Test conditions Units Turn-on diagnostics/ Power-up diagnostics ITEST Test current for short/open Ri set = 56ohm mA RISET allowed range - 5.6 - - ohm Short threshold to lower supply rail - - - -Vs +1 V Normal operation thresholds - -Vs+2 - -Vs+5.5 V - Short to supply - -Vs+8 - - V - Shorted load - - 6 mV - Normal load - 0.025 - 1 V - Open load - 2 - - V - Test charge current - -30 % 10 µA +30 % µA Test time - 60 80 100 ms VLSSHRT VNOP tTEST Permanent diagnostics VoffACT DC offset detected - ±3 - - V VoffACT DC offset not detected, normal operation allowed - - - ±1.2 V Temperature TWARN Chip thermal warning - 135 150 165 °C TWH Chip thermal warning hysteresis - 3 5 7 - TSH Chip thermal shutdown - 155 160 175 °C Shutdown hysteresis - 3 5 7 °C TEW External thermal warning - -10 % VDIG *.4 +10 % V TEWH External thermal warning hysteresis - Vdig*0.0 30 - Vdig*0. 044 V - Doc ID 13875 Rev 2 23/64 Electrical specifications Table 12. TDA7572 Diagnostics (continued) Symbol Parameters Test conditions Min. Typ. Max. Units TES External thermal shutdown - -15 % VDIG *0.36 +15 % V TESH External thermal shutdown hysteresis Vdig* 0.032 - Vdig* 0.046 V Supply current sense VSSenT Supply sense trip voltage - 16 20 25 mV - AOUT levels that allow sensing of supply current - - - 3 V - Duration of AOUT under threshold to allow supply current sensing - -25 % 80 +25 % ms Issenp Input bias current - 200 - 700 µA IssenM Input bias current - -500 - 500 nA Min. Typ. Max. Units 4.4 Voltage booster Table 13. Voltage booster Symbol Parameters Test conditions Current mode control topology BSTDCMAX Max duty cycle - - - 88 % BSTDCMIN Min duty cycle - 0 - - % Vref - -8 % 2.5 +8 % V - -200 - 200 nA BSTREF IBIASBSTREF Vsense input bias current VSENSE_UL Vsense pin allowed voltage range - -0.6 - 58 V BSTVGain Voltage-error gain Duty cycle/BSTVSense - 0.4 0.8 1.2 % D.C. per mV - 55 - 65 % D.C. BSTDCNOM Nominal duty cycle Csense_UL Csense pin allowed voltage range - -0.6 - 58 V Csense gain Csense gain Duty cycle / Csense - 0.120 - 0.350 % D.C. per mV CsenseTrip limit trip point - 0.220 - 0.440 V Soft-start step period not yet tested (to be confirmed) - - 3 - ms Soft start steps - - 16 - - TSS - 24/64 Doc ID 13875 Rev 2 TDA7572 Table 13. Symbol Electrical specifications Voltage booster (continued) Parameters Test conditions VOH_BST BST gate high voltage Isource = 0.5 A Isource = 20 mA VOL_BST BST gate low voltage Isink = 0.5 A Isink = 20 mA 4.4.1 Digital to analog converter Table 14. Digital to analog converter Symbol Parameters Test conditions Min. Typ. Max. Units 7 9.2 - - V - - 1.75 V 0.080 V Min. Typ. Max. Units 80 90 - dB - Dynamic range at -60 dBFS At output of analog filter -60dBFS input 1KHz sine tone - Noise floor At output of analog filter after > 25 ms of –97dBFS input 20-20 kHz flat - - 20 µV - THD+N at maximum useful input level Input = -1.5 dBFS The DAC output is limited to prevent operation in regions of degraded DAC performance. This spec represents the performance at this maximum practical value - - -60 dB - Silent Mute Must engage after 25 mS of 3Vfor more then 100ms the Offset bit in register Faults2 is set and the external FET's are tristated. The bit is cleared using the W1TC procedure. Resetting the bit removes the tristate mode and modulator operation is restored No I2C bus: Operation is as above except the fault is also reported by asserting the Address0/Fault_L pin. In order to restart the system is necessary to pass through standby mode. 48/64 Doc ID 13875 Rev 2 TDA7572 10.1.2 10.1.3 10.1.4 10.1.5 Diagnostics Die temperature ● I2C bus: The Twarn bit in register Faults2 bus register is set when the first threshold is exceeded. If the second threshold is exceeded the SCR is enabled (only if the PassFETctrl bit is set to one) which allows the external power switch to latch off, and can only be restarted by removing and reapplying power. Twarn is cleared using the W1TC procedure. ● No I2C bus: Operates as above, except the non-latched version (real-time version) of the Twarn bit is reported on the Address0/Fault_L pin. The value of PassFETctrl is determined by the SDA/SCR_Enb pin, which is read at power-up. External temperature ● I2C bus: The ExtTwarn bit is set if the voltage at the NTC pin exceeds the first threshold. If the second threshold is exceeded the SCR is enabled (only if the PassFETctrl register is set to one). ExtTwarn is cleared by the W1TC procedure ● No I2C bus: Operates as above, except the non-latched version (real-time version) of ExtTwarn register is reported on the Address0/Fault pin. The value of PassFETctrl bit is determined by the SDA/SCR_Enb pin, which is read at power-up Output clipping ● I2C bus: The Clip bit in the Faults2 register is set when the clipping detected. The Clip bit is cleared by the W1TC procedure. Clipping is detected if there is maximum modulation or over current control at the modulator, or if the AOUT pin clips. ● No I2C bus: The instantaneous value of clipping, as defined above, is reported on the SCL/CLIP_L pin. The pin is pulled low during a clipping event (assertion level low). ● DAC Enabled: To handle the case when the DAC is in use and to meet the requirement of a physical clipping signal, the clipping signal is brought out to the Addr0/Fault pin Output over-current ● I2C bus: The output current is clipped/limited by pulse injection into the modulator when the qualified VDS of the active FET exceeds the first threshold, at the same time the IoutTrip bit is set. If the second threshold is exceeded the current is cycle-by-cycle limited by switching the FET's off after few microsecond. If the cycle-to-cycle limitation is present for more then 4 cycle the SCR is enabled (only if the PassFETctrl register is set to one) and the external FET are tristated. In case of the SCR is disabled the external FET are not tristated and the limitation still going. The register is cleared by the W1TC procedure. ● No I2C bus: In addition to the above, the clipping out pin is engaged by the current limitation. The value of PassFETctrl bit is determined by the SDA/SCR_Enb pin, which is read at power-up Doc ID 13875 Rev 2 49/64 Diagnostics 10.1.6 10.1.7 TDA7572 Power supply overcurrent ● I2C bus: The bit IsenTrip is set when the voltage between the ISSENP and ISSENM pins exceeds the threshold. Also, the power control SCR is turned on (only if the PassFETctrl register is set to one). IsenTrip is cleared by the W1TC procedure. ● No I2C bus: In addition the above, the non-latched version of IsenTrip register is reported on the Address0/Fault_L pin. The value of PassFETctrl bit is determined by the SDA/SCR_Enb pin, which is read at power-up: ● NOTE: The Output current is monitored only when the output signal is in the +/-1.2V (see offset detector specification) range for more then 100ms. When this condition is reached a switch present between ISSENM and ISSENP is switched off. Normally this switch shorts the ISSENM pin to the ISSENP, allowing external filter caps to used to condition the current sense signal. Fault handling Table 34. Fault handling Fault 1st Threshold (Bus mode: I2C/No I2C) 2nd Threshold – Latch the offset bit – Tristate the modulator DC offset – Latch the offset bit and Fault pin – Tristate the modulator – Latch the Twarn bit Die temperature Output clipping – Latch the Twarn bit – Assert the fault pin – Latch the Clip bit – Assert the SCL_CLIP_L (if no DAC) – Assert the Address0 (if DAC) The SCR is activated if enabled - – Latch the Clip bit – Assert SCL_CLIP_L – Latch the IsenTrip bit – Clip the output current by modulator injection Output overcurrent – Latch the IsenTrip bit – Clip the output current by modulator injection Cycle-to-cycle Current limiting is activated. If the cycle-by-cycle limitation is present for more then four PWM cycles the SCR is activated if the SCR is enabled and the output FET are tristated. If the SCR is disabled the cycle-by cycle limitation keep going. – Latch the IoutTrip bit – The SCR is activated if enabled Power supply overcurrent Note: 50/64 – Latch the IoutTrip bit – Assert the Fault pin – The SCR is activated if enabled - in legacy mode (no I2C bus) the Output over-current warning information is not reported on the fault pin, while is present on the clipping detector output pin. Doc ID 13875 Rev 2 TDA7572 Diagnostics Events that put in tri-state the Modulator: – Diagnostic on – Offset detection – Output over-current second threshold trespassed Events that enable the Fault Pin without I2C bus: – Diagnostic Fault – Junction thermal warning – External thermal warning – Supply current over-threshold – Offset detection Events that enable the SCR: 10.1.8 – Over-temperature protection – Output over-current second threshold trespassed – Supply current over-threshold Faults during power-up: This is a power-up diagnostic useful to detect: load short to ground, load short to supply, short across the transducer, open transducer. The PUD could be performed with and without I2C bus. ● I2C bus: setting the bit 4 of Fault1 register the diagnostic begin. The capacitor TestC is then charged by a thevenin circuits with R = 155 k and supply equal to 1.75 V. The value of capacitor is choose in order to have an audible charge ramp and at the same time in order to have an acceptable charge time. The diagnostic time start when the TestC pin reaches the 98 % of full charge. During the diagnostic time of 100 ms a current equal to 2.45 I = ----------------------3  RISet The drop across the load produced by this current is continuously monitored. A fault is detected if the drop and/or the absolute value of pin HB1Out and HB2Out are abnormal for the full 100 ms period set when a fault is detected the correspondent bit in the Fault1 register is set and the diagnostic keep running until the fault is present. In case no fault is detected after the 100 ms period the capacitor is discharged and the current on the load is reduced down to zero. When this current is at the 2 % of is nominal value the bit 4 of Fault1 register is set to zero. Pulling this register the operator could understand the state of diagnostic. Note that during diagnostic cycle the output FET are in tristate. ● No I2C bus: The operation of diagnostic is equal to the one with I2C bus. The only differences are about the habilitation, which is selected by the mode, and the assertion of fault presence, which is done trough the addr0/Fault pin. At the end of diagnostic the Fault pin is for sure low and the external FET start to commute. These are the thresholds to take into account for short to ground and short to supply: Voltage threshold SGND VSM VSM+1V Normal operation X VSM+2V Doc ID 13875 Rev 2 VSM+5.5V X SVCC VSM+8V VSP 51/64 Diagnostics TDA7572 These are instead the thresholds to take into account for the short and open transducers with some example with a predefined current: - 52/64 SL X Normal load X OL Voltage threshold - 6 mV 20 mV 1 2 - Itest = 14 mA - 0.4  1.43  71  143  - Itest = 140 mA - 0.04  0.14  7.1  14.3  - Doc ID 13875 Rev 2 TDA7572 11 Oscillator Oscillator A common clock is needed to run all switching blocks at one frequency to avoid beating. The internally generated clock is used for the PWM modulators and to run the dc-dc converter. To blur the EMI spectrum, sub-audible frequency dither incorporated. ● When the DITH-sel pin is logic gnd then the internal oscillator operates without dither. ● With a cap there is ±100UA dithering functions ● Putting DITH-sel to VDIG allows an external clock to be accepted from CLKin-out at 4X the selected frequency ● Clock out is referred to VP2.5 and VM2.5, while external clock input is referred to DGND and VDIG ● External CLKin-out is always active. When DITH-sel is different to VDIG on this pin is present a 4X modulator frequency at digital level. The dither acts to span the intermodulation products present around multiple of switching frequency. Dither the modulator frequency means make it slowly changing around a nominal value. In case of a capacitor is connected to the DITH-sel pin a triangular drop is present across it and the modulator frequency value follows these behave. The maximum value reaches by it is the nominal value plus 10 %, while the minimum value is nominal one minus 10 %. This pick frequency values are reached when the DITH-sel pin reach the maximum voltage value. The value of capacitor is involved in the ratio of variation of modulator frequency, provided that it acts on triangular wave frequency. In case of DAC operation the modulator frequency of PWM digital out of this component is lock to the I2S input frequency, which is different from the analog modulator frequency imposed by the described oscillator. No high value intermodulation product are generated by difference of this frequency because the presence of filter between DAC out and Diff-toSE input. However a multiple frequency of DAC could be imposed to analog modulator by the CLKin-out pin. In this case no dither can be introduced. Doc ID 13875 Rev 2 53/64 Under voltage lock out (UVLO) 12 TDA7572 Under voltage lock out (UVLO) The UVLO lock at the voltage references value used to run the device. If some of them are not in the rate band the system is put in tristate or in standby. The Auto-mute Voltage Setting pin (pin56) voltage is used to define the limits of this voltage references. List of monitored pin: 1. MODE0 and MODE1 voltage value 2. VSP-VSM voltage difference 3. SVR voltage value 4. VSP-SVR or VSR-VSM voltage difference 5. V14 voltage value In the UVLO could be defined four blocks: 12.1 – VSP - UVLO – VP2.5/VM2.5 UVLO – V14 - UVLO – SVR - UVLO VSP-UVLO This block monitors the VSP-VSM drop and eventually moves the modulator in mute or in tristate. The limits imposed by the VSP-UVLO block are principally three: 1. an adjustable limit on the minimum supply/drop 2. an adjustable limit on the maximum supply/drop 3. an absolute limit on the maximum supply The adjustable limits are obtained by means of the reference voltage present on the AutomuteVSetting pin, which is fixed by means of a ladder resistor of R1 and R2 between VP2.5 and SVR. The comparators that sense the voltage drop for the auto mute are provided of hysteresis. An hysteresis is still present for the auto-tristate and expressed in the spec as two different thresholds that are function of reference voltage and slope polarity. 12.2 V14 - UVLO This block monitors the V14-VSM drop voltage and eventually moves the modulator in mute or in tristate. The V14-UVLO block fixes a limit on the minimum drop. An hysteresis is present for the auto-tristate and expressed in the spec as two different thresholds that are function of slope polarity. An hysteresis is still present for the auto-mute and expressed in the spec as two different thresholds that are function of auto-tristate threshold and slope polarity. 54/64 Doc ID 13875 Rev 2 TDA7572 12.3 Under voltage lock out (UVLO) SVR - UVLO This block monitors the SVR-VSM drop voltage and eventually moves the modulator in tristate. The SVR-UVLO block fixes a limit on the minimum drop. An hysteresis is present for the auto-tristate and expressed in the spec as two different thresholds that are function of slope polarity. An hysteresis is still present for the auto-mute and expressed in the spec as two different thresholds that are function of auto-tristate threshold and slope polarity. Doc ID 13875 Rev 2 55/64 Start-up procedures, modulator turn-on after a tristate condition 13 Start-up procedures, modulator turn-on after a tristate condition 13.1 Start-up TDA7572 Condition to be respected to turn-on the modulator at the start-up: ● Are MODE0 and/or MODE1 pins at voltage higher than 2.3V? ● Is the command “TristateMOD” Set to “1”? ● Is the PLL locked? (Only in case of digital Input) ● Is the Thermal protection FLAG ON? ● Are the VSP-VP2.5 and VM2.5-VSM drop voltage respectively over VAP and VAM? ● Is the VSP-VSM voltage lower than VU and VUC? ● Is the total VSP-VSM Higher than VPO+? ● Is the SVR pin higher than Vsvr+? ● Is the 14V pin supply higher than V14mute+? TristateMOD represents an internal signal which is – in NO I2C bus mode set to '1' when the digital supply pin VDIG (50) reaches its steady state value. – in I2C mode set to '1' when the digital supply pin VDIG (50) reaches its steady state value and by I2C bus is written '1' on the D4 bit of modulator register. – in NO I2C DIAGNOSTIC set to '1' when the digital supply pin VDIG (50) reaches its steady state value and the turn-on diagnostic has positive result. The thermal protection represent an internal signal which is set to '1' at the start-up and eventually set to '0' if – the internal temperature trespass the second threshold and/or – the external temperature trespass the second threshold Once all the listed condition present in the above table are respected the modulator is get out from tri-state after ~500 µs. 13.2 Tristate When the modulator is put in tristate by some diagnostic condition the system retrieve from this condition in two possible mode depending from the supplies configuration 56/64 – split supply: The modulator starts to switch ~500 µs after all conditions listed in the above table are realized. – Single-supply: Only in case of single supply, is activated a circuit that inhibit the startup of the SVR capacitor charge (then the modulator enable) if the SVR voltage is higher than 1.5 V. If, during the normal activity of the modulator, an event that moves the modulator in tristate is present (due to, as example, an UVLO) the Vsvr gets to discharge until its value is under 1.5V. Ones reached this value the capacitor SVR start to charge. The modulator starts to switch ~500 µs after all conditions listed in the above table are realized. Purpose of this circuit is to avoid fast turn-off/on of the modulator and increase the pop performance. Doc ID 13875 Rev 2 TDA7572 Applications 14 Applications 14.1 Single supply AC00110 Figure 12. Single supply evaluation board schematic. Doc ID 13875 Rev 2 57/64 Applications TDA7572 Figure 13. Single supply evaluation PCB AC00111 Top layer and component layout AC00112 Bottom layer 58/64 Doc ID 13875 Rev 2 TDA7572 Split supply Figure 14. Split supply evaluation board schematic. AC00113 14.2 Applications Doc ID 13875 Rev 2 59/64 Applications TDA7572 Figure 15. Split supply evaluation PCB AC00114 Top layer and component layout AC00115 Bottom layer 60/64 Doc ID 13875 Rev 2 TDA7572 14.3 Applications THD+N step-up on The graph below report the THD+N vs. Pout of a TDA7572 board with step-up on and 50 Hz input sine wave. Condition and step to made the board working are: 1. connect a voltage supplier to the connector J1: Positive terminal (max 14V) connected to L14V, ground terminal connected to -Vs. 2. connect the differential input signal on INP and INM BNC input or connect the single ended input on the INP BNC and short cut the INM BNC. 3. connect the load of 4  to the connector J2. 4. turn-on the device by means of MODE0 switch. 5. put in play the device by operating on MUTE switch Figure 16. THD+N step-up on Doc ID 13875 Rev 2 61/64 Package information 15 TDA7572 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 17. HiQUAD-64 mechanical data and package dimensions mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 0.124 A1 0 0.25 0 0.010 A2 2.50 2.90 0.10 0.114 A3 0 0.10 0 0.004 b 0.22 0.38 0.008 0.015 0.012 c 0.23 0.32 0.009 D 17.00 17.40 0.669 14.00 14.10 0.547 0.551 2.80 2.95 0.104 0.110 17.40 0.669 14.10 0.547 D1 (1) 13.90 D2 2.65 E 17.00 E1 (1) 13.90 e 14.00 0.65 0.685 0.555 0.116 0.685 0.551 0.555 0.025 E2 2.35 2.65 0.092 E3 9.30 9.50 9.70 0.366 0.374 0.382 E4 13.30 13.50 13.70 0.523 0.531 0.539 0.104 F 0.12 0.005 G 0.10 0.004 L 0.80 OUTLINE AND MECHANICAL DATA MAX. 3.15 1.10 0.031 N 10 (max.) S 0 (min.), 7 (max.) 0.043 HiQUAD-64 (1): "D1" and "E1" do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15 mm (0.006 inch) N E2 A2 A c A b BOTTOM VIEW ⊕ F M A B 33 53 E3 D2 (slug tail width) e B E1 E3 E Gauge Plane slug (bottom side) C 0.35 A3 S SEATING PLANE L 21 64 G C COPLANARITY 1 E4 (slug lenght) A1 D1 D 0102576 E 62/64 Doc ID 13875 Rev 2 TDA7572 16 Revision history Revision history Table 35. Document revision history Date Revision Changes 3-Sep-2007 1 Initial release. 17-Sep-2013 2 Updated Disclaimer. Doc ID 13875 Rev 2 63/64 TDA7572 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 64/64 Doc ID 13875 Rev 2