TDA7580

TDA7580 FM/AM digital IF sampling processor Features ■ FM/AM IF sampling DSP ■ ON-CHIP analogue to digital converter for 10.7MHz IF signal conversion ■ FM channel equalization ■ FM adjacent channel suppression ■ Reception enhancement in multipath condition ■ Stereo decoder and weak signal processing ■ 2 Channel serial audio interface (SAI) with sample rate converter ■ I2C and buffer SPI control interfaces ■ RDS filter, demodulator & decoder ■ Inter processor transport interface for antenna and tuner diversity ■ Front-end AGC feedback Description The TDA7580 is an integrated circuit implementing an advanced mixed analogue and digital solution, to perform the signal processing Table 1. u d o Device summary r P e Part number TDA7580 t e l o TDA758013TR ) s ( ct LQFP64 c u d e t le ) s t( o r P of an AM/FM channel. The HW & SW architecture has been devised to perform a digital equalization of the FM/AM channel, and a real rejection of adjacent channels and any other signals, interfering with the listening of the desired station. In severe multiple path conditions, the reception is improved to get high quality audio. o s b O Package Packing LQFP64 Tube LQFP64 Tape and reel s b O March 2007 Rev 5 1/39 www.st.com 1 Contents TDA7580 Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Block diagram and electrical specifications . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 SAI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 RDS SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 BSPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 Inter processor transport interface for antenna diversity . . . . . . . . . . 26 7 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 c u d e t le 8.2 DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3 Clock generation unit (CGU) and oscillator . . . . . . . . . . . . . . . . . . . . . . . 29 8.4 Stereo decoder (HWSTER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.5 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.6 I2C interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ) s ( ct 8.9 u d o r P e t e l o 2/39 o s b O - 24 bit DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.8 9 o r P 8.1 8.7 s b O ) s t( Serial peripheral interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 High speed serial synchronous interface (HS3I) . . . . . . . . . . . . . . . . . . . 31 Tuner AGC keying DAC (KEYDAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.10 Asynchronous sample rate converter (ASRC) . . . . . . . . . . . . . . . . . . . . . 31 8.11 IF band pass Σ Δ analogue to digital converter (IFADC) . . . . . . . . . . . . . 31 8.12 Digital down converter (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.13 RDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.14 AM/FM Detector (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TDA7580 Contents 9.1 Electrical application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 3/39 List of tables TDA7580 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended DC operating conditions (Tj = -40°C to 125°C) . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Low voltage interface CMOS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 15 High voltage CMOS interface DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15 Current consumption (Tj =-40°C to 125°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Crystal characteristics for 1 and 2 chip load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 External clock signal on XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DSP core (Tj =-40°C to 125°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 FM stereo decoder characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sample rate converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI and I2C timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SAI Timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 RDS SPI timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 BSPI timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 HS3I timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I2C BUS timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 c u d e t le ) s ( ct u d o r P e t e l o s b O 4/39 o s b O - o r P ) s t( TDA7580 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PIN connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power on and boot sequence using I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power on and boot sequence using SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SAI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SAI protocol (when: RLRS=0; RREL=0; RCKP=1; RDIR=0) . . . . . . . . . . . . . . . . . . . . . . . 20 SAI protocol (when: RLRS=1; RREL=0; RCKP=1; RDIR=1) . . . . . . . . . . . . . . . . . . . . . . . 21 SAI protocol (when: RLRS=0; RREL=0; RCKP=0; RDIR=0) . . . . . . . . . . . . . . . . . . . . . . . 21 SAI protocol (when: RLRS=0; RREL=1; RCKP=1; RDIR=0) . . . . . . . . . . . . . . . . . . . . . . . 21 RDS SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 RDS SPI clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 BSPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 BSPI clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 High speed synchronous serial interface - HS3I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 HS3I clocking scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DSP and RDS I2C BUS timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Radio mode with external slave audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Radio mode with external master audio device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Audio mode with external slave audio device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Application diagram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Mechanical, data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 5/39 Overview 1 TDA7580 Overview The algorithm is self-adaptive, thus it requires no “on-the-field” adjustments after the parameters optimization. The chip embeds a Band Pass Sigma Delta Analogue to Digital Converter for 10.7MHz IF conversion from a “tuner device” (the TDA7515 is highly recommended). The 24bit DSP allows flexibility in the algorithms implementation, thus giving some freedom for customer required features. The total processing power offers a significant headroom for customer’s software requirement, even when the channel equalization and the decoding software is running. the program and data memory space can be loaded from an external non volatile memory via I2C or SPI. The oscillator module works with an external 74.1MHz quartz crystal. It has very low electro magnetic interference, as it introduces very low distortion, and in any case harmonics fall outside the radio bandwidth. ) s t( The companion tuner device receives the reference clock through a differential ended interface, which works off the oscillator module by properly dividing down the master clock frequency. That allows the overall system saving an additional crystal for the tuner. c u d After the IF conversion, the digitized baseband signal passes through the base band processing section, either FM or AM, depending on the listener selection. The FM base band processing comprises of stereo decoder, spike detection and noise blanking. The AM noise blanking is fully software implemented. e t le o r P The internal RDS filter, demodulator and decoder features complete functions to have the output data available through either I2C or SPI interface. No DSP support is needed but at start-up, so that RDS can work in background and in parallel with other DSP processing. This mode (RDS only) allows current consumption saving for low power application modes. o s b O - An I2C/SPI interface is available for any control and communication with the main micro, as well as RDS data interface. The DSP SPI block embeds a 10 words FIFO for both transmit and receive channels, to lighten the DSP task and frequently respond to the interrupt from the control interface. ) s ( ct Serial audio interface (SAI) is the ideal solution for the audio data transfer, both transmit and receive: either master or slave. The flexibility of this module gives a wide choice of different protocols, including I2S. Two fully independent bidirectional data channels, with separate clocks allows the use of TDA7580 as general purpose digital audio processor. u d o r P e A fully asynchronous sample rate converter (ASRC) is available as a peripheral prior to sending audio data out via the SAI, so that internal audio sampling rate (~36kHz and FM/AM mode) can be adapted by upconversion to any external rate. t e l o bs O An inter processor transport interface (HS3I, high speed synchronous serial interface) is also available for a modular system which implements Dual Tuner Diversity, thus enhancing the overall system performance. It is about a synchronous serial interface which exchanges data up to the MPX rate. It has been designed to reduce the electro magnetic interference toward the sensitive analogue signal from the tuner. General purpose I/O registers are connected to and controlled by the DSP, by means of memory map. A debug and test interface is available for on chip software debug as well as for internal registers read/write operation. 6/39 TDA7580 2 Block diagram and electrical specifications Block diagram and electrical specifications Figure 1. Block diagram RDS A/D I2C/SPI I2C/SPI HS3I IF digital SAI1 Signal processor DAC SAI0 CGU SRC c u d Oscillator Table 2. Symbol VDD VDD3 e t le Absolute maximum ratings Parameter Power supplies (1) so b O - o r P Nom. 1.8V Nom. 3.3V Analog input or output voltage belonging to 3.3V IO ring (VDDSD, VDDOSC) ) s ( ct Tstg s b O Unit -0.5 to 2.5 -0.5 to 4.0 V V -0.5 to 4.0 V Normal(2) Failsafe(3) -0.5 to 6.50 -0.5 to 3.80 V V All remaining digital input or output voltage Nom. 1.8V Nom. 3.3V -0.5 to (VDD+0.5) -0.5 to (VDD3+0.5) V Operating junction temperature range -40 to 125 °C Storage temperature -55 to 150 °C r P e t e l o Value Digital input or output voltage, 5V tolerant u d o Tj ) s t( 1. VDD3 refers to all of the nominal 3.3V power supplies (VDDH, VOSC, VDDSD). VDD refers to all of the nominal 1.8V power supplies (VDD, VMTR). 2. During Normal Mode operation VDD3 is always available as specified. 3. During Fail-safe Mode operation VDD3 may be not available. Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7/39 Block diagram and electrical specifications Table 3. TDA7580 Recommended DC operating conditions (Tj = -40°C to 125°C) Symbol Parameter Comment Min. Typ. Max. Unit VDD 1.8V Power supply voltage Core power supply 1.7 1.80 1.9 V VDDH 3.3V Power supply voltage (1) IO Rings power supply (with GNDH) 3.15 3.30 3.45 V VOSC 3.3V Power supply voltage (1) Oscillator power supply (GNDOSC) 3.15 3.30 3.45 V VDDSD 3.3V Power supply voltage (1) IF ADC power supply (with GNDSD) 3.15 3.30 3.45 V VMTR 1.8V Power supply voltage DAC keying and tuner clock power supply (with GNDMTR) 1.7 1.80 1.9 V 1. VDDH, VOSC, VDDSD are also indicated in this document as VDD3. All others as VDD. Table 4. Thermal data Symbol Rth j-amb Parameter Value Thermal resistance junction to ambient 68 e t le ) s ( ct u d o r P e t e l o s b O 8/39 o s b O - o r P c u d ) s t( Unit °C/W TDA7580 Pin description GND VDD DBOUT1 DBRQ1 DBIN1 DBCK1 VDDH GNDH DBOUT0 DBRQ0 DBIN0 DBCK0 59 58 57 56 55 54 53 52 51 50 49 VDD 46 TST3_LRCKR 45 TST2_SCKR 44 LRCK_LRCKT 6 43 SCLK_SCKT GNDSD 7 42 SDO0 GNDOSC 8 41 VDDH XTI 9 40 GNDH XTO 10 39 TST1_SDI1 VDDOSC 11 38 TST4_SDI0 VDDMTR 12 37 GPIO_SDO1 CKREFP 13 36 TESTN CKREFN 14 35 GND AGCKEY 15 34 VDD GNDMTR 16 33 RESETN DEBUG0 DEBUG1 SAI VCMOP VDDISO 5 60 GND 47 c u d I INN GNDH 4 61 INP VDDH 3 62 48 19 I 2C P/ /S RD 20 P S VLO VDDSD 2 63 1 IFADC VHI VCM 64 PIN connection (top view) OSC. Figure 2. Tuner 2.1 Block diagram and electrical specifications 31 32 INT ADDR_SD 27 VDDH 30 26 IQCH3 RDS_CS 25 IQCH2 29 24 IQCH1 RDS_INT 23 IQSYNC 28 22 VDD GNDH 21 RDS GND SCL_SCK 18 SDA_MOSI MISO 17 PROTSEL_SS D S HS3I e t le ) s t( o r P o s b O - IFADC Modulator Power Supply pins pair Oscillator Power Supply pins pair Tuner Clock Out and AGC Keying DAC Power Supply pins pair Core Logic 1.8V Power Supply pins pair ) s ( ct I/O Ring 3.3V Power Supply pins pair Table 5. N° 1 u d o Pin description Name r P e t e l o VHI s b O Type Description Notes A It needs external Internally generated IFADC Opamps 2.65V (@VDD=3.3V) reference voltage pin minimum 4.7μF ceramic for external filtering capacitor 2 VCM A Internally generated common mode 1.65V It needs external (@VDD=3.3V) reference voltage pin for minimum 10μF ceramic external filtering capacitor 3 VLO A Internally generated IFADC opamps It needs external 0.65V (@VDD=3.3V) reference voltage pin minimum 4.7μF ceramic for external filtering capacitor 4 INP A Positive IF signal input from tuner 2.0Vpp @VDD=3.3V 5 INN A Negative IF signal input from tuner 2.0Vpp @VDD=3.3V 6 VCMOP - Not connected. After Reset 9/39 Block diagram and electrical specifications Table 5. N° TDA7580 Pin description (continued) Name Type Description After Reset Notes 7 GNDSD G IFADC modulator analogue ground Clean ground, to be star connected to voltage regulator ground 8 GNDOSC G Oscillator ground Clean ground, to be star connected to voltage regulator ground 9 XTI I High impedance oscillator input (quartz connection) or clock input when in Antenna Diversity slave mode Maximum voltage swing is VDD=3.3V 10 XTO O Low impedance oscillator output (quartz connection) 11 VDDOSC P Oscillator power supply 3.3V 12 VDDMTR P Tuner reference clock and AGC keying DAC power supply 1.8V Tuner reference clock positive output. FM 100kHz AMEU 18kHz With internal pull-up, on at reset [PP] Output FM 100kHz AMEU 18kHz With internal pull-up, on at reset [PP] Output 13 14 CKREFP B CKREFN B e t le Tuner reference clock negative output. o s b O - 15 AGCKEY A DAC output for Tuner AGC keying 16 GNDMTR G Ground of the tuner reference clock buffer and the AGC keying DAC 17 t e l o bs 18 SDA_MOSI ) s ( ct u d o r P e PROTSEL_SS o r P 1.5kohm ±30% output impedance. 1Vpp ±1% output dynamic range B DSP0 GPIO for control serial interface (low: SPI or high: I2C) selection at device Bootstrap. In SPI protocol mode, after boot procedure, SPI slave select, otherwise DSP0 GPIO0 DSP0 GPIO0 5V tolerant With internal pull-up, on at reset [PP] Input B Control serial interface and RDS IO: - SPI mode: slave data in or master data out for main SPI & RDS SPI data in - I2C mode: data for main I2C or RDS I2C 5V tolerant With internal pull-up, on at reset [PP] Input DSP0 GPIO1 5V tolerant. With internal pull-up, on at reset [PP] Input 5V tolerant. With internal pull-up, on at reset [PP] Input O 19 MISO B SPI slave data out or master data in for main SPI and RDS SPI data out 20 SCL_SCK B Bit clock for Control Serial Interface and RDS 10/39 c u d ) s t( TDA7580 Block diagram and electrical specifications Table 5. N° Pin description (continued) Name Type Description After Reset Notes 21 GND G Digital core power ground 22 VDD P Digital core power supply 1.8V B High speed synchronous serial interface (HS3I) clock if HS3I master mode, else DSP1 GPIO or DSP1 debug port clock (DBOUT1) DSP1 GPIO0 5V tolerant. With internal pull-up, on at reset Input B High speed synchronous serial interface (HS3I) channel 1 data if HS3I master mode, else DSP1 GPIO or DSP1 debug port request (DBRQ1) DSP1 GPIO1 5V tolerant. With internal pull-up, on at reset [PP] Input B High speed synchronous serial interface (HS3I) channel 2 data if HS3I master mode, else DSP1 GPIO or DSP1 debug port data In (DBIN1) DSP1 GPIO2 5V tolerant. With internal pull-down, on at reset [PP] Input B High speed synchronous serial interface (HS3I) channel 3 data if HS3I master mode, else DSP1 GPIO or DSP1 debug port data out (DBCK1) DSP1 GPIO3 5V tolerant With internal pull-down, on at reset [PP] P 3.3V IO ring power supply (HS3I, I2C/SPI, RDS, INT) G 3.3V IO ring power ground (HS3I, I2C/SPI, RDS, INT) 23 24 25 26 27 28 29 IQSYNC IQCH1 IQCH2 IQCH3 VDDH GNDH RDS_INT 30 RDS_CS 31 INT t e l o e t le o s b O - o r P Input B RDS interrupt to external main microprocessor in case of traffic information DSP1 GPIO4. 5V tolerant, open drain With internal pull-up, on at reset [OD] Input B RDS chip select. When RESETN rising, If DSP1 GPIO5. 5V RDS_CS 0, the RDS’s SPI is selected; tolerant. With internal else RDS’s I2C pull-up, on at reset [PP] Input I DSP0 external interrupt 5V tolerant. With internal pull-up, on at reset DSP0 GPIO2 5V tolerant With internal pull-down, on at reset [PP] ) s ( ct u d o r P e c u d ) s t( 32 ADDR_SD s b O B IFS chip master (Low) or slave (High) mode selection, latched in upon RESETN release. It selects the LSB of the I2C addresses. Station detector output 33 RESETN I Chip hardware reset, active low 5V tolerant With internal pull-up 34 VDD P Digital power supply 1.8V 35 GND G Digital power ground 36 TESTN I Test enable pin, active low Input With internal pull-up 11/39 Block diagram and electrical specifications Table 5. Pin description (continued) Notes After Reset 5V tolerant. DSP0 GPIO3. With internal pull-up, on at reset [PP] Input B 5V tolerant. DSP0 Audio SAI0 data input or test selection pin GPIO5. With internal in test mode pull-up, on at reset [PP] Input TST1_SDI1 B DSP0 GPIO for boot selection or audio SAI1 input. Test selection pin in test mode. Input 40 GNDH G 3.3V IO ring power ground (audio SAI, ResetN, test pins) 41 VDDH P 3.3V IO ring power supply (audio SAI, ResetN, test pins) 42 SDO0 B Radio or audio SAI0 data output 5V tolerant. With internal pull up, @0V at reset [PP] Output 5V tolerant With internal pull up, on at reset [PP] Input N° Name 37 GPIO_SDO1 B DSP0 GPIO for boot selection or audio SAI0 output. 38 TST4_SDI0 39 Type Description 5V tolerant. DSP0 GPIO4. With internal pull-up, on at reset [PP] c u d ) s t( 43 SCLK_SCKT B SAI0 receive and transmit bit clock (master or slave with ASRC); SAI1 transmit bit clock 44 LRCK_LRCKT B SAI0 receive and transmit left/right clock (master or slave with ASRC); SAI1 transmit left/right clock 5V tolerant With internal pull up, on at reset [PP] Input 5V tolerant. DSP0 GPIO6. With internal pull up, on at reset [PP] Input Input e t le o s b O - o r P 45 TST2_SCKR B SAI0 Transmit bit clock; SAI1 receive and transmit bit clock. Or test selection pin in test mode 46 TST3_LRCKR B SAI0 Transmit LeftRight clock; SAI1 Receive and Transmit bit clock. Or Test selection pin in Test Mode DSP0 GPIO7. 5V tolerant. With internal pull up, on at reset [PP] 47 VDD P Digital core power supply 1.8V 48 GND 49 G B (s) t c u d o r P e t e l o DBCK0 bs O TDA7580 Digital core power ground Debug port clock of DSP0 (DBCK0) DSP0 GPIO. 9. 5V tolerant. With internal pull down, on at reset [PP] Input Input 50 DBIN0 B Debug port data input of DSP0 (DBIN0) DSP0 GPIO. 11. 5V tolerant. With internal pull down, on at reset [PP] 51 DBRQ0 B Debug port request of DSP0 (DBRQ0) DSP0 GPIO. 5V tolerant With internal pull up, on at reset [PP] Input 52 DBOUT0 B Debug port data output of DSP0 (DBOUT0) DSP0 GPIO10. 5V tolerant. With internal pull up, on at reset [PP] Input 12/39 TDA7580 Table 5. N° Block diagram and electrical specifications Pin description (continued) Name Type Description After Reset Notes 53 GNDH G 3.3V IO ring power ground (debug interface, GPIO) 54 VDDH P 3.3V IO ring power supply (Debug interface, GPIO) B DSP1 debug port clock (DBCK1) if HS3I master mode, else high speed synchronous serial interface (HS3I) channel3 data DSP1 GPIO9. 5V tolerant. With internal pull down, on at reset [PP] Input B DSP1 GPIO or DSP1 debug port data in (DBIN1) if HS3I master mode, else high speed synchronous serial interface (HS3I) channel2 data i DSP1 GPIO11 5V tolerant With internal pull down, on at reset [PP] Input B DSP1 GPIO or DSP1 debug port request 5V tolerant. With (DBRQ1) if HS3I master mode, else high internal pull up, on at speed synchronous serial interface (HS3I) reset [PP] channel1 data DSP1 GPIO10 5V tolerant With internal pull up, on at reset [PP] 1.8V 55 56 57 DBCK1 DBIN1 DBRQ1 58 DBOUT1 B DSP1 GPIO or DSP1 debug port data out (DBOUT1) if HS3I master mode, else high speed synchronous serial interface (HS3I) clock 59 VDD P Digital core power supply 60 GND G Digital core power ground 61 VDDISO P 3.3V N-isolation biasing supply 62 GNDH G 3.3V IO ring power ground (modulator digital section) 63 VDDH 64 VDDSD s b O e t le o s b O - u d o r P e t e l o ) s ( ct c u d P 3.3V IO ring power supply (modulator digital section) P 3.3V IFADC modulator analogue power supply ) s t( o r P Input Input Clean 3.3V supply to be star connected to voltage regulator Clean power supply, to be star connected to 3.3V voltage regulator I/O Type I/O Definition and status P: Power supply from voltage regulator G: Power ground from voltage regulator A: Analogue I/O I: Digital input O: Digital output B: Bidirectional I/O Z: high impedance (input) O: logic low output X: undefined output 1: logic high output Output PP: Push pull / OD: Open drain 13/39 Block diagram and electrical specifications TDA7580 2.2 Electrical characteristics Table 6. General interface electrical characteristics (Tj =-40°C to 125°C; VDD=1.8V, VDD3= 3.3V) Symbol Parameter Test condition Min. Typ. Max. Unit lilh Low level input current I/Os@VDD3 (absolute value) Vi = 0V (1) (2) without pull-up-down device 1 μA lihh High level input current I/Os@VDD3 (absolute value) Vi = VDD3 (1) (2) without pull-up-down device 1 μA lil Low level input current I/Os@VDD (absolute value) Vi = 0V (1) (3) (4) without pull-up-down device 1 μA lih High level input current I/Os@VDD (absolute value) Vi = VDD (1) (3) (4) without pull-up device 1 μA Iipdh Pull-down current I/Os @ VDD3 Vi = VDD3 (5) with pull-down device 85 μA Iopuh Pull-up current I/Os @ VDD3 Vi = 0V (6) with pull-up device Iopul Pull-up current I/Os @ VDD Iaihop Analogue pin sunk / drawn current Vi = VDD3 on pin1 Vi = 0V Iacm Analogue pin sunk / drawn current Vi = VDD3 on pin 2 Vi = 0V Iail Analogue pin sunk / drawn current Vi = VDD3 on pin 3 Vi = 0V Iain Analogue pin sunk / drawn current Vi = VDD3 on pin 4 and pin 5 Vi = 0V Iaih6 Analogue pin current on pin 6 Iaik Analogue pin sunk / drawn current Vi = VDD on pin 15 Vi = 0V (spec absolute value) Ioz Tri-state output leakage o r P e du 5V tolerant tri-state output leakage t e l o Ilatchup s b O 60 -100 -70 -40 -30 μA -20 μA 1.25 1.55 mA o r P -5.0 -3.75 mA 6.0 8.0 10.0 mA -10.0 -8.0 -6.0 mA 3.75 5.0 6.25 mA -1.55 -1.25 -0.95 mA pull-up device c u d 0.95 -6.25 e t le ) s t( -40 so b O - 24 32 40 μA -40 -32 -24 μA 5 μA 1.6 mA 1 μA Vo = 0V or VDD3 without pull up / down device (1) 1 μA Vo = 0V or VDD (1) 1 μA Vo = 5V 80 μA (s) Vo = 0V or VDD3 ct IozFT Vesd Vi = 0V (3) with 35 0.8 1.2 I/O latch up current V < 0V, V > VDD 200 mA Electrostatic protection Leakage, 1μA 2000 V 1. The leakage currents are generally very small,