TDA7705TR

TDA7705 Highly integrated tuner for AM/FM car radio Features ■ Fully integrated VCO for world tuning ■ High performance PLL for fast RDS system ■ AM/FM mixers with high image rejection ■ Integrated AM-LNA and AM-PINDIODE ■ Automatic self alignment for preselection and image rejection ■ Digital IF signal processing, high performance and drift-free ■ Integrated IF-filters with high selectivity, high dynamic range and adaptive bandwidth control ■ RDS demodulation with group and block synchronization ■ High performance stereodecoder with noiseblanker ■ I2C/SPI bus controlled ■ Single 5 V supply ■ LQFP64 package Description The TDA7705 highly integrated tuner (HIT) is a new generation of high performance tuners for carradio applications. Table 1. LQFP64 It contains mixers and IF amplifiers for AM and FM, fully integrated VCO and PLL synthesizer, IF-processing including adaptive bandwidth control, stereo decoder and RDS decoder on a single chip. The utilization of digital signal processing results in numerous advantages against today's tuners: very low number of external components, very small space occupation and easy application, very high selectivity due to digital filters, high flexibility by software control and automatic alignment. Device summary Order code Package Packing TDA7705 LQFP64 (10x10x1.4mm) Tray TDA7705TR LQFP64 (10x10x1.4mm) Tape and reel September 2013 Doc ID 15938 Rev 9 1/42 www.st.com 1 Contents TDA7705 Contents 1 2 3 2/42 Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 FM - mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 FM - AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 AM - LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 AM - AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 AM - mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 IF A/D converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.7 Audio D/A converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.8 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.9 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.10 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.11 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.12 IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.13 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.13.1 Serial interface choice / boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.13.2 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.13.3 SPI bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4.1 FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4.2 AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4.3 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.4 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.5 Tuning DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 15938 Rev 9 TDA7705 Contents 3.5 3.4.6 IF ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.7 Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.8 IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.9 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.10 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.11 Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5.1 FM overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5.2 AM MW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5.3 AM LW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5.4 AM SW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5.5 WX overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 Front-end processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Weak signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 5.2 6 FM IF-processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.1 Dynamic channel selection filter (DISS) . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.2 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.3 Adjacent channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.4 Stereo blend- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.5 High cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.6 Stereo decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AM IF-processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.1 Channel selection filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.2 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.3 High cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1 Basic application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2 Application schematic example with SPI-bus and tuned preselection . . . 39 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Doc ID 15938 Rev 9 3/42 List of tables TDA7705 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. 4/42 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Boot mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 General key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AM - section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Tuning DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 IF ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 IO interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FM overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AM MW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AM LW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AM SW overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 WX overall system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Register 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Register 0x01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Register 0x02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Register 0x05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Dynamic channel selection filter (DISS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Adjacent channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Stereo blend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 High cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 De-emphasis filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Stereo decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Channel selection filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 High cut control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Doc ID 15938 Rev 9 TDA7705 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 I2C "write" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C "read" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SPI "write" sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SPI "read" sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I2C bus timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI bus timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FM input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AM MW input set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AM LW input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AM SW input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 WX input set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FM wide-band application / I2C control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Example of FM tuned (narrow-band) application / SPI control . . . . . . . . . . . . . . . . . . . . . . 39 LQFP64 (10x10x1.4mm) mechanical data and package dimensions. . . . . . . . . . . . . . . . . 40 Doc ID 15938 Rev 9 5/42 Block diagram and pins description TDA7705 1 Block diagram and pins description 1.1 Block diagram Functional block diagram DSP RDS RDSINT Figure 1. DLL Supply OSC :N AGC AM Doc ID 15938 Rev 9 VCO PLL FREF :8 AGC DAC 6/42 Audio Out STEREO DAC SPI ADC ADC I2C/ NCO SUM TDA7705 Pin description VCC-DAC OSCout OSCin GND-DAC DACoutL GND-IFADC DACoutR LIFrefL LIFrefH VCC-IFADC VCC-PLL GND-PLL VCOdec LFref VCC-VCO Pin connection (top view) GND-VCO Figure 2. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 LFI 1 48 GND-1V2 PLLTEST 2 47 VDD-1V2 DAC 3 46 TEST TCAGCFM 4 45 RSTN FMMIX1dec 5 44 MODE FMMIX1in 6 43 GPIO0 FMMIX2in 7 42 GPIO1 GND-RF 8 41 GPIO2 FMPINDRV 9 40 GPIO3 VCC-RF 10 39 RDSINT TCAM 11 38 VDD-1V2 AMPINDRV 12 37 SCL/CLK PINDdec 13 36 SDA/MOSI PINDin 14 35 SPI_MISO GND-LNA 15 34 SPI_CS LNAin 16 33 GND-3V3 Table 2. Pin # VDD-3V3 REG-1V2 VCCREG12 VCC-DIG GND-DIG VREFdec VREF165 GND-IF AMMIXdec AMMIXin1 AMMIXin2 LNAdec2 LNAout2 LNAin2 LNAout 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LNAdec 1.2 Block diagram and pins description AC00418 Pin description Pin name Function 1 LF1 PLL loopfilter output 2 PLLTEST PLL test output / GPO 3 DAC FM tuning DAC output 4 TCAGCFM FM AGC time constant 5 FMMIX1dec FM mixer decoupling 6 FMIX1in FM mixer input 1 7 FMIX2in FM mixer input 2 8 GND-RF RF Ground 9 FMPINDRV FM AGC PIN diode driver 10 VCC-RF 5V supply for RF section 11 TCAM AM AGC time constant 12 AMPINDRV AM AGC external PIN diode driver 13 PINDdec AM AGC internal PIN diode decoupling 14 PINDin AM AGC internal PIN diode input 15 GND-LNA AM LNA and internal PIN diode GND 16 LNAin AM LNA input Doc ID 15938 Rev 9 7/42 Block diagram and pins description Table 2. Pin # 8/42 TDA7705 Pin description (continued) Pin name Function 17 LNAdec AM LNA decoupling 18 LNAout AM LNA output first stage 19 LNAin2 AM LNA input 2nd stage 20 LNAout2 AM LNA output 21 LNAdec2 AM LNA decoupling 2nd stage 22 AMMIXin2 AM mixer input 2 23 AMMIXin1 AM mixer input 1 24 AMMIXdec AM mixer decoupling 25 GND-IF IF and Vref GND 26 VREF165 1.65V reference voltage decoupling 27 VREFdec 3.3V reference voltage decoupling 28 GND-DIG Digital GND 29 VCC-DIG 5V supply for digital logic 30 VCCreg1V2 VCC of 1.2V regulator 31 REG1V2 1.2V regulator output 32 VDD-3V3 3.3V VDD output / decoupling 33 GND-3V3 3.3V VDD GND 34 SPI_CS SPI chip select 35 SPI_MISO SPI Data output 36 SDA / SPI_MOSI I2C bus data / SPI data input 37 SCL / SPI_CLK I2C bus Clock / SPI clock 38 VDD-1V2 1.2V DSP supply 39 RDSINT RDS interrupt 40 GPIO3 Reserved 41 GPIO2 Reserved 42 GPIO 1 Reserved 43 GPIO 0 Reserved 44 MODE For debug purpose only, connected to GND 45 RSTN Reset pin (active low) 46 TEST Test input 47 VDD-1V2 1.2V DSP supply 48 GND-1V2 Digital GND for 1.2V VDD 49 VCC-DAC 5V supply of audio DAC 50 OSCout Xtal osc output 51 OSCin Xtal osc input Doc ID 15938 Rev 9 TDA7705 Block diagram and pins description Table 2. Pin # Pin description (continued) Pin name Function 52 GND-DAC Audio DAC GND 53 DACoutL Audio output left 54 DACoutR Audio output right 55 GND-IFADC IF ADC GND 56 LIFrefL IF ADC reference low 57 LIFrefH IF ADC reference high 58 VCC-IFADC 5V supply of IF ADC 59 VCC-PLL 5V supply of PLL 60 GND-PLL PLL GND 61 VCO-dec VCO decoupling 62 LFref Loopfilter reference 63 VCC-VCO 5V supply of VCO 64 GND-VCO VCO GND Doc ID 15938 Rev 9 9/42 Function description TDA7705 2 Function description 2.1 FM - mixers The image-rejection mixer has two FM inputs, selectable through software. These inputs feed stages with different gains, noise figures, and IIP3. They are optimized for best performance in case of a passive tuned prestage and for a passive fixed bandpass without tuning for low-cost application respectively. The second input offers also the possibility of an easy addition of a weather-band preselection filter. The input frequency is downconverted to low IF with high image rejection. The tuned application is supported by an 8-bit tuning DAC. The alignment of the DAC is performed automatically. 2.2 FM - AGC The programmable RFAGC senses the mixer input whereas the IFAGC senses the IFADC input to avoid overload. The PIN diode driver is able to drive external PIN diodes with a current value as high as 15mA. The time constant of the FM-AGC is defined by an external capacitor. 2.3 AM - LNA The AM-LNA is integrated with low noise and high IIP2 and IIP3. The gain of the LNA is controlled by the AGC. The maximum gain is set with an external resistor, typically 26 dB with 1 k. 2.4 AM - AGC The programmable AM-RF-AGC senses the mixer inputs and controls the internal PIN diode and LNA gain. First the LNA gain is reduced by about 10dB, then the PIN diodes are activated to attenuate the signal. The time constant of the AM-AGC is defined with an external capacitor and programmable internal currents. 2.5 AM - mixers The image-rejection mixer has two AM inputs selectable via software. It easily supports lowcost applications for extended frequency bands like SW, DRM. The input frequency is converted to low IF with high image rejection. 10/42 Doc ID 15938 Rev 9 TDA7705 2.6 Function description IF A/D converters A high performance IQ-IFADC converts the IF-signal to digital IF for subsequent digital signal processing. 2.7 Audio D/A converters A stereo DAC provides the left / right audio signals after IF-processing and stereodecoding by the DSP. 2.8 VCO The VCO is fully integrated without any external tuning component. It covers all FM frequency bands including EU, US , Japan, EastEU, Weatherband and AM-bands including LW, MW, SW. 2.9 PLL The high speed tuning PLL is able to settle within about 300 µs for fast RDS applications. The frequency step can be as low as 5 kHz in FM and 500 Hz in AM. 2.10 Crystal oscillator The device works with a 37.05 MHz fundamental tone crystal, and can be used also with a 3rd overtone 37.05 MHz crystal. 2.11 DSP The DSP and its hardware accelerators perform all the digital signal processing. The main program is fixed in ROM. Control parameters are copied in RAM and are accessible and modifiable there, thus allowing parametric performance optimization. It performs: ● digital down-conversion of IF ● bandwidth selection with variable controlled bandwidth ● FM and AM noiseblanking ● FM/AM demodulation with softmute, high-cut, weak signal processing and quality detection ● FM stereo decoding with stereo blend ● RDS demodulation including error correction and block synchronization with generation of an RDS interrupt for the main µP ● Autonomous control of RDS-AF tests ● Self alignment of preselection tuning Doc ID 15938 Rev 9 11/42 Function description 2.12 TDA7705 IO interface pins The TDA7705 has the following IO pins: PLLTEST pin 2 general purpose output SPI_CS pin 34 serial communication with µP SPI_MISO pin 35 serial communication with µP SDA/MOSI pin 36 serial communication with µP SCL/CLK pin 37 serial communication with µP RDSINT pin 39 serial communication with µP RSTN pin 45 reset pin driven by µP The pins labeled GPIO0, 1, 2 and 3 (pins 43 to 40) are reserved. The pin PLLTEST output voltage can be freely programmed via software and be used to drive switches if needed by the application. All the inputs are voltage-tolerant up to 3.5 V . The outputs can drive currents up to 0.5 mA from the internal 3.3 V supply line. 2.13 Serial interface The device is controlled with a standard I2C bus or SPI interface. Through the serial bus the processing parameters can be modifed and the signal quality parameters and the RDS information can be read out. The operation of the device is handled through high level commands sent by the main carradio µP through the serial interface, which allow to simplify the operations carried out in the main µP. The high level commands include among others: 2.13.1 ● set frequency (which allows to avoid computing the PLL divider factors); ● start seek (the seek operation can be carried out by the TDA7705 in a completely autonomous fashion); ● RDS seek/search (jumps to AF and quality measurements are automatically sequenced). Serial interface choice / boot mode The device can communicate with the main µP with two different standard serial protocols: SPI and I2C. The configuration is chosen by setting the proper value (0V or 3.3V) at pins 35 and 39 and it is latched (e.g. made effective) when the RSTN line transitions from low to high (when RSTN is low, the IC is in reset mode). The voltage level forced to pins 35 and 39 must be released to start the system operation a suitable time after the RSTN line has gone high. The list of configurations is shown in the following table: 12/42 Doc ID 15938 Rev 9 TDA7705 Table 3. Function description Boot mode pin configuration I2C (addr. 0 x C2) Configuration: Pin I2C (addr. 0 x C8) SPI at reset operation at reset operation at reset operation 39 RDSINT 0 in RDS interrupt out 0 in RDS interrupt out 1 in RDS interrupt out 37 SCL x I2C SCL in x I2C SCL in x SPI CLK in 36 SDA x I2C SDA in/out x I2C SDA in/out x SPI MOSI in 35 (SPI_MISO) 0 in - 1 in - 1 in SPI MISO out 34 (SPI_CS) x - x - x SPI SS in If I2C serial bus is chosen as means of communication with the controlling device, two chip addresses are possible: 0xC2/C3 or 0xC8/C9, depending on the initial configuration of pins 35 and 39. The status of pins 35 and 39 during the reset phase can be set to: high, through external