TDA7803A
High efficiency digital input automotive quad power amplifier with
built-in diagnostics features, ’start stop’ compatible
Datasheet - production data
Programmable diagnostic pin
CMOS compatible enable pin
Thermal protection
GAPGPS00071
PowerSO-36
GAPGPS00069
Pop free in mute to play transitions and viceversa
Flexiwatt 27 (SMD)
Description
The TDA7803A is a single chip quad bridge
amplifier in advanced BCD technology
integrating: a full D/A converter, digital input for
direct connection to I2S (or TDM) and powerful
MOSFET output stages.
GAPGPS00068
GAPGPS00070
Flexiwatt 27
(horizontal)
Flexiwatt 27
(vertical)
Features
The integrated D/A converter allows the
performance to reach an outstanding 115 dB S/N
ratio with more than 110 dB of dynamic range.
AEC-Q100 qualified
24-bit digital processing
115 dB dynamic range (A-weighted)
SB-I (SB - improved) high efficiency operation
the highest ’non - class D’ efficiency
Parallel mode function availability
High output power capability:
– 4 x 27 W 4Ω@ 14.4 V, 1 kHz, THD = 10%
– 4 x 47 W 2 Ω @ 14.4 V, 1 kHz, THD = 10%
Flexible mode control:
– Full I2C bus driving 1.8V/3.3V) with four
addresses selectable (only for PowerSO36
package option)
– Independent front/rear play/ mute
– Selectable digital gains for very-low noise
line-out function
– Digital diagnostic with DC and AC load
detections
Start-stop compatibility (operation down to 6V)
Sample rates: 44.1 kHz, 48 kHz, 96 kHz, 192 kHz
Flexible serial data port (1.8 V / 3.3 V):
– I2S standard, TDM 4Ch, TDM 8Ch, TDM
16ch (8+8ch)
Moreover the TDA7803A integrates an innovative
high efficiency concept, optimized also for
uncorrelated music signals. The device is
designed to be compatible to battery modulation
for class-G systems.
Thanks to this concept, the dissipated “output
power” under average listening conditions can be
reduced up to 50% when compared to the
conventional class AB solutions.
The TDA7803A integrates also a programmable
PLL that is able to lock at the input frequencies of
64*Fs for all the input configurations.
The device is equipped with a full diagnostics array
that communicates the status of each speaker
through the I2C bus. The same I2C bus allows to
control several configurations of the device.
The TDA7803A is able to play music down to 6 V
supply voltage - so it is compatible with the so
called 'start stop' battery profile recently adopted
by several car makers (thus reducing the fuel
consumption and the impact over the
environment).
Offset detector
Independent front/rear clipping detector
May 2022
This is information on a product in full production.
DS12195 Rev 6
1/72
www.st.com
Contents
TDA7803A
Contents
1
Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2
Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
Electrical characteristics typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operation states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1
Standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2
ECO-mode state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3
Amplifier-mode state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4
Turn-on and permanent diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Operation compatibility vs. battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/72
6.1
Voltage regulators timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2
Turn-on diagnostic description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3
Permanent diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4
AC diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.5
Input offset detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.6
Double faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.7
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.8
Voltage monitoring feature and ADC characteristics . . . . . . . . . . . . . . . . 33
6.9
Mute management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.9.1
Auto-mute threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.9.2
Mute and unmute commutation time . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DS12195 Rev 6
TDA7803A
7
8
9
10
Contents
6.10
Class SBI - Improved high efficiency principle . . . . . . . . . . . . . . . . . . . . . 35
6.11
High power and parallel mode configuration . . . . . . . . . . . . . . . . . . . . . . 36
6.12
Power on reset threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1
Noise gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2
Tri-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I2S and TDM bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.1
I2S and TDM input data frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.2
I2S input data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3
TDM input data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.4
Timings requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.5
Group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1
Writing procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.2
Reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.3
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.4
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.5
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.6
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.7
Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.8
I2C bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.1
Instruction byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.1.1
IB0 - Subaddress "I0000000h" - default = "00000000" . . . . . . . . . . . . . 46
10.1.2
IB1 - Subaddress "I0000001h" - default = "00000000" . . . . . . . . . . . . . 47
10.1.3
IB2 - Subaddress "I0000010h" - default = "00000000" . . . . . . . . . . . . . 48
10.1.4
IB3 - Subaddress "I0000011h" - default = "00000000" . . . . . . . . . . . . . 49
10.1.5
IB4 - Subaddress "I0000100h" - default = "00000000" . . . . . . . . . . . . . 50
10.1.6
IB5 - Subaddress "I0000101h" - default = "00000000" . . . . . . . . . . . . . 51
10.1.7
IB6 - Subaddress "I0000110h" - default = "00000000" . . . . . . . . . . . . . 52
10.1.8
IB7 - Subaddress "I0000111h" - default = "00000000" . . . . . . . . . . . . . 53
DS12195 Rev 6
3/72
4
Contents
TDA7803A
10.2
11
Data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.2.1
DB0 - Subaddress: "I0010000h" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
10.2.2
DB1 - Subaddress: "I0010001h" - Channel 1 . . . . . . . . . . . . . . . . . . . . 55
10.2.3
DB2 - Subaddress: "I0010010h" - Channel 2 . . . . . . . . . . . . . . . . . . . . 56
10.2.4
DB3 - Subaddress: "I0010011h" - Channel 3 . . . . . . . . . . . . . . . . . . . . . 57
10.2.5
DB4 - Subaddress: "I0010100h" - Channel 4 . . . . . . . . . . . . . . . . . . . . 58
10.2.6
DB5 - Subaddress: "I0010101h" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.2.7
DB6 - Subaddress: "I0010110h" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10.2.8
DB7 - Subaddress: "I0010111h" - Vcc level ADC conversion . . . . . . . . 60
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11.1
PowerSO-36 (slug up) package information . . . . . . . . . . . . . . . . . . . . . . 61
11.2
Flexiwatt 27 (vertical) package information . . . . . . . . . . . . . . . . . . . . . . . 63
11.3
Flexiwatt 27 (SMD) package information . . . . . . . . . . . . . . . . . . . . . . . . . 65
11.4
Flexiwatt 27 (horizontal) package information . . . . . . . . . . . . . . . . . . . . . 67
11.5
Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4/72
DS12195 Rev 6
TDA7803A
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Flexiwatt27 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PowerSO36 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Start-up pulse typical timings (Fs = 48 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Double faults priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
VCC value express by 8 bit with thermometric code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Transition play to mute strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Mute and unmute commutation time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
System input frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I2S interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Address threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I2C bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
IB0 - Subaddress "I0000000h" - default = "00000000" . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
IB1 - Subaddress "I0000001h" - default = "00000000" . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
IB2 - Subaddress "I0000010h" - default = "00000000" . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
IB3 - Subaddress "I0000011h" - default = "00000000" . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
IB4 - Subaddress "I0000100h" - default = "00000000" . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
IB5 - Subaddress "I0000101h" - default = "00000000" . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
IB6 - Subaddress "I0000110h" - default = "00000000" . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
IB7 - Subaddress "I0000111h" - default = "00000000" . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DB0 - Subaddress: "I0010000h" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DB1 - Subaddress: "I0010001h" - Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DB2 - Subaddress: "I0010010h" - Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DB3 - Subaddress: "I0010011h" - Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DB4 - Subaddress: "I0010100h" - Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DB5 - Subaddress: "I0010101h" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DB6 - Subaddress: "I0010110h" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DB7 - Subaddress: "I0010111h" - Vcc level ADC conversion . . . . . . . . . . . . . . . . . . . . . . 60
PowerSO-36 (slug up) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Flexiwatt 27 (vertical) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Flexiwatt 27 (SMD) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Flexiwatt 27 (horizontal) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DS12195 Rev 6
5/72
5
List of figures
TDA7803A
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
6/72
Block diagram (Flexiwatt27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pins connection diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
I2C bus mode application diagram (Flexiwatt)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
I2C bus mode application diagram (PowerSO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Quiescent current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output power vs. supply voltage (4 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output power vs. supply voltage (2 Ω, STD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Distortion vs. output power (4 Ω, STD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Distortion vs. output power (4 Ω, SBI mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Distortion vs. output power (2 Ω, STD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Distortion vs. output power (2 Ω, SBI mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Distortion vs. frequency (4 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Distortion vs. frequency (2 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Distortion vs. output power (4 Ω, Vs = 6 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Distortion vs. output power (2 Ω, Vs = 6 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Vo vs. Vin (Gv1-2-3-4 settings). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Vo vs. Vin (Gv1-2-3-4 settings + 6 dB dig. gain). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Distortion vs. output voltage (LD-Gv2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Distortion vs. output voltage (LD-Gv3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Distortion vs. output voltage (LD-Gv4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output attenuation vs. Vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Crosstalk vs. frequency (STD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Crosstalk vs. frequency (SBI mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Supply voltage rejection vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Total power dissipation & efficiency vs. Po (4 Ω, STD, Sine) . . . . . . . . . . . . . . . . . . . . . . . 21
Total power dissipation & efficiency vs. Po (4 Ω, SBI, Sine). . . . . . . . . . . . . . . . . . . . . . . . 21
Total power dissipation & efficiency vs. Po (2 Ω, SBI, Sine). . . . . . . . . . . . . . . . . . . . . . . . 21
Power dissipation vs. average Po (audio program simulation, 4 Ω) . . . . . . . . . . . . . . . . . . 21
Power dissipation vs. average Po (audio program simulation, 2 Ω) . . . . . . . . . . . . . . . . . . 21
ITU R-ARM frequency response, weighting filter for transient pop. . . . . . . . . . . . . . . . . . . 21
State diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operation compatibility vs. battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Soft short diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Short circuit and open load diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Short to GND and short to Vs, threshold description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Short across the speaker and open load threshold description, in speaker mode . . . . . . . 27
Short across the speaker and open load threshold description, line driver mode . . . . . . . 28
Permanent diagnostic flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Thermal muting diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Low voltage mute attenuation, supply voltage variation (Vs); result digital attenuation (At) 35
I2S format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TDM 16 (8+8) - channel format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TDM 8-channel format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TDM 16 (8+8) - channel format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Audio interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
I2C bus protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
I2C bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PowerSO-36 (slug up) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DS12195 Rev 6
TDA7803A
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
List of figures
Flexiwatt 27 (vertical) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Flexiwatt 27 (SMD) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Flexiwatt 27 (horizontal) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PowerSO-36 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Flexiwatt 27 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
DS12195 Rev 6
7/72
7
Block diagram and pins description
TDA7803A
1
Block diagram and pins description
1.1
Block diagram
Figure 1. Block diagram (Flexiwatt27)
I2C
26
PLL
WS
5
3
SCK
11
SD24
12
SD13
13
STBY
2
I2S
interface
25
27
I2C
Diagn.
Interpol.
64Fs
+
Noise
shaper
ST-BY
A2D
VCC12 VCC34
CD/DIAG
SDA SCL
7
21
10 OUT1+
Thermometric
Code
Conversion
+
DDWA
64 x 2
Current
generators
array
Thermometric
Code
Conversiion
+
DDWA
64 x 2
Current
generators
array
Thermometric
Code
Conversion
+
DDWA
64 x 2
Current
generators
array
Fully Balanced
Transresistance
Power Filter
Thermometric
Code
Conversion
+
DDWA
64 x 2
Current
generators
array
Fully Balanced
Transresistance
Power Filter
Fully Balanced
Transresistance
Power Filter
Fully Balanced
Transresistance
Power Filter
8
OUT1-
6
4
OUT2+
4
6
OUT2-
18 OUT3+
20 OUT322 OUT424
2
OUT4+
VCC
16
14
D3V3 DGND
17
15
1
25
23
1
19
A3V3
AGND
TAB
PWGND4
PWGND3
9
3
5
PWGND1 PWGND2
GAPGPS02388
1.2
Pins description
Figure 2. Pins connection diagrams
Flexiwatt27
27
SCL
26
SDA
25
CD/DIAG
24
OUT4+
23
PWGND4
22
OUT4-
21
TAB
36
1
TAB
OUT3-
35
2
OUT4-
VCC34
34
3
VCC34
VCC34
PWGND3
33
4
PWGND4
20
OUT3-
OUT3+
32
5
OUT4+
19
PWGND3
NC
31
6
NC
18
OUT3+
17
A3V3
A3V3
30
7
CD/DIAG
16
D3V3
D3V3
29
8
SDA
15
AGND
AGND
28
9
SCL
14
DGND
13
SD13
DGND
27
10
ADD
12
SD24
SD13
26
11
STBY
11
SCK
SD24
25
12
WS
10
OUT1+
SCK
24
13
UNMUTEhw
9
PWGND1
8
OUT1-
OUT1+
23
14
OUT2+
7
VCC12
PWGND1
22
15
PWGND2
6
OUT2-
VCC12
21
16
VCC12
OUT1-
20
17
OUT2-
TAB
19
18
5
PWGND2
4
OUT2+
3
WS
2
STBY
1
TAB
TAB
GAPGPS02390
GAPGPS02389
8/72
PowerSO
DS12195 Rev 6
TDA7803A
Block diagram and pins description
Table 1. Flexiwatt27 pins description
N°
Pin
1
TAB
2
STBY
3
WS
4
OUT2+
5
PWGND2
6
Function
TAB connection
Ground
STBY pin
Input
2
Word select (I S bus)
Logic Input
Channel 2 (Left Rear) positive output
Power Output
Power ground channels 2
Power Ground
OUT2-
Channels 2 (Left Rear) negative output
Power Output
7
VCC12
Channel 1 and 2 positive supply
8
OUT1-
Channel 1 (Left Front) negative output
Power Output
9
PWGND1
Power ground channel 1
Power Ground
10
OUT1+
Channel 1 (Left Front) positive output
Power Output
2S
Battery
bus)
Logic Input
11
SCK
Serial clock (I
12
SD24
Serial data channels 2 and 4 (I2S bus)
2S
bus)
Logic Input
Logic Input
13
SD13
Serial data channels 1 and 3 (I
14
DGND
Digital ground
Signal Ground
15
AGND
Analog ground
Signal Ground
16
D3V3
Digital 3.3V supply filter
Digital Regulator
17
A3V3
Analog 3.3V supply filter
Analog Regulator
18
OUT3+
19
PWGND3
20
Channels 3 (right front) positive output
Power Output
Power ground channel 3
Power Ground
OUT3-
Channels 3 (right front) negative output
Power Output
21
VCC34
Channels 3 and 4 positive supply
22
OUT4-
Channels 4 (right rear) negative output
Power Output
23
PWGND4
Power ground channel 4
Power Ground
24
OUT4+
Channels 4 (right rear) positive output
Power Output
25
CD/DIAG
26
27
Clip detector and diagnostic output
2C
SDA
I
SCL
I2
data
Battery
Open Drain Output
Signal Input
C clock
Signal Input
DS12195 Rev 6
9/72
71
Block diagram and pins description
TDA7803A
Table 2. PowerSO36 pins description
N°
Pin
1
TAB
2
OUT4-
Channels 4 (right rear) negative output
3
VCC34
Channels 3 and 4 positive supply
4
PWGND4
5
OUT4+
Device slug connection
Ground
Power Output
Battery
Power ground channel 4
Power Ground
Channels 4 (right rear) positive output
Power Output
6
NC
7
CD/DIAG
8
SDA
I2C data
Signal Input
SCL
I2
Signal Input
10
ADD
I2C Address
11
STBY
STBY pin
9
Not connected
-
Clip detector and diagnostic output
C clock
Input
WS
UNMUTEhw
14
OUT2+
15
PWGND2
16
VCC12
Channel 1 and 2 positive supply
17
OUT2-
Channels 2 (Left Rear) negative output
18
TAB
Device slug connection
19
TAB
Device slug connection
20
OUT1-
Channel 1 (Left Front) negative output
21
VCC12
Channel 1 and 2 positive supply
22
PWGND1
23
OUT1+
25
SD24
Word select
(I2S
13
SCK
Open Drain Output
Logic Input
12
24
10/72
Function
bus)
Logic Input
Unmute Hardware
Logic Input
Channel 2 (Left Rear) positive output
Power Output
Power ground channels 2
Power Ground
Battery
Power Output
Ground
Ground
Power Output
Battery
Power ground channel 1
Power Ground
Channel 1 (Left Front) positive output
Power Output
Serial clock
(I2S
bus)
Logic Input
Serial data channels 2 and 4
(I2S
(I2
bus)
Logic Input
26
SD13
Serial data channels 1 and 3
27
DGND
Digital ground
Signal Ground
28
AGND
Analog ground
Signal Ground
29
D3V3
Digital 3.3V supply filter
Digital Regulator
30
A3V3
Analog 3.3V supply filter
Analog Regulator
31
NC
S bus)
Not connected
32
OUT3+
33
PWGND3
34
VCC34
Channels 3 and 4 positive supply
35
OUT3-
Channels 3 (right front) negative output
36
TAB
Logic Input
-
Channels 3 (right front) positive output
Power Output
Power ground channel 3
Power Ground
Device slug connection
DS12195 Rev 6
Battery
Power Output
Ground
TDA7803A
2
Application diagrams
Application diagrams
Figure 3. I2C bus mode application diagram (Flexiwatt))
Vs
C3
0.22μF
C4
2.200μF
VCC12
VCC34
7
STBY
21
+
18
2
OUT RF / OUT3
19
20
+
24
23
I2C BUS
SDA
26
SCL
27
OUT RR / OUT4
22
TDA7803A
+
10
OUT LF / OUT1
9
I2S INPUT
WS
3
8
SCK
11
SD24
12
4
SD13
13
5
+
OUT LR / OUT2
6
15
14
17
1
25
16
A3V3
D3V3
C5 (*)
22μF
DGND AGND
TAB
R3
C6 (*)
4.7μF
(*) Ceramic (X7R) types recommended.
V
47k
CD/DIAG
GADG1701170816PS
Figure 4. I2C bus mode application diagram (PowerSO)
Vs
C3
0.22μF
C4
2.200μF
VCC12 VCC12 VCC34 VCC34
21
STBY
16
34
3
11
32
5
I2S INPUT
8
SCL
9
WS
12
SCK
24
22
SD24
25
20
26
ADD
(see Note 1)
10
2
23
TDA7803A
14
R4
47k
C7
OUT RR / OUT4
+
OUT LF / OUT1
+
OUT LR / OUT2
15
17
UNMUTEhw
+
4
SDA
SD13
OUT RF / OUT3
33
35
I2C BUS
+
13
27
1, 18, 19, 36
28
30
29
A3V3
1μF
DGND AGND
C5 (*)
22μF
TAB
7
D3V3
C6 (*)
4.7μF
(*) Ceramic (X7R) types recommended.
R3
V
47k
CD/DIAG
GADG1701170820PS
2
1. Refer to Section 9: I C bus interface for connection suggestions.
DS12195 Rev 6
11/72
71
Electrical specification
TDA7803A
3
Electrical specification
3.1
Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol
VS
Parameter
Value
Unit
DC supply voltage
-0.3 to 28
V
Transient supply voltage for t = 100 ms
-0.3 to 50
V
2
-0.3 to 4.6
V
2
I S bus pins voltage
-0.3 to 4.6
V
Unmute hardware voltage (PSO36 only)
-0.3 to 4.6
V
CD/Diag pin voltage
-0.3 to 20
V
STBY pin voltage
-0.3 to 4.6
V
Output peak current (repetitive f > 10 Hz)
internally
limited(1)
A
85
W
Storage and junction temperature
55 to 150
°C
Tamb
Operative temperature range(2)
-40 to 105
°C
Cmax
Maximum capacitor vs. ground connected to the output
Vpeak
Vi2c
Vi2s
Vunmute
Vcd
Vstby
IO
Ptot
Tstg, Tj
ESDHBM
ESDCDM
I C bus pins voltage
Power dissipation Tcase = 70 °C
4.7
nF
ESD protection HBM
(3)
2000
V
ESD protection CDM
(3)
500
V
1. Internally limited by overcurrent protection.
2. A suitable heatsink/dissipation system should be used to keep Tj inside the specified limits.
3. Conforming to Q100 ESD standard.
3.2
Thermal data
Table 4. Thermal data
Symbol
Rth j-case
12/72
Parameter
Thermal resistance junction-to-case (max.)
DS12195 Rev 6
Value
Unit
1
°C/W
TDA7803A
3.3
Electrical specification
Electrical characteristics
Referred to the test setup VS = 14.4 V; RL = 4 Ω; f = 1 kHz; tested at Tamb = 25 °C;
functionality guaranteed for Tj = -40 °C to 150 °C; SB-I mode; unless otherwise specified.
Table 5. Electrical characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
RL = 4 Ω
6
-
18.5
V
RL = 2 Ω, std_bridge
6
-
16
V
RL = 2 Ω, SBI
6
-
16
V
Standby current
-
-
1
4
µA
Iq
Total quiescent current in
amplifier mode
Mute condition
-
170
210
mA
IqECO
Total quiescent current in
ECO mode
ECO mode
-
35
40
mA
AM
Mute attenuation
-
80
-
-
dB
VOS
Offset voltage
Mute and play
-25
-
+25
mV
Attenuation Receive-Mode (Chip could be programmed by uP)
I = Auto increment; when 1, the address is automatically incremented for each byte
transferred
A = Acknowledge
P = Stop
MAX CLOCK SPEED 400kbit/sec
There are four I2C addresses (for PowerSO36 package): 1101100, 1101101, 1101110, 1101111.
For Flexiwatt package only the 1101100 is available.
DS12195 Rev 6
43/72
71
I2C bus interface
9.1
TDA7803A
Writing procedure
There are two possible procedures:
9.2
1.
without increment: the I bit is set to 0 and the register to be written is addressed by the
subaddress SUB A. Only this register is written by the DATA byte following the
subaddress byte.
2.
with increment: the I bit is set to 1 and the first register to be written is the one
addressed by subaddress SUB A. Then all the registers from SUB A up to stop bit or
the reaching of last register are written.
Reading procedure
There are two possible procedures:
9.3
1.
without increment: the I bit is set to 0 and the only register to be read is addressed by
the subaddress sent in the previous write procedure.
2.
with increment: the I bit is set to 1 and the first register to be read is the one addressed
by subaddress sent in the previous write procedure. Then all the registers from this
subaddress up to stop bit or the reaching of last register are read.
Data validity
The data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
9.4
Start and stop conditions
A start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH.
The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
9.5
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
9.6
Acknowledge
The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse. The receiver** has to pull-down (LOW) the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during this clock pulse.
* Transmitter
= master (μP) when it writes an address or instruction byte to the TDA7803A
= slave (TDA7803A) when the μP reads a data byte from TDA7803A
** Receiver
= slave (TDA7803A) when the μP writes an address or instruction byte to the
TDA7803A
= master (μP) when it reads a data byte from TDA7803A
44/72
DS12195 Rev 6
I2C bus interface
TDA7803A
9.7
Address selection
To select the proper I2C address a resistor must be connected to ADD pin as follows:
Table 14. Address threshold
ADD2
9.8
ADD1
Rload
0
0
120K < R
0
1
56K < R < 64K
1
0
30K < R < 38K
1
1
R < 15K
I2C bus timings
This paragraph describes more in detail the I2C bus protocol used and its timings. Figure 47
and Table 15 include the timings that have to be respected in order to correctly write into/
read from the I2C registers.
Figure 47. I2C bus interface timing
Tsclh
Tbuf
Tscll
SCL
Tsclp
Tsstart
Thstart
Tssda
SDA
Tsstop
Thsda
MSB7
MSB0
ACK
start
stop
GAPGPS00814
Table 15. I2C bus interface timing
Symbol
Parameter
Fscl
SCL (clock line) frequency
Tscl
SCL period
Tsclh
Tscll
Min
Max
Unit
-
400
kHz
2500
-
ns
SCL high time
0.6
-
µs
SCL low time
1.3
-
µs
Tsstart
Setup time for start condition
0.6
-
µs
Thstart
Hold time for start condition
0.6
-
µs
Tsstop
Setup time for stop condition
0.6
-
µs
Bus free time between a stop and a start condition
1.3
-
µs
Setup time for data line
100
-
ns
Hold time for data line
0(1)
-
ns
-
300
ns
Tbuf
Tssda
Thsda
Tf
Fall time for SCL and SDA
1. Device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined
region of the falling edge of SCL.
DS12195 Rev 6
45/72
71
I2C registers
TDA7803A
10
I2C registers
10.1
Instruction byte
10.1.1
IB0 - Subaddress "I0000000h" - default = "00000000"
Table 16. IB0 - Subaddress "I0000000h" - default = "00000000"
Bit
46/72
Instruction decoding bit
D7
Channel 4 Tristate Mode
0: off
1: on
D6
Channel 3 Tristate Mode
0: off
1: on
D5
Channel 2 Tristate Mode
0: off
1: on
D4
Channel 1 Tristate Mode
0: off
1: on
D3
Channel 4 Amplifier Mode
0: High Efficiency SBI mode
1: Standard Class AB Mode
D2
Channel 3 Amplifier Mode
0: High Efficiency SBI mode
1: Standard Class AB Mode
D1
Channel 2 Amplifier Mode
0: High Efficiency SBI mode
1: Standard Class AB Mode
D0
Channel 1 Amplifier Mode
0: High Efficiency SBI mode
1: Standard Class AB Mode
DS12195 Rev 6
I2C registers
TDA7803A
10.1.2
IB1 - Subaddress "I0000001h" - default = "00000000"
Table 17. IB1 - Subaddress "I0000001h" - default = "00000000"
Bit
Instruction decoding bit
D7
Impedance efficiency optimizer (front channels)
0: Efficiency optimized for 2 ohm
1: Efficiency optimized for 4 ohm
D6
Impedance efficiency optimizer (rear channels)
0: Efficiency optimized for 2 ohm
1: Efficiency optimized for 4 ohm
D5
D4
Digital gain selection
D4 D5 Digital gain
0
0
No digital gain
1
0
+6 dB
0
1
+12 dB
1
1
Not used
D3
D2
Gain Channel 1 & 3
D3 D2
Gain
0 0
GV1
0 1
GV2
1 0
GV3
1 1
GV4
D1
D0
Gain Channel 2 & 4
D1 D0
Gain
0 0
GV1
0 1
GV2
1 0
GV3
1 1
GV4
DS12195 Rev 6
47/72
71
I2C registers
10.1.3
TDA7803A
IB2 - Subaddress "I0000010h" - default = "00000000"
Table 18. IB2 - Subaddress "I0000010h" - default = "00000000"
Bit
48/72
Instruction decoding bit
D7
D6
D5
Mute Time Setting
D7 D6
D5
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
D4
Mute 1&3
0: Channels 1 & 3 Muted
1: Channels 1 & 3 un-Muted
D3
Mute 2&4
0: Channels 2 & 4 Muted
1: Channels 2 & 4 un-Muted
D2
Disable digital mute
0: Digital mute ON
1: Digital mute OFF
D1
Internal use – set “0”
D0
Low Battery Mute threshold
0: 5.3 V (guaranteed play down to 6 V)
1: 7.3 V (guaranteed play down to 8 V)
mute timing (Fs = 44.1 kHz)
1.45 ms
5.8 ms
11.6 ms
23.2 ms
46.4 ms
92.8 ms
185.5 ms
371.1 ms
DS12195 Rev 6
I2C registers
TDA7803A
10.1.4
IB3 - Subaddress "I0000011h" - default = "00000000"
Table 19. IB3 - Subaddress "I0000011h" - default = "00000000"
Bit
D7-D6
1.
Note:
Instruction decoding bit
Sample frequency range (Word select frequency)
D7
D6
Sample frequency
0
0
44.1 kHz
0
1
48 kHz(1)
1
0
96 kHz
1
1
192 kHz
D5
D4
D3
Digital Input Format
D5
D4
D3
0
0
0 I2S standard
0
0
1 TDM – 4ch
0
1
0 TDM – 8ch (SD2_4 input, device 1)
0
1
1 TDM – 8ch (SD2_4 input device 2)
1
0
0 TDM – 16ch (8 + 8) (SD2_4 input - device 1)
1
0
1 TDM – 16ch (8 + 8) (SD2_4 input - device 2)
1
1
0 TDM – 16ch (8 + 8) (SD1_3 input - device 3)
1
1
1 TDM – 16ch (8 + 8) (SD1_3 input - device 4)
D2
Noise Gating Function enable/disable
0: enable
1: disable
D1
Input offset detection
0: disable
1: enable
D0
Digital High pass filter enable/disable
0: disable
1: enable
Configurations IB3 [D7, D6] =00 and 01 are the same from a signal processing point of view. The distinction is
needed in order to handle functions timings and duration.
Byte IB3 settings can be changed only if the amplifier is in ECO mode state, otherwise the
command is ignored.
DS12195 Rev 6
49/72
71
I2C registers
10.1.5
TDA7803A
IB4 - Subaddress "I0000100h" - default = "00000000"
Table 20. IB4 - Subaddress "I0000100h" - default = "00000000"
Bit
50/72
Instruction decoding bit
D7
Internal use – set “0”
D6
Short Fault information on CD/diag pin
0: yes
1: no
D5
Offset information on CD/diag pin. Selection possible only if IB3(0) = ”0”
0: yes
1: no
D4
AC diagnostic current threshold
0: high
1: low
D3
AC Diagnostic Enable/Disable
0: disable
1: enable
D2
Channel 1&3 Diagnostic Mode
0: Speaker mode
1: Line Driver mode
D1
Channel 2&4 Diagnostic Mode
0: Speaker mode
1: Line Driver mode
D0
Diagnostic Mode Enable/Disable
0: disable
1: enable
DS12195 Rev 6
I2C registers
TDA7803A
10.1.6
IB5 - Subaddress "I0000101h" - default = "00000000"
Table 21. IB5 - Subaddress "I0000101h" - default = "00000000"
Bit
Instruction decoding bit
Thermal threshold programmability:
D7, D6
D5
D4, D3,
D2, D1
D0
D7
D6
Thermal threshold (TWs)
0
0
Default (datasheet value)
0
1
TWs shifted -10°C
1
0
TWs shifted -20°C
1
1
Not used
Internal use – set “0”
Current capability enhancer
D4 - D1
0000 disabled
1111 enabled
Internal use – set “0”
DS12195 Rev 6
51/72
71
I2C registers
10.1.7
TDA7803A
IB6 - Subaddress "I0000110h" - default = "00000000"
Table 22. IB6 - Subaddress "I0000110h" - default = "00000000"
Bit
Instruction decoding bit
Diagnostic pulse stretch
D7
D6
D5
D7
D6
D5 Diagnostic timing set
0
0
0
Default
0
0
1
Streched*2
0
1
0
Streched*4
0
1
1
Streched*8
1
0
0
Streched*16
Others
D4
Default
Internal use – set “0”
Parallel mode Configuration
D3 D2 (like LOADA,LOADB):
D3
D2
52/72
D3
D2
0
0
Single channel mode on 1,2,3 & 4 channel
0
1
Parallel mode only on 1 & 2 channels
1
0
Parallel mode only on 3 & 4 channels
1
1
Parallel mode on both sides
D1
Internal use – set “0”
D0
Internal use – set “0”
Load configuration
DS12195 Rev 6
I2C registers
TDA7803A
10.1.8
IB7 - Subaddress "I0000111h" - default = "00000000"
Table 23. IB7 - Subaddress "I0000111h" - default = "00000000"
Bit
Instruction decoding bit
D7
D6
D5
Temperature warning information on CDdiag pin
D7 D6 D5
Temperature
0 0 0
TW1
0 0 1
TW2
0 1 0
TW3
0 1 1
TW4
1 x x
no thermal warning information on diag pin
D4
D3
Clipping detection level for front channels
D4 D3
0 0 threshold 1 for all channel 1 and 3
0 1 threshold 2 for all channel 1 and 3
1 0 threshold 3 for all channel 1 and 3
1 1 no clipping for channel 1 and 3
D2
D1
Clipping detection level for rear channels
D2 D1
0 0 threshold 1 for all channel 2 and 4
0 1 threshold 2 for all channel 2 and 4
1 0 threshold 3 for all channel 2 and 4
1 1 no clipping for channel 2 and 4
D0
Amplifier on/off
0: off
1: on
DS12195 Rev 6
53/72
71
I2C registers
TDA7803A
10.2
Data byte
10.2.1
DB0 - Subaddress: "I0010000h"
Table 24. DB0 - Subaddress: "I0010000h"
Bit
54/72
Instruction decoding bit
D7
Power on reset (POR)
0: the start-up phase to move from ‘stand by’ state to ’ECO - mode’ state is
running
1: the device is ‘out of stand by’.
D6
Start-up Diagnostic status
0: Turn-on Diag. cycle not activated or not terminated
1: Turn-on Diag. cycle terminated
D5
Diagnostic Data Valid
1: diagnostic data not valid
0: diagnostic data valid
D4
Internal use
D3
Internal use
D2
Internal use
D1
Channel 2 & 4 in mute/play
0: Channel 2 & 4 in play
1: Channel 2 & 4 in mute
D0
Channel 1 & 3 in mute/play
0: Channel 1 & 3 in play
1: Channel 1 & 3 in mute
DS12195 Rev 6
I2C registers
TDA7803A
10.2.2
DB1 - Subaddress: "I0010001h" - Channel 1
Table 25. DB1 - Subaddress: "I0010001h" - Channel 1
Bit
Instruction decoding bit
D7
Overcurrent protection Channel 1:
0: Overcurrent protection NOT triggered on CH1
1: Overcurrent protection triggered on CH1
D6
Channel 1 Soft Short present
0: No Soft short
1: Soft Short
(only during turn-on diagnostic)
D5
Channel 1 offset detection
0: No output offset
1: Output offset detected
D4
Channel 1 Permanent Diagnostic status
0: Permanent diagnostic cycle not activated or not terminated
1: Permanent diagnostic cycle terminated
D3
Channel 1 Normal/Short Load
0: Normal load
1: Short load
D2
Channel 1 Open load
0: No open load
1: Open load detection
(only during turn-on diagnostic)
D1
Channel 1 Short to Vcc
0: No Hard short to Vcc
1: Hard short to Vcc
D0
Channel 1 Short to GND
0: No Hard short to GND
1: Hard Short to GND
DS12195 Rev 6
55/72
71
I2C registers
10.2.3
TDA7803A
DB2 - Subaddress: "I0010010h" - Channel 2
Table 26. DB2 - Subaddress: "I0010010h" - Channel 2
Bit
56/72
Instruction decoding bit
D7
Overcurrent protection Channel 2:
0: Overcurrent protection NOT triggered on CH2
1: Overcurrent protection triggered on CH2
D6
Channel 2 Soft Short present
0: No Soft short
1: Soft Short
(only during turn-on diagnostic)
D5
Channel 2 offset detection
0: No output offset
1: Output offset detected
D4
Channel 2 Permanent Diagnostic status
0: Permanent diagnostic cycle not activated or not terminated
1: Permanent diagnostic cycle terminated
D3
Channel 2 Normal/Short Load
0: Normal load
1: Short load
D2
Channel 2 Open load
0: No open load
1: Open load detection
(only during turn-on diagnostic)
D1
Channel 2 Short to Vcc
0: No Hard short to Vcc
1: Hard short to Vcc
D0
Channel 2 Short to GND
0: No short to GND
1: Short to GND
DS12195 Rev 6
I2C registers
TDA7803A
10.2.4
DB3 - Subaddress: "I0010011h" - Channel 3
Table 27. DB3 - Subaddress: "I0010011h" - Channel 3
Bit
Instruction decoding bit
D7
Overcurrent protection Channel 3:
0: Overcurrent protection NOT triggered on CH3
1: Overcurrent protection triggered on CH3
D6
Channel 3 Soft Short present
0: No Soft short
1: Soft Short
(only during turn-on diagnostic)
D5
Channel 3 offset detection
0: No output offset
1: Output offset detected
D4
Channel 3 Permanent Diagnostic status
0: Permanent diagnostic cycle not activated or not terminated
1: Permanent diagnostic cycle terminated
D3
Channel 3 Normal/Short Load
0: Normal load
1: Short load
D2
Channel 3 Open load
0: No open load
1: Open load detection
(only during turn-on diagnostic)
D1
Channel 3 Short to Vcc
0: No Hard short to Vcc
1: Hard short to Vcc
D0
Channel 3 Short to GND
0: No short to GND
1: Short to GND
DS12195 Rev 6
57/72
71
I2C registers
10.2.5
TDA7803A
DB4 - Subaddress: "I0010100h" - Channel 4
Table 28. DB4 - Subaddress: "I0010100h" - Channel 4
Bit
58/72
Instruction decoding bit
D7
Overcurrent protection Channel 4:
0: Overcurrent protection NOT triggered on CH4
1: Overcurrent protection triggered on CH4
D6
Channel 4 Soft Short present
0: No Soft short
1: Soft Short
(only during turn-on diagnostic)
D5
Channel 4 offset detection
0: No output offset
1: Output offset detected
D4
Channel 4 Permanent Diagnostic status
0: Permanent diagnostic cycle not activated or not terminated
1: Permanent diagnostic cycle terminated
D3
Channel 4 Normal/Short Load
0: Normal load
1: Short load
D2
Channel 4 Open load
0: No open load
1: Open load detection
(only during turn-on diagnostic)
D1
Channel 4 Short to Vcc
0: No Hard short to Vcc
1: Hard short to Vcc
D0
Channel 4 Short to GND
0: No short to GND
1: Short to GND
DS12195 Rev 6
I2C registers
TDA7803A
10.2.6
DB5 - Subaddress: "I0010101h"
Table 29. DB5 - Subaddress: "I0010101h"
Bit
Instruction decoding bit
D7
AC DIAG – Signal level compatible with AC diag detection
0: Signal ok
1: Signal too high
D6
AC DIAG – Channel 4 tweeter detection
0: Ch4 tweeter not present
1: Ch4 tweeter present
D5
AC DIAG – Channel 3 tweeter detection
0: Ch3 tweeter not present
1: Ch3 tweeter present
D4
AC DIAG – Channel 2 tweeter detection
0: Ch2 tweeter not present
1: Ch2 tweeter present
D3
AC DIAG – Channel 1 tweeter detection
0: Ch1 tweeter not present
1: Ch1 tweeter present
D2
Front channel clip detection
0: No clipping on front channel
1: Clipping on front channel
D1
Rear channel clip detection
0: No clipping on rear channel
1: Clipping on rear channel
D0
PLL lock detector
0: PLL no locked
1: PLL locked
DS12195 Rev 6
59/72
71
I2C registers
10.2.7
TDA7803A
DB6 - Subaddress: "I0010110h"
Table 30. DB6 - Subaddress: "I0010110h"
Bit
10.2.8
Instruction decoding bit
D7
TW1
0: TW1 threshold not trespassed
1: TW1 threshold trespassed
D6
TW2
0: TW2 threshold not trespassed
1: TW2 threshold trespassed
D5
TW3
0: TW3 threshold not trespassed
1: TW3 threshold trespassed
D4
TW4
0: TW4 threshold not trespassed
1: TW4 threshold trespassed
D3
Internal use
D2
Internal use
D1
Internal use
D0
Internal use
DB7 - Subaddress: "I0010111h" - Vcc level ADC conversion
Table 31. DB7 - Subaddress: "I0010111h" - Vcc level ADC conversion
Bit
60/72
Instruction decoding bit
D7
Battery Level (7)
D6
Battery Level (6)
D5
Battery Level (5)
D4
Battery Level (4)
D3
Battery Level (3)
D2
Battery Level (2)
D1
Battery Level (1)
D0
Battery Level (0)
DS12195 Rev 6
TDA7803A
11
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
PowerSO-36 (slug up) package information
Figure 48. PowerSO-36 (slug up) package outline
H
E3
A
A5
A4
A2
A
N
0.12 M A B
b
c
D2 (X2)
e
E2
e3
DETAIL A
E
hx45°
1
DETAIL A
(slug tail width)
11.1
B
E1
E4
GAGE
PLAINE
0.35
s
L
a1
SEATING PLANE
C
STAND OFF –
STAND OFF 0
STAND OFF +
G C
36
(COMPLANARITY)
D1
D
GAPGPS03445
7183931_H_ZS
Table 32. PowerSO-36 (slug up) package mechanical data
Dimensions
Ref
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
A
3.27
-
3.41
0.1287
-
0.1343
A2
3.1
-
3.18
0.1220
-
0.1252
DS12195 Rev 6
61/72
71
Package information
TDA7803A
Table 32. PowerSO-36 (slug up) package mechanical data (continued)
Dimensions
Ref
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
A4
0.8
-
1.0
0.0315
-
0.0394
A5
-
0.2
-
-
0.0079
-
a1
0.03
-
-0.04
0.0012
-
-0.0016
b
0.22
-
0.38
0.0087
-
0.0150
c
0.23
-
0.32
0.0091
-
0.0126
(2)
D
15.8
-
16.0
0.6220
-
0.6299
D1
9.4
-
9.8
0.3701
-
0.3858
D2
-
1.0
-
-
0.0394
-
E
13.9
-
14.5
0.5472
-
0.5709
10.9
-
11.1
0.4291
-
0.4370
E2
-
-
2.9
-
-
0.1142
E3
5.8
-
6.2
0.2283
-
0.2441
E4
2.9
-
3.2
0.1142
-
0.1260
e
-
0.65
-
-
0.0256
-
e3
-
11.05
-
-
0.4350
-
G
0
-
0.075
0
-
0.0031
H
15.5
-
15.900
0.6102
-
0.6260
h
-
-
1.1
-
-
0.0433
L
0.8
-
1.1
0.0315
-
0.0433
N
-
-
10°
-
-
10°
s
-
-
8°
-
-
8°
(2)
E1
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. ‘D’ and ‘E1’ do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”).
62/72
DS12195 Rev 6
TDA7803A
Flexiwatt 27 (vertical) package information
Figure 49. Flexiwatt 27 (vertical) package outline
V
C
B
V
H
H1
V3
A
H2
O
H3
R3
L4
R4
V1
R2
L2
N
R
L3
11.2
Package information
L
L1
V1
V2
R2
L5
Pin 1
D
R1
R1
R1
E
G
G1
F
M
M1
GAPGPS03446
7139011_F_48
Table 33. Flexiwatt 27 (vertical) package mechanical data
Dimensions
Ref
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
A
4.45
4.50
4.65
0.1752
0.1772
0.1831
B
1.80
1.90
2.00
0.0709
0.0748
0.0787
C
-
1.40
-
-
0.0551
-
D
0.75
0.90
1.05
0.0295
0.0354
0.0413
E
0.37
0.39
0.42
0.0146
0.0154
0.0165
-
-
0.57
-
-
0.0224
G
0.80
1.00
1.20
0.0315
0.0394
0.0472
G1
25.75
26.00
26.25
1.0138
1.0236
1.0335
28.90
29.23
29.30
1.1378
1.1508
1.1535
H1
-
17.00
-
-
0.6693
-
H2
-
12.80
-
-
0.5039
-
(2)
F
H
(3)
DS12195 Rev 6
63/72
71
Package information
TDA7803A
Table 33. Flexiwatt 27 (vertical) package mechanical data (continued)
Dimensions
Ref
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
H3
-
0.80
-
-
0.0315
-
L (3)
22.07
22.47
22.87
0.8689
0.8846
0.9004
L1
18.57
18.97
19.37
0.7311
0.7469
0.7626
L2 (3)
15.50
15.70
15.90
0.6102
0.6181
0.6260
L3
7.70
7.85
7.95
0.3031
0.3091
0.3130
L4
-
5
-
-
0.1969
-
L5
3.35
3.5
3.65
0.1319
0.1378
0.1437
M
3.70
4.00
4.30
0.1457
0.1575
0.1693
M1
3.60
4.00
4.40
0.1417
0.1575
0.1732
N
-
2.20
-
-
0.0866
-
O
-
2
-
-
0.0787
-
R
-
1.70
-
-
0.0669
-
R1
-
0.5
-
-
0.0197
-
R2
-
0.3
-
-
0.0118
-
R3
-
1.25
-
-
0.0492
-
R4
-
0.50
-
-
0.0197
-
V
5°
5°
V1
3°
3°
V2
20°
20°
V3
45°
45°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. dam-bar protusion not included.
3. molding protusion included.
64/72
DS12195 Rev 6
TDA7803A
Flexiwatt 27 (SMD) package information
Figure 50. Flexiwatt 27 (SMD) package outline
Detail ”A”
Rotated 90° CCW
V4
R3
V2
H1
GAUGE PLANE
R2
V4
H3
V3
L6
STAND OFF
C
B
A
L5
aaa
S
V4
P
D
V4
V
0.50
N2
H2
SEATING PLANE
S
L4
N1
T
H
R1
L3
N
R
V1
V1
R4
L2
M
L1
11.3
Package information
V5
Lead#27
Lead#1
See detail "A"
E
G
F
G2
G1
GAPGPS03447
7993733_D_8Z
Table 34. Flexiwatt 27 (SMD) package mechanical data
Dimensions
Ref
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
A
4.45
4.50
4.65
0.1752
0.1772
0.1831
B
2.12
2.22
2.32
0.0835
0.0874
0.0913
C
-
1.40
-
-
0.0551
-
D
-
2.00
-
-
0.0787
-
E
0.36
0.40
0.44
0.0142
0.0157
0.0173
F(2)
0.47
0.51
0.57
0.0185
0.0201
0.0224
(3)
0.75
1.00
1.25
0.0295
0.0394
0.0492
G
DS12195 Rev 6
65/72
71
Package information
TDA7803A
Table 34. Flexiwatt 27 (SMD) package mechanical data (continued)
Dimensions
Ref
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
G1
25.70
26.00
26.30
1.0118
1.0236
1.0354
G2(3)
1.75
2.00
2.25
0.0689
0.0787
0.0886
28.85
29.23
29.40
1.1358
1.1508
1.1575
H1
-
17.00
-
-
0.6693
-
H2
-
12.80
-
-
0.5039
-
H3
-
0.80
-
-
0.0315
-
L
15.50
15.70
15.90
0.6102
0.6181
0.6260
L1
7.70
7.85
7.95
0.3031
0.3091
0.3130
L2
14.00
14.20
14.40
0.5512
0.5591
0.5669
L3
11.80
12.00
12.20
0.4646
0.4724
0.4803
L4
1.30
1.48
1.66
0.0512
0.0583
0.0654
L5
2.42
2.50
2.58
0.0953
0.0984
0.1016
L6
0.42
0.50
0.58
0.0165
0.0197
0.0228
M
-
1.50
-
-
0.0591
-
N
-
2.20
-
-
0.0866
-
N1
1.30
1.48
1.66
0.0512
0.0583
0.0654
2.73(3)
2.83
2.93
0.1075
0.1114
0.1154
4.73
4.83
4.93
0.1862
0.1902
0.1941
R
-
1.70
-
-
0.0669
-
R1
-
0.30
-
-
0.0118
-
R2
0.35
0.40
0.45
0.0138
0.0157
0.0177
R3
0.35
0.40
0.45
0.0138
0.0157
0.0177
R4
-
0.50
-
-
0.0197
-
T(3)
-0.08
-
0.10
-0.0031
-
0.0039
aaa(3)
-
0.1
-
-
0.0039
-
V
-
45°
-
-
45°
-
(2)
H
(2)
(3)
N2
(3)
P
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension “F” doesn’t include dam-bar protrusion.
Dimensions "H” and “L" include mold flash or protrusions.
3.
66/72
Golden parameters.
DS12195 Rev 6
TDA7803A
Flexiwatt 27 (horizontal) package information
Figure 51. Flexiwatt 27 (horizontal) package outline
B
C
V
V
H
V3
H2
H1
D
H3
R2
N
R2
L
V1
L2
V1
L4
R4
R
M
V2
L5
L6
L1
L3
G
F
G1
P
E
R1
M1
R1
11.4
Package information
M2
GAPGPS03453
7399738_D_QL
Table 35. Flexiwatt 27 (horizontal) package mechanical data
Dimensions
Ref
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
A
4.45
4.50
4.65
0.1752
0.1772
0.1831
B
1.80
1.90
2.00
0.0709
0.0748
0.0787
C
-
1.40
-
-
0.0551
-
D
-
2.00
-
-
0.0787
-
E
0.37
0.39
0.42
0.0146
0.0154
0.0165
F(2)
-
-
0.57
-
-
0.0224
G
0.75
1.00
1.25
0.0295
0.0394
0.0492
DS12195 Rev 6
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71
Package information
TDA7803A
Table 35. Flexiwatt 27 (horizontal) package mechanical data (continued)
Dimensions
Ref
Inches(1)
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
25.70
26.00
26.30
1.0118
1.0236
1.0354
28.90
29.23
29.30
1.1378
1.1508
1.1535
H1
-
17.00
-
-
0.6693
-
H2
-
12.80
-
-
0.5039
-
H3
-
0.80
-
-
0.0315
-
21.64
22.04
22.44
0.8520
0.8677
0.8835
L1
10.15
10.50
10.85
0.3996
0.4134
0.4272
L2 (3)
15.50
15.70
15.90
0.6102
0.6181
0.6260
L3
7.70
7.85
7.95
0.3031
0.3091
0.3130
L4
-
5
-
-
0.1969
-
L5
5.15
5.45
5.85
0.2028
0.2146
0.2303
M
2.75
3.00
3.50
0.1083
0.1181
0.1378
M1
-
4.73
-
-
0.1862
-
M2
-
5.61
-
-
0.2209
-
N
-
2.20
-
-
0.0866
-
P
3.20
3.50
3.80
0.1260
0.1378
0.1496
R
-
1.70
-
-
0.0669
-
R1
-
0.5
-
-
0.0197
-
R2
-
0.3
-
-
0.0118
-
R3
-
1.25
-
-
0.0492
-
R4
-
0.50
-
-
0.0197
-
G1
H
L
(3)
(3)
V
5°
5°
V1
3°
3°
V2
20°
20°
V3
45°
45°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. dam-bar protusion not included.
3. molding protusion included.
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DS12195 Rev 6
TDA7803A
11.5
Package information
Package marking information
Figure 52. PowerSO-36 marking information
Marking area
Last two digits
ES: Engineering sample
: Commercial sample
PowerSO-20/36 TOP VIEW
(not in scale)
GAPG2304150722PS_ES
Figure 53. Flexiwatt 27 marking information
Marking area
Last two digits
ES: Engineering sample
: Commercial sample
Flexiwatt 27 TOP VIEW
(not in scale)
GAPG2204151554PS_ES
Parts marked as ‘ES’ are not yet qualified and therefore not approved for use in production.
ST is not responsible for any consequences resulting from such use. In no event will ST be
liable for the customer using any of these engineering samples in production. ST’s Quality
department must be contacted prior to any decision to use these engineering samples to run
a qualification activity.
DS12195 Rev 6
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71
Order codes
12
TDA7803A
Order codes
Table 36. Ordering information
Order code
Package
Packing
TDA7803A-48X
Flexiwatt27 (Vertical)
Tube
TDA7803A-QLX
Flexiwatt27 (Horizontal)
Tube
TDA7803A-8ZX
TDA7803A-8ZT
TDA7803A-ZSX
TDA7803A-ZST
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Flexiwatt27 (SMD)
PowerSO36
DS12195 Rev 6
Tube
Tape & reel
Tube
Tape & reel
TDA7803A
13
Revision history
Revision history
.;
Table 37. Document revision history
Date
Revision
16-Jun-2017
1
Initial release.
19-Oct-2017
2
Removed note 1 (Part number not yet released for
production.) on Table 35: Ordering information on page 70.
15-Dec-2017
3
Update column note for “TPLS and X” parameters in Table 6.
18-Jan-2018
4
Document changed from "Confidential" to "Public", no
content change.
5
Corrected in Table 3 the value for “Cmax - Maximum
capacitor vs. ground connected to the output” from 10 nF to
4.7 nF.
Updated Table 13: Address threshold on page 45.
6
Updated:
– Figure 27: Total power dissipation & efficiency vs. Po (2 Ω,
SBI, Sine);
– Section 8.5: Group delay.
Minor text changes in:
– Section 6.3: Permanent diagnostic;
– Table 17: IB1 - Subaddress "I0000001h" - default =
"00000000";
– Table 19: IB3 - Subaddress "I0000011h" - default =
"00000000".
15-Jan-2019
25-May-2022
Changes
DS12195 Rev 6
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TDA7803A
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DS12195 Rev 6
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