TEA6425

TEA6425 VIDEO CELLULAR MATRIX ■ ■ ■ ■ ■ ■ ■ ■ ■ 6 Video Inputs - 8 Video Outputs 2 Internal Selectable YC Adders 15MHz Bandwidth @ -3dB Selectable 0.5/6.5dB Gain FOR EACH Output High Impedance Switch for each Output (3state operation) Programmable Clamp Mode on each Input (sync bottom or average value) -60dB Crosstalk @ 5MHz 4 Sub-address Capability I2C Bus Control DIP20 (Plastic Package) ORDER CODE: TEA6425 DESCRIPTION This device is intended for switching between video and chroma signals such as CVBS, SVHS, baseband CVBS, MAC. Each input clamp mode, each output gain, all switching are controlled through the I2C bus. The 8 outputs can be set separately in high impedance state, to enable parallel DC connection of several devices (up to 4). SO20L (Plastic Micropackage) ORDER CODE: TEA6425D September 2003 IN 1 1 20 V CC SDA 2 19 OUT 1 IN 2 3 18 OUT 2 SCL 4 17 OUT 3 IN 3 5 16 OUT 4 IN 4 6 15 OUT 5 SUB 7 14 OUT 6 IN 5 8 13 OUT 7 V CCP 9 12 OUT 8 IN 6 10 11 GND 6425-01.eps Figure 1. Pin Connections 1/10 1 TEA6425 1 PROG. CLAMP 3 PROG. CLAMP 5 PROG. CLAMP 6 PROG. CLAMP 8 PROG. CLAMP 10 PROG. CLAMP SCL 4 SDA 2 SUB-ADDRESS 7 VCC1 9 6x8 MATRIX I2C DECODER 0/6 dB 0/6 dB 0/6 dB VCC2 20 0/6 dB 0/6 dB 0/6 dB 0/6 dB 0/6 dB 17 18 19 6425-02.eps INPUTS Figure 2. Block Diagram 3 STATE OUTPUTS TEA6425 11 12 13 14 15 GND 16 OUTPUTS Figure 3. Cellular Matrix Connections 6 INPUTS PROG. CLAMP 2nd/4 addresses I2 C DECODER I2 C DECODER 6X8 Full MATRIX IC1 6X8 Full MATRIX IC2 6 INPUTS CVBS or C 1st/4 addresses ADDER 0dB 6dB IC3 IC4 8 OUTPUTS LINES 2/10 1 6425-03.eps 3 STATE OUT TEA6425 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI Toper Tstg Parameter Supply Voltage Voltage at Pin i to GND Operating Ambient Temperature Storage Temperature Value 12 0, VCC 0, + 70 -20, + 150 Unit V V oC oC THERMAL DATA Symbol Rth (j-a) Parameter Junction-ambient Thermal Resistance Value 80 Min. Unit C/W o ELECTRICAL CHARACTERISTICS (VCC = 8V, Tamb = 25oC, VIN = 1V, Gain = 6.5dB, Cload = 20pF, Rload = 4.7kΩ ; Gain condition, clamp and 3-state are controlled by I 2C bus, unless otherwise specified) Symbol Parameter Test Conditions SUPPLY Supply Voltage VCC Supply Current ICC RR Supply Voltage Rejection f = 1kHz VIDEO INPUTS (clamping at bottom sync level) Max. Signal Amplitude Clamp Active VIN Vclamp Clamp Level Clamp Active Input DC Level Clamp Inactive VDC Leakage Current 1 input connected to 1 output IIN Clamp Current Vclamp - 200mV Iclamp VIDEO OUTPUTS Output Resistance ROUT Output "off" Impedance no load ZHI COUT in 3-state no load CHI G1 Voltage Gain f = 100kHz G2 Voltage Gain f = 100kHz Top Level Sync (Y or CVBS) G = 6.5dB, Clamp Active Vsync G = 0.5dB, Clamp Inactive Output Mean Level (chroma) Vbias G = 6.5dB, Clamp Inactive Isolation "off" State f = 5MHz Crosstalk Attenuation between f = 5MHz Channels B Bandwidth Cload = 20pF, G = 6.5dB at ± 0.5dB at ± 1dB at - 3dB Min. Typ. Max. Unit 7.2 8 45 46 8.8 60 V mA dB 2 3 2 0.9 2.3 3.3 5 3 15 50 3 0.5 6.5 1.25 2.4 3.4 1 7 2 3 4 40 2 1.7 2.7 50 0 6 1 2 3 60 50 60 5 10 21 VPP V V µA mA W kΩ pF dB dB V V V dB dB MHz FUNCTIONAL DESCRIPTION This device is controlled via the I2C bus. 4 addresses can be selected by a 4-level detector on Pin 7, thus enabling parallel connection of 4 devices. Via the I2C bus : – The input signals can be clamped at their negative peak (top sync). – The gain factor of the outputs can be selected between 0.5 and 6.5dB. – Each of the 6 inputs can be connected to the 8 outputs. – Each output can individually be set in a high impedance state. Two internal SVHS mixers will add the selected Y and C inputs. Two dedicated outputs will have the option to select this added signal also. 3/10 1 TEA6425 I2C BUS CHARACTERISTICS Symbol SCL VIL VIH ILI fSCL tR tF CI SDA VIL VIH ILI CI tR tF VOL tF CL TIMING tLOW tHIGH tSU, DAT tHD, DAT tSU, STO tBUF tHD, STA Parameter Test Conditions Low Level Input Voltage High Level Input Voltage Input Leakage Current Clock Frequency Input Rise Time Input Fall Time Input Capacitance VI = 0 to VDD Standard Mode Min. Max. Fast Mode Min. Max. - 0.3 3.0 - 10 0 + 1.5 VCC + 0.5 + 10 100 1000 300 10 - 0.3 + 1.5 V 3.0 VCC + 0.5 V - 10 + 10 µA 0 400 kHz 300 ns 300 ns 10 pF - 0.3 3.0 - 10 + 1.5 VCC + 0.5 + 10 10 1000 300 0.4 250 400 - 0.3 + 1.5 3.0 VCC + 0.5 - 10 + 10 10 300 300 0.4 250 400 V V µA pF ns ns V ns pF 1.3 0.6 100 0 0.6 1.3 0.6 µs µs ns ns µs µs µs 1.5V to 3V 1.5V to 3V Low Level Input Voltage High Level Input Voltage Input Leakage Current Input Capacitance Input Rise Time Input Fall Time Low Level Output Voltage Output Fall Time Load Capacitance VI = 0 to VDD 1.5V to 3V 1.5V to 3V IOL = 3mA 3V to 1.5V Clock Low Period Clock High Period Data Set-up Time Data Hold Time Set-up Time from Clock High to Stop Start Set-up Time following a Stop Start Hold Time Start Set-up Time following Clock Low-to tSU, STA High Transition 4.7 4.0 250 0 4.0 4.7 4.0 340 4.7 0.6 340 Unit µs Figure 4. I2C Bus Timing SDA t BUF t LOW tf SCL tr t HD,DAT t HIGH t SU,DAT SDA t SU,STA 4/10 1 t SU,STO 6425-04.eps t HD,STA TEA6425 I2C BUS SELECTION I2C Bus Slave Address Address A6 A5 A4 A3 A2 A1 A0 R/W Value 1 0 0 1 0 A1 A0 0 I2C Sub-Address Symbol Parameter Vsub Slave address HEXA 1 2 3 4 90 96 94 92 Conditions Sub-address (see note) A0 A1 0 0 1 1 0 1 1 0 Pin 7 Voltage (Typ) Unit GND VCC 1/3 2/3 V V VCC VCC Note: The first 3 levels are defined by connecting the sub-address pin to the appropriate level. Sub-address 4 will be selected when this pin is left open. 1st Data Byte Output Select b7 b6 b5 b4 b3 b2 b1 b0 a2 0 0 0 0 1 1 1 1 a1 0 0 1 1 0 0 1 1 a0 0 1 0 1 0 1 0 1 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * I 0 0 0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 a2 0 0 0 0 1 1 * * * * * * * * a1 0 0 1 1 0 0 * * * * * * * * a0 0 1 0 1 0 1 * * * * * * * * * * * * * * * 0 1 * * * * * * * * * * * * * * * 0 1 * * * * * * * * * * * * * * * 0 1 * * * * * * * * * * * * * * * 0 1 I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Selected Output OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 2nd Data Byte Input Select Clamp Gain Mixer Tri-state Selected Output IN1 IN2 IN3 IN4 IN5 IN6 Free Clamped 0.5dB 6.5dB Disabled Enabled Low impedance Tri-state Power-on-Reset When active: outputs in 3-state, inputs are clamped Symbol Parameter Start of Reset Reset End of Reset Test Conditions Incr. VCC Decr. VCC Incr. VCC Min. 4.5 Typ. Max. 2.5 4.2 Unit V V V 5/10 1 TEA6425 PIN CONFIGURATIONS Figure 5. Video IN Clamp V REF V REF Clamp 6425-05.eps Pins 1 - 3 - 5 6 - 8 - 10 to Matrix Figure 6. Video OUT TRI-STATE TRI-STATE TRI-STATE Pins 12 - 13 - 14 - 15 16 - 17 - 18 - 19 From Matrix TRISTATE TRISTATE TRISTATE TRI-STATE 6425-06.eps V REF TRISTATE Figure 7. PROG Pin Figure 8. Bus Inputs VC C VC C 20kΩ ESD PROT. VREF 7 Pins 2-4 40kΩ to CMOS V REF to CMOS X4 6425-07.eps 6/10 1 For SDA only 6425-08.eps ACKN 3 TIMES IN // TEA6425 Figure 9. Typical Application V CC (+8V) 22µF 10µH 75Ω C 220nF 220nF Y 75Ω 4.7kΩ 9 3 C3 C4 C5 Y2 5 6 8 C6 10 C2 2x 75Ω I2 C TUNER OUT (CVBS) 4.7kΩ 17 16 15 CVBS/Y 14 TO TV PROCESSOR (CVBS or YC) C 13 12 2 4 7 2 4 7 SDA SCL C7 75Ω 19 1 T E A 6 4 2 5 C8 3 SCART 1 (CVBS IN) C9 SCART 2 (CVBS IN) 5 C10 6 SCART 3 (CVBS IN) C11 8 10 9 18 75Ω 17 75Ω 16 SCART 1 (CVBS OUT) SCART 2 (CVBS OUT) SCART 3 (CVBS OUT) 15 14 13 12 6x 4.7kΩ 11 20 220nF C12 220nF 3x 75Ω 18 Y COMB FILTER C (CVBS) 4.7kΩ SVHS 1/2 (Y+C) 6425-09.eps SVHS2 IN T E A 6 4 2 5 C2 2x 75Ω TO PIP PROCESSOR (CVBS or Y+C) 19 1 C1 4.7kΩ 11 20 C1 Y1 SVHS1 IN EXT SVHS OUT 7/10 TEA6425 PACKAGE MECHANICAL DATA 20 PINS - PLASTIC DIP Figure 10. 20-Pin Package 8/10 TEA6425 PACKAGE MECHANICAL DATA (Cont’d) 20 PINS - PLASTIC MICROPACKAGE Figure 11. 20-Pin Package 9/10 TEA6425 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. 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