TS2007FC
3 W, filter-free, class-D audio power amplifier with 6 or 12 dB fixed
gain select
Datasheet - production data
Description
TS2007EIJT, 9-bump Flip-chip
The TS2007FC is a class-D audio power
amplifier. It is able to drive up to 1.4 W into an 8 Ω
load at 5 V, it achieves better efficiency than
typical class-AB audio power amplifiers.
This device can switch between two gain settings,
6 dB or 12 dB via a logic signal on the gain select
pin. The pop and click reduction circuitry provides
low on/off switching noise which allows the device
to start within 1 ms typically.
A standby mode function (active low) keeps the
current consumption down to 1 µA typically.
Features
• Operates from VCC = 2.4 V to 5.5 V
The TS2007FC is available in a 9-bump Flip-chip
lead-free package.
• Standby mode active low
• Output power: 1.4 W at 5 V or 0.5 W at 3.0 V
into 8 Ω with 1% THD+N max.
• Output power: 2.3 W at 5 V or 0.75 W at 3.0 V
into 4 Ω with 1% THD+N max.
• Two fixed gain selects: 6 dB or 12 dB
• Low current consumption
• Efficiency: 86% typ.
• Signal-to-noise ratio: 90 dB typ.
• PSRR: 68 dB typical at 217 Hz with 6 dB gain
• PWM base frequency: 280 kHz
• Low pop and click noise
• Thermal shutdown protection
• Output short-circuit protection
• Flip-chip lead-free 9-bump package with back
coating in option
Applications
• Cellular phones
• PDAs
• Notebook PCs
April 2019
This is information on a product in full production.
DocID14937 Rev 4
1/33
www.st.com
Contents
TS2007FC
Contents
1
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 4
2
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
5
3.1
Electrical characteristics tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2
Electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1
Differential configuration principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2
Gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3
Common mode feedback loop limitations . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4
Low frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5
Circuit decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6
Wakeup time (twu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.7
Shutdown time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.8
Consumption in shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.9
Single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.10
Output filter considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.11
Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.12
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1
9-bump Flip-chip package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/33
DocID14937 Rev 4
TS2007FC
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Absolute maximum ratings (AMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
External component description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VCC = +5 V, GND = 0 V, Vic = 2.5 V, Tamb = 25 °C (unless otherwise specified) . . . . . . . . 8
VCC = +4.2 V, GND = 0 V, Vic = 2.1 V, Tamb = 25 °C (unless otherwise specified) . . . . . . . 9
VCC = +3.6 V, GND = 0 V, Vic = 1.8 V, Tamb = 25 °C (unless otherwise specified) . . . . . . 10
VCC = +3.0 V, GND = 0 V, Vic = 1.5 V, Tamb = 25 °C (unless otherwise specified) . . . . . . 11
VCC = +2.7 V, GND = 0 V, Vic = 1.35 V, Tamb = 25 °C (unless otherwise specified) . . . . . 12
Index of graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
GS pin gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Example of component choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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List of figures
TS2007FC
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
4/33
9-bump Flip-chip pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Test diagram for measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Test diagram for PSRR measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Current consumption vs. power supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Standby current vs. power supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current consumption vs. standby voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Efficiency vs. output power @ 5 V and 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Efficiency vs. output power @ 5 V and 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Efficiency vs. output power @ 3.6 V and 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Efficiency vs. output power @ 3.6 V and 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Efficiency vs. output power @ 2.7 V and 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Efficiency vs. output power @ 2.7 V and 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output power vs. power supply voltage @ 1% THD+N . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output power vs. power supply voltage @ 10% THD+N . . . . . . . . . . . . . . . . . . . . . . . . . . 18
THD+N vs. output power @ 4 Ω and 100 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
THD+N vs. output power @ 8 Ω and 100 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
THD+N vs. frequency @ 4 Ω and 1 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
THD+N vs. output power @ 8 Ω and 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
THD+N vs. frequency @ 5 V and 4 Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
THD+N vs. frequency @ 5 V and 8 Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
THD+N vs. frequency @ 4.2 V and 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
THD+N vs. frequency @ 4.2 V and 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
THD+N vs. frequency @ 3.6 V and 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
THD+N vs. frequency @ 3.6 V and 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
THD+N vs. frequency @ 3 V and 4 Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
THD+N vs. frequency @ 3 V and 8 Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
THD+N vs. frequency @ 2.7 V and 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
THD+N vs. frequency @ 2.7 V and 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PSRR vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PSRR vs. common mode input voltage @ +6 dB gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PSRR vs. common mode input voltage @ +12 dB gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CMRR vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CMRR vs. common mode input voltage @ +6 dB gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CMRR vs. common mode input voltage @ +12 dB gain . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Gain vs. frequency @ +6 dB gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Gain vs. frequency @ +12 dB gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output offset vs. common mode input voltage @ 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output offset vs. common mode input voltage @ 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output offset vs. common mode input voltage @ 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power derating curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Startup and shutdown phase VCC = 5 V, G = 6 dB, Cin = 1 µF, inputs grounded . . . . . . . . 23
Startup and shutdown phase VCC = 5 V, G = 6 dB, Cin = 1 µF, Vin = 1 Vpp, F = 10 kHz . . 23
Startup and shutdown phase VCC = 5 V, G = 12 dB, Cin = 1 µF, Vin = 1 Vpp, F = 10 kHz . 23
Typical application for single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Ferrite chip bead placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LC output filter with RC network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9-bump Flip-chip package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DocID14937 Rev 4
TS2007FC
Figure 49.
List of figures
9-bump Flip-chip marking (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Absolute maximum ratings and operating conditions
1
TS2007FC
Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings (AMR)
Symbol
VCC
Vin
Parameter
Value
Supply voltage(1)
Input voltage
6
V
(2)
GND to VCC
Toper
Operating free-air temperature range
-40 to + 85
Tstg
Storage temperature
-65 to +150
Tj
Rthja
Pd
Maximum junction temperature
Thermal resistance junction to
200
Latch-up
Internally limited
Latch-up immunity
Output short-circuit protection
W
2
kV
200
V
Class A = 200
mA
260
°C
Internally limited(7)
A
3.2
Ω
model(6)
Lead temperature (soldering, 10 s)
RL
°C/W
(4)
Human body model(5)
Machine
°C
150
ambient(3)
Power dissipation
ESD
Unit
Minimum load resistor
1. All voltage values are measured with respect to the ground pin
2. The magnitude of the input signal must never exceed VCC + 0.3 V / GND - 0.3 V
3. The device is protected from over heating by a thermal shutdown active @ 150° C
4. Exceeding the power derating curves during a long period provokes abnormal operating conditions
5. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for
all couples of pin combinations with other pins floating.
6. Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two
pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin
combinations with other pins floating.
7. Implemented short-circuit protection protects the amplifier against damage by short-circuit between
positive and negative outputs and between outputs and ground.
6/33
DocID14937 Rev 4
TS2007FC
Absolute maximum ratings and operating conditions
Table 2. Operating conditions
Symbol
Parameter
VCC
Supply voltage
Vin
Input voltage range
Vicm
VSTBY
VGS
RL
Rthja
Value
Unit
2.4 to 5.5
GND to VCC
Input common mode voltage range(1)
Standby voltage input(2):
Device ON
Device OFF
V
1.4 ≤ VSTBY ≤ VCC
GND ≤ VSTBY ≤ 0.4 (3)
Gain select input voltage(4):
Gain = 6 dB
Gain = 12 dB
1.4 ≤ VGS ≤ VCC
GND ≤ VGS ≤ 0.4
Load resistor
Thermal resistance junction to
GND + 0.15 V to
VCC - 0.7 V
ambient(5)
≥4
Ω
90
°C/W
1. |Voo| ≤ 35 mV max with both differential gains
2. Without any signal on VSTBY, the device is in standby (internal 300 kΩ pull-down resistor)
3. Minimum current consumption is obtained when VSTBY = GND
4. Without any signal on GS pin, the device is in a 6 dB gain configuration (internal 300 kΩ pull up resistor)
5. When mounted on 4-layer PCB
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Application information
2
TS2007FC
Application information
Table 3. External component description
Components
Functional description
Cs
Supply capacitor that provides power supply filtering
Cin
Input coupling capacitors (optional) that block the DC voltage at the amplifier input
terminal. These capacitors also form a high-pass filter with
Zin (Fc = 1 / (2 x π x Zin x Cin)).
Figure 1. 9-bump Flip-chip pinout (top view)
3
OUT-
GND
OUT+
2
GS
VCC
STBY
1
IN+
VCC
IN-
A
B
C
Balls are underneath
Table 4. Pin description
8/33
Pin name
Pin description
IN+
Positive differential input
VCC
Power supply
IN-
Negative differential input
GS
Gain select input
STDBY
Standby pin (active low)
GND
Ground
OUT+
Positive differential output
OUT-
Negative differential output
DocID14937 Rev 4
TS2007FC
Application information
Figure 2. Typical application
VCC
Cs
Gain select control
A2
Input capacitors
are optional
InC1
IN-
A1
IN+
Gain
Select
TS2007FC
Vcc
GS
Cin
Differential
Input
B2
1uF
+
Speaker
OUT+ C3
PWM
H
Bridge
A3
OUT-
Cin
C2
Standby
Control
Standby
Oscillator
Protection
Circuit
Gnd
B3
In+
Standby control
Note:
See Section 4.10: Output filter considerations.
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Electrical characteristics
TS2007FC
3
Electrical characteristics
3.1
Electrical characteristics tables
Table 5. VCC = +5 V, GND = 0 V, Vic = 2.5 V, Tamb = 25 °C (unless otherwise specified)
Symbol
ICC
ICC-STBY
Parameter
Min.
Supply current, no input signal, no load
Standby current(1), no input signal, VSTBY = GND
Voo
Output offset voltage, floating inputs, RL = 8 Ω
Po
Output power
THD = 1% max., F = 1 kHz, RL = 4 Ω
THD = 1% max., F = 1 kHz, RL = 8 Ω
THD = 10% max., F = 1 kHz, RL = 4 Ω
THD = 10% max., F = 1 kHz, RL = 8 Ω
Typ.
Max.
Unit
2.5
4
mA
1
2
µA
25
mV
2.3
1.4
3
1.75
THD + N
Total harmonic distortion + noise
Po = 900 mWRMS, G = 6 dB, F= 1 kHz, RL = 8 Ω
Efficiency
Efficiency
Po = 2.3 Wrms, RL = 4 Ω (with LC output filter)
Po = 1.4 Wrms, RL = 8 Ω (with LC output filter)
86
92
PSRR
Power supply rejection ratio with inputs grounded, CIN = 1 µF (2)
F= 217 Hz, RL = 8 Ω, Gain = 6 dB, Vripple = 200 mVpp
F= 217 Hz, RL = 8 Ω, Gain = 12 dB, Vripple = 200 mVpp
68
65
CMRR
Common mode rejection ratio Cin=1 µF, RL = 8 Ω
20 Hz < F< 20 kHz, Gain = 6 dB, ΔVICM = 200 mVpp
Gain value, Gs = 0 V
Gain value, GS = VCC
W
0.12
%
dB
60
11.5
5.5
12
6
12.5
6.5
Single ended input impedance (3)
68
75
82
kΩ
FPWM
Pulse width modulator base frequency
190
280
370
kHz
SNR
Signal-to-noise ratio (A-weighting), F = 1 kHz, Po = 1.9 W
G = 6 dB, RL = 4 Ω (with LC output filter)
93
tWU
Wake-up time
1
tSTBY
Standby time
1
Gain
Zin
VN
dB
3
ms
Output voltage noise, F = 20 Hz to 20 kHz, RL = 4 Ω
Unweighted (filterless, G = 6 dB)
A-weighted (filterless, G = 6 dB)
Unweighted (with LC output filter, G = 6 dB)
A-weighted (with LC output filter, G = 6 dB)
Unweighted (filterless, G = 12 dB)
A-weighted (filterless, G = 12 dB)
Unweighted (with LC output filter, G = 12 dB)
A-weighted (with LC output filter, G = 12 dB)
87
60
83
58
106
77
101
75
1. Standby mode is active when VSTBY is tied to GND
2. Dynamic measurement - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ F =217 Hz.
3. Independent of gain configuration (6 or 12 dB) and between IN+ or IN- and GND
10/33
DocID14937 Rev 4
µVrms
TS2007FC
Electrical characteristics
Table 6. VCC = +4.2 V, GND = 0 V, Vic = 2.1 V, Tamb = 25 °C (unless otherwise specified)
Symbol
ICC
ICC-STBY
Parameter
Min.
Supply current, no input signal, no load
(1)
Standby current , no input signal, VSTBY = GND
Voo
Output offset voltage, floating inputs, RL = 8 Ω
Po
Output power
THD = 1% max., F = 1 kHz, RL = 4 Ω
THD = 1% max., F = 1 kHz, RL = 8 Ω
THD = 10% max., F = 1 kHz, RL = 4 Ω
THD = 10% max., F = 1 kHz, RL = 8 Ω
Typ.
Max.
Unit
2
3.3
mA
0.85
2
µA
25
mV
1.6
0.95
2
1.2
THD + N
Total harmonic distortion + noise
Po = 600 mWrms, G = 6 dB, F = 1 kHz, RL = 8 Ω
Efficiency
Efficiency
Po = 1.6 Wrms, RL = 4 Ω (with LC output filter)
Po = 0.95 Wrms, RL = 8 Ω (with LC output filter)
86
92
PSRR
Power supply rejection ratio with inputs grounded, Cin = 1 µF(2)
F = 217 Hz, RL = 8 Ω, Gain = 6 dB, Vripple = 200 mVpp
F = 217 Hz, RL = 8 Ω, Gain = 12 dB, Vripple = 200 mVpp
68
65
CMRR
Common mode rejection ratio Cin = 1 µF, RL = 8 Ω,
20 Hz < F< 20 kHz, Gain = 6 dB, ΔVICM = 200 mVpp
Gain
Gain value
Gs = 0 V
GS = VCC
W
0.09
%
60
dB
11.5
5.5
12
6
12.5
6.5
Single ended input impedance(3)
68
75
82
kΩ
FPWM
Pulse width modulator base frequency
190
280
370
kHz
SNR
Signal-to-noise ratio (A-weighting), F = 1 kHz, Po = 1.3 W
G = 6 dB, RL = 4 Ω (with LC output filter)
92
tWU
Wake-up time
1
tSTBY
Standby time
1
ZIN
VN
Output voltage noise, F = 20 Hz to 20 kHz, RL = 4 Ω
Unweighted (filterless, G = 6 dB)
A-weighted (filterless, G = 6 dB)
Unweighted (with LC output filter, G = 6 dB)
A-weighted (with LC output filter, G = 6 dB)
Unweighted (filterless, G = 12 dB)
A-weighted (filterless, G = 12 dB)
Unweighted (with LC output filter, G = 12 dB)
A-weighted (with LC output filter, G = 12 dB)
dB
3
86
59
82
57
105
74
100
74
ms
µVrms
1. Standby mode is active when VSTBY is tied to GND
2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ F = 217 Hz
3. Independent of gain configuration (6 or 12 dB) and between IN+ or IN- and GND
DocID14937 Rev 4
11/33
33
Electrical characteristics
TS2007FC
Table 7. VCC = +3.6 V, GND = 0 V, Vic = 1.8 V, Tamb = 25 °C (unless otherwise specified)
Symbol
ICC
ICC-STBY
Parameter
Min.
Supply current, no input signal, no load
(1)
Standby current , no input signal, VSTBY = GND
Voo
Output offset voltage, floating inputs, RL = 8 Ω
Po
Output power
THD = 1% max., F = 1 kHz, RL = 4 Ω
THD = 1% max., F = 1 kHz, RL = 8 Ω
THD = 10% max., F = 1 kHz, RL = 4 Ω
THD = 10% max., F = 1 kHz, RL = 8 Ω
Typ.
Max.
Unit
1.7
3.1
mA
0.75
2
µA
25
mV
1.2
0.7
1.55
0.9
THD + N
Total harmonic distortion + noise
Po = 400 mWrms, G = 6 dB, F = 1 kHz, RL = 8 Ω
Efficiency
Efficiency
Po = 1.18 Wrms, RL = 4 Ω (with LC output filter)
Po = 0.7 Wrms, RL = 8 Ω (with LC output filter)
86
92
PSRR
Power supply rejection ratio with inputs grounded, Cin = 1 µF(2)
F = 217 Hz, RL = 8 Ω, Gain = 6 dB, Vripple = 200 mVpp
F = 217 Hz, RL = 8 Ω, Gain = 12 dB, Vripple = 200 mVpp
68
65
CMRR
Common mode rejection ratio Cin = 1 µF, RL = 8 Ω,
20 Hz < F< 20 kHz, Gain = 6 dB, ΔVICM = 200 mVpp
Gain
Gain value
Gs = 0 V
GS = VCC
W
0.06
%
60
dB
11.5
5.5
12
6
12.5
6.5
Single ended input impedance(3)
68
75
82
kΩ
FPWM
Pulse width modulator base frequency
190
280
370
kHz
SNR
Signal-to-noise ratio (A-weighting), F=1 kHz, Po = 0.9 W
G = 6 dB, RL = 4 Ω (with LC output filter)
90
tWU
Wakeup time
1
tSTBY
Standby time
1
Zin
VN
Output voltage noise, F = 20 Hz to 20 kHz, RL = 4 Ω
Unweighted (filterless, G = 6 dB)
A-weighted (filterless, G = 6 dB)
Unweighted (with LC output filter, G = 6 dB)
A-weighted (with LC output filter, G = 6 dB)
Unweighted (filterless, G = 12 dB)
A-weighted (filterless, G = 12 dB)
Unweighted (with LC output filter, G = 12 dB)
A-weighted (with LC output filter, G = 12 dB)
dB
3
84
58
79
56
104
75
99
72
1. Standby mode is active when VSTBY is tied to GND
2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ F= 217 Hz
3. Independent of gain configuration (6 or 12 dB) and between IN+ or IN- and GND
12/33
DocID14937 Rev 4
ms
μVRMS
TS2007FC
Electrical characteristics
Table 8. VCC = +3.0 V, GND = 0 V, Vic = 1.5 V, Tamb = 25 °C (unless otherwise specified)
Symbol
ICC
ICC-STBY
Parameter
Min.
Supply current, no input signal, no load
(1)
Standby current , no input signal, VSTBY = GND
Voo
Output offset voltage, floating inputs, RL = 8 Ω
Po
Output power
THD = 1% max., F = 1 kHz, RL = 4 Ω
THD = 1% max., F = 1 kHz, RL = 8 Ω
THD = 10% max., F = 1 kHz, RL = 4 Ω
THD = 10% max., F = 1 kHz, RL = 8 Ω
Typ.
Max.
Unit
1.5
2.9
mA
0.6
2
µA
25
mV
0.75
0.5
1
0.6
THD + N
Total harmonic distortion + noise
Po = 300 mWRMS, G = 6 dB, F= 1 kHz, RL = 8 Ω
Efficiency
Efficiency
Po = 0.8 Wrms, RL = 4 Ω (with LC output filter)
Po = 0.5 Wrms, RL = 8 Ω (with LC output filter)
85
91
PSRR
Power supply rejection ratio with inputs grounded, Cin = 1 µF (2)
F = 217 Hz, RL = 8 Ω, Gain = 6 dB, Vripple = 200 mVpp
F = 217 Hz, RL = 8 Ω, Gain = 12 dB, Vripple = 200 mVpp
68
65
CMRR
Common mode rejection ratio Cin = 1 µF, RL = 8 Ω,
20 Hz < F< 20 kHz, Gain = 6 dB, ΔVICM = 200 mVpp
Gain
Gain value
Gs = 0 V
GS = VCC
W
0.04
%
60
dB
11.5
5.5
12
6
12.5
6.5
Single ended input impedance(3)
68
75
82
kΩ
FPWM
Pulse width modulator base frequency
190
280
370
kHz
SNR
Signal-to-noise ratio (A-weighting), F=1 kHz, Po = 0.6 W
G = 6 dB, RL = 4 Ω (with LC output filter)
89
tWU
Wakeup time
1
tSTBY
Standby time
1
Zin
VN
Output voltage noise, F = 20 Hz to 20 kHz, RL = 4 Ω
Unweighted (filterless, G = 6 dB)
A-weighted (filterless, G = 6 dB)
Unweighted (with LC output filter, G = 6 dB)
A-weighted (with LC output filter, G = 6 dB)
Unweighted (filterless, G = 12 dB)
A-weighted (filterless, G = 12 dB)
Unweighted (with LC output filter, G = 12 dB)
A-weighted (with LC output filter, G = 12 dB)
82
57
78
55
103
74
99
71
dB
3
ms
µVRMS
1. Standby mode is active when VSTBY is tied to GND
2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ F = 217 Hz
3. Independent of gain configuration (6 or 12 dB) and between IN+ or IN- and GND
DocID14937 Rev 4
13/33
33
Electrical characteristics
TS2007FC
Table 9. VCC = +2.7 V, GND = 0 V, Vic = 1.35 V, Tamb = 25 °C (unless otherwise specified)
Symbol
ICC
ICC-STBY
Parameter
Min.
Supply current, no input signal, no load
(1)
Standby current , no input signal, VSTBY = GND
Voo
Output offset voltage, floating inputs, RL = 8 Ω
Po
Output power
THD = 1% max., F = 1 kHz, RL = 4 Ω
THD = 1% max., F = 1 kHz, RL = 8 Ω
THD = 10% max., F = 1 kHz, RL = 4 Ω
THD = 10% max., F = 1 kHz, RL = 8 Ω
Typ.
Max.
Unit
1.45
2.5
mA
0.5
2
µA
25
mV
0.64
0.39
0.83
0.49
THD + N
Total harmonic distortion + noise
Po = 250 mWrms, G = 6 dB, F = 1 kHz, RL = 8 Ω
Efficiency
Efficiency
Po = 0.64 Wrms, RL = 4 Ω (with LC output filter)
Po = 0.39 Wrms, RL = 8 Ω (with LC output filter)
84
91
PSRR
Power supply rejection ratio with inputs grounded, Cin = 1 µF (2)
F= 217 Hz, RL = 8 Ω, Gain = 6 dB, Vripple = 200 mVpp
F= 217 Hz, RL = 8 Ω, Gain = 12 dB, Vripple = 200 mVpp
68
65
CMRR
Common mode rejection ratio Cin = 1 µF, RL = 8 Ω,
20 Hz < F< 20 kHz, Gain = 6 dB, ΔVICM = 200 mVpp
Gain
Gain value
Gs = 0 V
GS = VCC
W
0.03
%
60
dB
11.5
5.5
12
6
12.5
6.5
Single ended input impedance(3)
68
75
82
kΩ
FPWM
Pulse width modulator base frequency
190
280
370
kHz
SNR
Signal-to-noise ratio (A-weighting), F=1 kHz, Po = 0.5 W
G = 6 dB, RL = 4 Ω (with LC output filter)
88
tWU
Wakeup time
1
tSTBY
Standby time
1
Zin
VN
dB
3
ms
Output voltage noise, F = 20 Hz to 20 kHz, RL = 4 Ω
Unweighted (filterless, G = 6 dB)
A-weighted (filterless, G = 6 dB)
Unweighted (with LC output filter, G = 6 dB)
A-weighted (with LC output filter, G = 6 dB)
Unweighted (filterless, G = 12 dB)
A-weighted (filterless, G = 12 dB)
Unweighted (with LC output filter, G = 12 dB)
A-weighted (with LC output filter, G = 12 dB)
82
56
77
55
100
73
98
70
µVRMS
1. Standby mode is active when VSTBY is tied to GND
2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinus signal to VCC @ F= 217 Hz
3. Independent of gain configuration (6 or 12 dB) and between IN+ or IN- and GND
14/33
DocID14937 Rev 4
TS2007FC
3.2
Electrical characteristics
Electrical characteristic curves
The graphs shown in this section use the following abbreviations:
•
RL+ 15 µH or 30 µH = pure resistor + very low series resistance inductor
•
Filter = LC output filter (1 µF+ 30 µH for 4 Ω and 0.5 µF+15 µH for 8 Ω)
All measurements are made with CS1 = 1 µF and CS2 = 100 nF (Figure 3), except for the
PSRR where CS1 is removed (Figure 4).
Figure 3. Test diagram for measurements
Cs1
1 µF
VCC
Cs2
100 nF
GND
GND
RL
4 or 8 Ω
Cin
Out+
In+
In-
5th order
50 kHz
15 µH or 30 µH
or
LC Filter
TS2007FC
Out-
low-pass filter
Cin
GND
Audio Measurement
Bandwith < 30 kHz
Figure 4. Test diagram for PSRR measurements
VCC
Cs2
100 nF
20 Hz to 20 kHz
Vripple
GND
GND
1 µF
Cin
Vcc
Out+
In+
TS2007FC
In-
Out-
RL
4 or 8 Ω
15 µH or 30 µH
or
LC Filter
5th order
50 kHz
low-pass filter
Cin
1 µF
GND
5th order
50 kHz
low-pass filter
GND
reference
RMS Selective Measurement
Bandwith =1% of Fmeas
DocID14937 Rev 4
15/33
33
Electrical characteristics
TS2007FC
A list of the graphs shown in this section is provided in Table 10.
Table 10. Index of graphs
Description
16/33
Figure
Current consumption vs. power supply voltage
Figure 5
Standby current vs. power supply voltage
Figure 6
Current consumption vs. standby voltage
Figure 7
Efficiency vs. output power
Figure 8 to Figure 13
Output power vs. power supply voltage
Figure 14, Figure 15
THD+N vs. output power
Figure 16 to Figure 19
THD+N vs. frequency
Figure 20 to Figure 29
PSRR vs. frequency
Figure 30
PSRR vs. common mode input voltage
Figure 31, Figure 32
CMRR vs. frequency
Figure 33
CMRR vs. common mode input voltage
Figure 34, Figure 35
Gain vs. frequency
Figure 36, Figure 37
Output offset vs. common mode input voltage
Figure 38 to Figure 40
Power derating curves
Figure 41
Startup and shutdown phase
Figure 42 to Figure 44
DocID14937 Rev 4
TS2007FC
Electrical characteristics
Figure 5. Current consumption vs. power
supply voltage
3.5
Current Consumption (mA)
3.0
Figure 6. Standby current vs. power supply
voltage
1.4
No load
TAMB = 25°C
No load
Vstdby = GND
Tamb = 25°C
1.2
Standby Current (μA)
2.5
2.0
1.5
1.0
1.0
0.8
0.6
0.4
0.5
0.2
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0
2.5
3.0
3.5
Power Supply Voltage (V)
4.0
4.5
5.0
5.5
Power Supply Voltage (V)
Figure 7. Current consumption vs.
standby voltage
Figure 8. Efficiency vs. output power
@ 5 V and 4 Ω
4
0.6
2
Vcc=3.6V
1
0
Vcc=2.7V
1
2
0.4
0.3
40
Vcc=3V
3
Efficiency
60
Power
Dissipation
20
No load
TAMB = 25°C
0
0.5
80
Vcc=4.2V
4
0
0.0
5
0.5
1.0
1.5
2.0
Output Power (W)
Vcc = 5V
F = 1kHz
RL = 4Ω + ≥ 15μ H
THD+N ≤ 10%
BW ≤ 30kHz
TAMB = 25 °C
2.5
0.2
Power Dissipation (W)
Vcc=5V
Efficiency (%)
3
0.1
0.0
3.0
Standby Voltage (V)
Figure 9. Efficiency vs. output power
@ 5 V and 8 Ω
Figure 10. Efficiency vs. output power
@ 3.6 V and 4 Ω
100
0.16
Efficiency
80
Efficiency
0.10
60
0.08
Power
Dissipation
40
20
0
0.0
0.30
0.12
0.5
1.0
Output Power (W)
Vcc = 5V
F = 1kHz
RL = 8Ω + ≥ 15 μ H
THD+N ≤ 10%
BW ≤ 30kHz
TAMB = 25°C
1.5
0.06
0.04
0.02
0.00
2.0
Efficiency (%)
80
0.35
100
0.25
60
0.20
40
Power
Dissipation
20
0
0.0
DocID14937 Rev 4
0.2
0.4
0.6
0.8
1.0
Output Power (W)
Vcc = 3.6V
F = 1kHz
RL = 4 Ω + ≥ 15μ H
THD+N ≤ 10%
BW ≤ 30kHz
TAMB = 25°C
1.2
1.4
0.15
0.10
Power Dissipation (W)
0.14
Efficiency (%)
Current Consumption (mA)
100
0.05
0.00
1.6
17/33
33
Electrical characteristics
TS2007FC
Figure 11. Efficiency vs. output power
@ 3.6 V and 8 Ω
Figure 12. Efficiency vs. output power
@ 2.7 V and 4 Ω
0.09
0.20
100
0.18
0.08
0.07
0.06
60
0.05
40
Power
Dissipation
20
0
0.0
0.2
Vcc = 3.6V
F = 1kHz
RL = 8Ω + ≥ 15μ H
THD+N ≤ 10%
BW ≤ 30kHz
TAMB = 25°C
0.4
0.6
Output Power (W)
0.8
0.04
0.03
0.02
80
0.10
0
0.0
0.00
1.0
Efficiency (%)
0.035
60
0.030
0.025
0
0.0
0.1
0.2
0.3
Output Power (W)
Vcc = 2.7V
F = 1kHz
RL = 8 Ω + ≥ 15μ H
THD+N ≤ 10%
BW ≤ 30kHz
TAMB = 25°C
0.4
0.5
0.2
0.3
0.4
0.5
0.6
Output Power (W)
0.7
0.8
0.020
0.015
0.010
0.005
0.000
F = 1kHz
BW < 30kHz
2.5 T
= 25°C
AMB
RL=4Ω +≥ 15μH
1.5
1.0
RL=8Ω +≥ 15μH
0.5
0.0
2.5
3.0
3.5
4.0
4.5
5.0
10
RL = 4Ω + 15 μ H
F = 100Hz
G = +6dB
BW < 30kHz
1 TAMB = 25°C
RL=4Ω +≥ 15μH
THD + N (%)
Output power at 10% THD + N (W)
Figure 16. THD+N vs. output power
@ 4 Ω and 100 Hz
2.5
2.0
1.5
Vcc=5V
Vcc=4.2V
Vcc=3.6V
Vcc=3V
Vcc=2.7V
0.1
RL=8Ω +≥ 15μH
0.5
0.0
18/33
2.5
3.0
3.5
4.0
4.5
Power supply voltage (V)
5.0
0.02
2.0
Figure 15. Output power vs. power supply
voltage @ 10% THD+N
1.0
0.04
0.00
0.9
Power supply voltage (V)
3.5 F = 1kHz
BW < 30kHz
3.0 TAMB = 25°C
0.06
3.0
Output power at 1% THD + N (W)
0.040
Efficiency
0.1
0.08
Figure 14. Output power vs. power supply
voltage @ 1% THD+N
0.045
20
Power
Dissipation
20
0.050
Power
Dissipation
Vcc = 2.7V
F = 1kHz
RL = 4Ω + ≥ 15μ H
THD+N ≤ 10%
BW ≤ 30kHz
TAMB = 25°C
40
0.01
100
40
0.12
60
Figure 13. Efficiency vs. output power
@ 2.7 V and 8 Ω
80
0.16
Efficiency
0.14
Efficiency (%)
Efficiency
Power Dissipation (W)
Efficiency (%)
80
Power Dissipation (W)
100
5.5
0.01
0.01
0.1
Output power (W)
DocID14937 Rev 4
1
5.5
TS2007FC
Electrical characteristics
Figure 17. THD+N vs. output power
@ 8 Ω and 100 kHz
Figure 18. THD+N vs. frequency
@ 4 Ω and 1 kHz
10
10
RL = 4Ω + 15μ H
F = 1kHz
G = +6dB
BW < 30kHz
1 TAMB = 25°C
Vcc=5V
Vcc=4.2V
Vcc=3.6V
THD + N (%)
THD + N (%)
RL = 8Ω + 15 μ H
F = 100Hz
G = +6dB
BW < 30kHz
1 TAMB = 25°C
Vcc=3V
Vcc=2.7V
0.1
Vcc=4.2V
Vcc=3.6V
Vcc=3V
Vcc=2.7V
0.1
Vcc=5V
0.01
0.01
0.1
0.01
0.01
1
0.1
Figure 19. THD+N vs. output power
@ 8 Ω and 1 kHz
Figure 20. THD+N vs. frequency
@ 5 V and 4 Ω
10
10
Vcc = 5V
RL = 4Ω + 15μ H
G = +6dB
BW < 30kHz
1 TAMB = 25°C
Vcc=4.2V
Vcc=3.6V
Vcc=3V
THD + N (%)
RL = 8Ω + 15μ H
F = 1kHz
G = +6dB
BW < 30kHz
1 Tamb = 25°C
THD + N (%)
1
Output power (W)
Output power (W)
Vcc=2.7V
0.1
Po=1400mW
0.1
Po=700mW
Vcc=5V
0.01
0.01
0.1
0.01
1
100
Output power (W)
Figure 21. THD+N vs. frequency
@ 5 V and 8 Ω
10000
Figure 22. THD+N vs. frequency
@ 4.2 V and 4 Ω
10
10
Vcc = 4.2V
RL = 4Ω + 15μ H
G = +6dB
BW < 30kHz
1 TAMB = 25°C
Po=900mW
THD + N (%)
Vcc = 5V
RL = 8Ω + 15μ H
G = +6dB
BW < 30kHz
1 TAMB = 25°C
THD + N (%)
1000
Frequency (Hz)
0.1
Po=1000mW
0.1
Po=450mW
Po=500mW
0.01
100
1000
10000
0.01
Frequency (Hz)
100
1000
10000
Frequency (Hz)
DocID14937 Rev 4
19/33
33
Electrical characteristics
TS2007FC
Figure 23. THD+N vs. frequency
@ 4.2 V and 8 Ω
Figure 24. THD+N vs. frequency
@ 3.6 V and 4 Ω
10
10
Vcc = 3.6V
RL = 4Ω + 15μ H
G = +6dB
BW < 30kHz
1 TAMB = 25°C
Po=600mW
THD + N (%)
THD + N (%)
Vcc = 4.2V
RL = 8Ω + 15μ H
G = +6dB
BW < 30kHz
1 TAMB = 25°C
0.1
0.1
Po=300mW
0.01
100
1000
Po=350mW
0.01
10000
100
Frequency (Hz)
10
Vcc = 3V
RL = 4Ω + 15μ H
G = +6dB
BW < 30kHz
1 TAMB = 25°C
THD + N (%)
THD + N (%)
Vcc = 3.6V
RL = 8Ω + 15μ H
G = +6dB
BW < 30kHz
1 TAMB = 25°C
Po=400mW
0.1
100
1000
Po=250mW
0.01
10000
100
Frequency (Hz)
1000
10000
Frequency (Hz)
Figure 27. THD+N vs. frequency
@ 3 V and 8 Ω
Figure 28. THD+N vs. frequency
@ 2.7 V and 4 Ω
10
10
Vcc = 2.7V
RL = 4Ω + 15μ H
G = +6dB
BW < 30kHz
1 TAMB = 25°C
Po=300mW
THD + N (%)
Vcc = 3V
RL = 8Ω + 15μ H
G = +6dB
BW < 30kHz
1 TAMB = 25°C
THD + N (%)
Po=500mW
0.1
Po=200mW
Po=150mW
0.1
100
1000
10000
Po=400mW
Po=200mW
0.1
0.01
Frequency (Hz)
20/33
10000
Figure 26. THD+N vs. frequency
@ 3 V and 4 Ω
10
0.01
1000
Frequency (Hz)
Figure 25. THD+N vs. frequency
@ 3.6 V and 8 Ω
0.01
Po=700mW
100
1000
Frequency (Hz)
DocID14937 Rev 4
10000
TS2007FC
Electrical characteristics
Figure 29. THD+N vs. frequency @ 2.7 V and 8 Ω
Figure 30. PSRR vs. frequency
10
0
Inputs grounded
Vcc = 5V, 4.2V, 3.6V, 3V, 2.7V
Vripple = 200mVpp
CIN = 1μ F
-10
Po=250mW
-20
RL = ≥ 4 Ω + ≥ 15μ H
TAMB = 25 °C
-30
PSRR (dB)
THD + N (%)
Vcc = 2.7V
RL = 8Ω + 15μ H
G = +6dB
BW < 30kHz
1 TAMB = 25°C
Po=125mW
0.1
-40
-50
G=+6dB
G=+12dB
-60
-70
0.01
100
1000
-80
10000
100
1000
Frequency (Hz)
Frequency (Hz)
Figure 31. PSRR vs. common mode input
voltage @ +6 dB gain
Figure 32. PSRR vs. common mode input
voltage @ +12 dB gain
0
0
Vripple = 200mVpp
G = +6dB
F = 217Hz
RL = ≥ 4 Ω + ≥ 15μ H
TAMB = 25°C
-20
PSRR (dB)
-30
-20
-30
-40
Vcc=3V
-50
Vcc=4.2V
Vcc=2.7V
-60
Vripple = 200mVpp
G = +12dB
F = 217Hz
RL = ≥ 4Ω + ≥ 15μ H
TAMB = 25°C
-10
PSRR (dB)
-10
-70
Vcc=3.6V
0
1
2
Vcc=5V
3
4
Vcc=3V
-40
Vcc=5V
Vcc=2.7V
-50
-60
-70
-80
-90
10000
Vcc=3.6V
-80
-90
5
Vcc=4.2V
0
1
Common Mode Input Voltage (V)
2
3
4
5
Common Mode Input Voltage (V)
Figure 33. CMRR vs. frequency
Figure 34. CMRR vs. common mode input
voltage @ +6 dB gain
0
Δ Vicm = 200mVpp
-10
-20
0
G = +6dB, +12dB
Cin = 4.7μ F
RL = ≥ 4Ω + ≥ 15μ H
Tamb = 25°C
Δ Vic = 200mVpp
-10
-20
-40
CMRR (dB)
CMRR (dB)
-30
-50
G = +6dB
F = 217Hz
RL = ≥ 4Ω + ≥ 15μ H
TAMB = 25°C
Vcc=5V, 4.2V, 3.6V, 3V, 2.7V
-60
-30
Vcc=3V
-40
Vcc=4.2V
Vcc=2.7V
-50
-60
-70
Vcc=3.6V
-70
-80
Vcc=5V
100
1000
Frequency (dB)
10000
-80
0
1
2
3
4
5
Common Mode Input Voltage (V)
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33
Electrical characteristics
TS2007FC
Figure 35. CMRR vs. common mode input
voltage @ +12 dB gain
Figure 36. Gain vs. frequency
@ +6 dB gain
8
0
Δ Vic = 200mVpp
-30
6
5
Vcc=3.6V
Vcc=3V
Gain (dB)
CMRR (dB)
-20
-40
Vcc=2.7V
-50
-60
RL=8 Ω +15μ H
4
RL=8 Ω +30μ H
3
RL=4 Ω +30μ H
2
-70
-80
No load
7
G = +12dB
F = 217Hz
RL = ≥ 4Ω + ≥ 15 μ H
TAMB = 25°C
-10
0
1
2
3
4
0
5
RL=4Ω +15μ H
Set Gain = +6dB
Vin = 500mVpp
TAMB = 25 °C
1
Vcc=5V
Vcc=4.2V
100
1000
Common Mode Input Voltage (V)
Figure 37. Gain vs. frequency
@ +12 dB gain
Figure 38. Output offset vs. common mode
input voltage @ 5 V
14
10
No load
13
12
1
RL=8Ω +15μ H
10
|Voo| (mV)
Gain (dB)
11
RL=8Ω +30μ H
9
RL=4 Ω +30μ H
8
6
100
1000
0.01
1E-3
0.0
10000
Vcc = 5V
RL = 8Ω + 15μ H
TAMB = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Figure 40. Output offset vs. common mode
input voltage @ 2.7 V
10
10
1
1
|Voo| (mV)
|Voo| (mV)
Figure 39. Output offset vs. common mode
input voltage @ 3.6 V
G=+6dB
G=+12dB
0.01
1E-3
0.0
G=+12dB
Common Mode Input Voltage (V)
Frequency (Hz)
0.1
G=+6dB
0.1
RL=4 Ω +15μ H
Set Gain = +12dB
Vin = 500mVpp
TAMB = 25°C
7
G=+6dB
0.1
G=+12dB
0.01
Vcc = 3.6V
RL = 8 Ω + 15μ H
TAMB = 25 °C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1E-3
0.0
Common Mode Input Voltage (V)
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10000
Frequency (Hz)
Vcc = 2.7V
RL = 8Ω + 15μ H
TAMB = 25°C
0.5
1.0
1.5
2.0
Common Mode Input Voltage (V)
DocID14937 Rev 4
2.5
TS2007FC
Electrical characteristics
Flip-Chip Package Power Dissipation (W)
Figure 41. Power derating curves
Figure 42. Startup and shutdown phase
VCC = 5 V, G = 6 dB, Cin = 1 µF, inputs grounded
1.6
1.4
Vo1
Mounted on a 4-layer PCB
1.2
Vo2
1.0
0.8
Standby
0.6
0.4
Vo1 - Vo2
No Heat sink
AMR value
0.2
0.0
0
25
50
75
100
Ambiant Temperature (°C)
125
150
Figure 43. Startup and shutdown phase
VCC = 5 V, G = 6 dB, Cin = 1 µF, Vin = 1 Vpp,
F = 10 kHz
Figure 44. Startup and shutdown phase
VCC = 5 V, G = 12 dB, Cin = 1 µF, Vin = 1 Vpp,
F = 10 kHz
Vo1
Vo1
Vo2
Vo2
Standby
Standby
Vo1 - Vo2
Vo1 - Vo2
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Application information
TS2007FC
4
Application information
4.1
Differential configuration principle
The TS2007FC is a monolithic, fully-differential input/output, class-D power amplifier. It
includes a common mode feedback loop that controls the output bias value to average it at
VCC/2 in the range of DC common mode input voltage. This allows the device to always
have a maximum output voltage swing, and consequently, maximizes the output power. In
addition, as the load is connected differentially compared to a single-ended topology, the
output is four times higher for the same power supply voltage.
A fully-differential amplifier has the following advantages:
4.2
•
High PSRR (power supply rejection ratio)
•
High CMRR (common mode noise rejection
•
Virtually zero pop without additional circuitry, giving a faster startup time than
conventional single-ended input amplifiers
•
Easy interfacing with a differential output audio DAC
•
No input coupling capacitors required since there is a common mode feedback loop
Gain settings
In the flat region of the frequency-response curve (no input coupling capacitor or internal
feedback loop + load effect), the differential gain can be set to either 6 or 12 dB depending
on the logic level of the GS pin.
Table 11. GS pin gains
GS pin
Gain (dB)
Gain (V/V)
1
6 dB
2
0
12 dB
4
Note:
Between the GS pin and VCC there is an internal 300 kΩ resistor. When the pin is floating
the gain is 6 dB. In standby mode, this internal resistor is disconnected (HiZ input).
4.3
Common mode feedback loop limitations
The common mode feedback loop allows the output DC bias voltage to be averaged at
VCC/2 for any DC common mode bias input voltage.
Due to the Vicm limitation of the input stage (see Table 2: Operating conditions), the common
mode feedback loop can fulfill its role only within the defined range.
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TS2007FC
4.4
Application information
Low frequency response
If a low frequency bandwidth limitation is required, it is possible to use input coupling
capacitors. In the low frequency region, the input coupling capacitor Cin has a greater effect.
Cin and the input impedance Zin form a first-order high-pass filter with a -3 dB cutoff
frequency (see Table 5 to Table 9).
1
F CL = -----------------------------------2 ⋅ π ⋅ Z in ⋅ C in
where FCL = cutoff frequency
So, for a desired cutoff frequency we can calculate Cin as follows:
1
C in = -------------------------------------2 ⋅ π ⋅ Z in ⋅ F CL
where FCL is expressed in Hz, Zin in Ω, and Cin in F.
The input impedance, Zin, is for the whole power supply voltage range, typically 75 kΩ.
There is also a tolerance around the typical value (see Table 5 to Table 9). The tolerance of
FCL can also be calculated:
4.5
•
FCLmax = 1.103 ⋅ FCL
•
FCLmin = 0.915 ⋅ FCL
Circuit decoupling
A power supply capacitor, referred to as CS, is needed to correctly bypass the TS2007FC.
The TS2007FC has a typical switching frequency of 280 kHz and an output fall and rise time
of less than or equal to 5 ns. Due to these very fast transients, careful decoupling is
mandatory.
A 1 µF ceramic capacitor is enough, but it must be located very close to the TS2007FC in
order to avoid any extra parasitic inductance created by a long track wire. Parasitic loop
inductance, in relation with di/dt, introduces overvoltage that decreases the global efficiency
of the device and may cause, if this parasitic inductance is too high, a TS2007FC
breakdown. For filtering low frequency noise signals on the power line, it is recommended to
use a capacitor of at least 1 µF.
In addition, even if a ceramic capacitor has an adequate high frequency ESR (equivalent
series resistance) value, its current capability is also important. A 0603 size is a good
compromise, particularly when a 4 Ω load is used.
Another important parameter is the rated voltage of the capacitor. A 1 µF/6.3 V capacitor
used at 5 V, can loose about 50% of its value. With a power supply voltage of 5 V, the
decoupling value, instead of 1 µF, can be reduced to 0.5 µF. As CS has particular influence
on the THD+N in the medium to high frequency region, this capacitor variation becomes
decisive. In addition, less decoupling means higher overshoots which can be problematic if
they reach the power supply AMR value (6 V).
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Application information
4.6
TS2007FC
Wakeup time (twu)
When the standby is released to set the device ON, there is a wait of 1 ms typically. The
TS2007FC has an internal digital delay that mutes the outputs and releases them after this
time in order to avoid any pop noise.
Note:
The gain increases smoothly (see Figure 43 and Figure 44) from the mute to the gain
selected by the GS pin (Section 4.2).
4.7
Shutdown time
When the standby command is set to high, the time required to put the two output stages
into high impedance and to put the internal circuitry in shutdown mode, is typically 1 ms.
This time is used to decrease the gain and avoid any pop noise during shutdown.
Note:
The gain decreases smoothly until the outputs are muted (see Figure 43 and Figure 44).
4.8
Consumption in shutdown mode
Between the shutdown pin and GND there is an internal 300 kΩ resistor. This resistor forces
the TS2007FC to be in shutdown when the shutdown input is left floating.
However, this resistor also introduces additional shutdown power consumption if the
shutdown pin voltage does not equal 0 V. This extra current is provided by the device that
drives the standby pin of the amplifier.
Referring to Table 2: Operating conditions, with a 0.4 V shutdown voltage pin for example,
you must add 0.4 V/300 k = 1.3 µA in typical (0.4 V/273 k = 1.46 µA maximum) to the
shutdown current specified in Table 5 to Table 9.
4.9
Single-ended input configuration
It is possible to use the TS2007FC in a single-ended input configuration. However, input
coupling capacitors are needed in this configuration. The following schematic diagram
shows a typical single-ended input application.
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DocID14937 Rev 4
TS2007FC
Application information
Figure 45. Typical application for single-ended input configuration
VCC
Cs
Gain select control
Input
B2
A2
1uF
Vcc
GS
Cin
C1
IN-
A1
IN+
Gain
Select
TS2007FC
+
Speaker
OUT+ C3
PWM
H
Bridge
A3
OUT-
Cin
Oscillator
Protection
Circuit
Gnd
B3
C2
Standby
Control
Standby
Standby control
4.10
Output filter considerations
The TS2007FC is designed to operate without an output filter. However, due to very sharp
transients on the TS2007FC output, EMI radiated emissions may cause some standard
compliance issues.
These EMI standard compliance issues can appear if the distance between the TS2007FC
outputs and loudspeaker terminal are long (typically more than 50 mm, or 100 mm in both
directions). As the PCB layout and internal equipment device are different for each
configuration, it is difficult to provide a one-size-fits-all solution.
However, to decrease the probability of EMI issues, there are several simple rules to follow:
•
Reduce, as much as possible, the distance between the TS2007FC output pins and the
speaker terminals
•
Use a ground plane for shielding sensitive wires
•
Place, as close as possible to the TS2007FC and in series with each output, a ferrite
bead with a rated current of minimum 2.5 A and impedance greater than 50 Ω at
frequencies above 30 MHz
•
Allow an extra footprint to place, if necessary, a capacitor to short perturbations to
ground (Figure 46)
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Application information
TS2007FC
Figure 46. Ferrite chip bead placement
From TS2007FC output Ferrite chip bead
to speaker
about 100pF
gnd
In the case where the distance between the TS2007FC output and the speaker terminals is
too long, it is possible to have low frequency EMI issues due to the fact that the typical
operating PWM frequency is 280 kHz and the fall and rise time of the output signal is less
than or equal to 5 ns. In this configuration, it is necessary to use the output filter shown in
Figure 47, that consists of L1, C1, L2, and C2 as close as possible to the TS2007FC
outputs.
When an output filter is used and there exists a possibility to disconnect a load, it is
recommended to use an RC network that consists of C3 and R as shown in Figure 47. In
this case, when the output filter is connected without any load, the filter acts like a shortcircuit for input frequencies above 10 kHz. The RC network corrects the frequency response
of the output filter and compensates this limitation.
Table 12. Example of component choice
Component
L1
L2
C1
RL = 4 Ω
RL = 8 Ω
15 μH/1.4 A
30 μH/0.7 A
2 μF/10 V
C2
C3
1 μF/10 V
R
22 Ω/0.25 W
1 μF/10 V
47 Ω/0.25 W
Figure 47. LC output filter with RC network
LC Output Filter
RC network
OUT+
L1
C1
C3
from TS2007FC
OUT-
28/33
RL
L2
C2
DocID14937 Rev 4
R
TS2007FC
4.11
Application information
Short-circuit protection
The TS2007FC includes an output short-circuit protection. This protection prevents the
device from being damaged if there are fault conditions on the amplifier outputs.
When a channel is in operating mode and a short-circuit occurs directly between two
outputs (Out+ and Out-) or between an output and ground (Out+ and GND or Out- and
GND), the short-circuit protection detects this situation and puts the amplifier into standby.
To put the amplifier back into operating mode, put the standby pin to logical LO and then to
logical HI.
4.12
Thermal shutdown
The TS2007FC device has an internal thermal shutdown protection in the event of extreme
temperatures to protect the device from overheating. Thermal shutdown is active when the
device reaches 150 °C. When the temperature decreases to a safe level, the circuit
switches back to normal operation.
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Package information
5
TS2007FC
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
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TS2007FC
5.1
Package information
9-bump Flip-chip package information
Figure 48. 9-bump Flip-chip package outline
1.57 mm
1.57 mm
0.5mm
0.5mm
∅ 0.25mm
40µm
600µm
1. Die size: 1.57 mm x 1.57 mm ±30 µm
Die height (including bumps): 600 µm
Bump diameter: 315 µm ±50 µm
Bump diameter before reflow: 300 µm ±10 µm
Bump height: 250 µm ±40 µm
Die height: 350 µm ±20 µm
Pitch: 500 µm ±50 µm
Back coating layer height (optional): 40 µm ±10 µm
Coplanarity: 50 µm max.
Figure 49. 9-bump Flip-chip marking (top view)
(5)
(6)
(1)
(2)
07 X (3)
YWW (4)
GAMS1312131712CB
1. Logo: ST
2. First two digits for part number: 07
3. Third digit for assembly plant: X
4. Three digit date code: YWW
5. Dot indicates pin A1
6. “E” symbol for lead free
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Ordering information
6
TS2007FC
Ordering information
Table 13. Order codes
7
Order code
Temperature range
Package
Marking
TS2007EIJT
-40° C to +85° C
Flip-chip
07
Revision history
Table 14. Document revision history
32/33
Date
Revision
Changes
19-Aug-2008
1
Initial release.
17-May-2011
2
Added minimum RL to Table 1: Absolute maximum ratings (AMR)
Updated ECOPACK® paragraph in Section 5: Package information
Minor textual updates
28-Feb-2014
3
Removed pinout from cover page and added it to Section 2:
Application information.
Table 1: Absolute maximum ratings (AMR): updated
Updated following figure titles: Figure 8 through to Figure 29;
Figure 31 and Figure 32; Figure 34 through to Figure 40.
Section 5.1: 9-bump Flip-chip package information: updated section
layout.
Figure 49: 9-bump Flip-chip marking (top view): changed marking
from “K7” to “07”.
Table 13: Order codes: updated order code markings
15-Apr-2019
4
Removed the part number TS2007EKIJT.
DocID14937 Rev 4
TS2007FC
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