TS274ACN

TS274 High performance CMOS quad operational amplifier Features ■ ■ ■ ■ ■ Output voltage can swing to ground Excellent phase margin on capacitive loads Gain bandwidth product: 3.5 MHz Unity gain stable Two input offset voltage selections SO-14 (Plastic micropackage) DIP14 (Plastic package) Description The TS274 devices are low cost, quad operational amplifiers designed to operate with single or dual supplies. These operational amplifiers use the ST silicon gate CMOS process giving an excellent consumption-speed ratio. These series are ideally suited for low consumption applications. Three power consumptions are available thus offering the best consumption-speed ratio for your application: ■ ■ ■ TSSOP14 (Thin shrink small outline package) Pin connections (top view) Output 1 1 Inverting Input 1 2 Non-inverting Input 1 3 VCC + 4 Non-inverting Input 2 5 Inverting Input 2 6 Output 2 7 + + + + 14 Output 4 13 Inverting Input 4 12 Non-inverting Input 4 11 VCC 10 Non-inverting Input 3 9 8 Inverting Input 3 Output 3 ICC = 10 µA/amp: TS27L4 (very low power) ICC = 150 µA/amp: TS27M4 (low power) ICC = 1 mA/amp: TS274 (standard) These CMOS amplifiers offer very high input impedance and extremely low input currents. The major advantage versus JFET devices is the very low input currents drift with temperature (see Figure 5 on page 6). For enhanced features of TS274, in particular railto-rail capability and low offset voltage, two new Table 1. Part number TSV914 TSV994 families, TSV91x and TSV99x will better suit low voltage applications. Enhanced related families VCC range (V) 2.5 - 5.5 2.5 - 5.5 Rail-torail I/O I/O I/O Vio max (mV) 1.5/4.5 1.5/4.5 Iib max (pA) 10 10 Avd min (dB) 80 80 ICC max (mA) 1.1 1.1 GBP typ (MHz) 8 20 (G ≥3) SR typ (V/µs) 4.5 10 Packages SO-14, TSSOP14 SO-14, TSSOP14 February 2008 Rev 3 1/14 www.st.com 14 Absolute maximum ratings and operating conditions TS274 1 Absolute maximum ratings and operating conditions Table 2. Symbol VCC+ Vid Vin Io Iin Toper Tstg Absolute maximum ratings (AMR) Parameter Supply voltage (1) Differential input voltage Input voltage (3) (2) TS274C/AC 18 ±18 TS274I/AI Unit V V V mA mA -0.3 to 18 ±30 ±5 0 to +70 -40 to +125 Output current for VCC+ ≥ 15V Input current Operating free-air temperature range Storage temperature range Thermal resistance junction to ambient(4) SO-14 TSSOP14 DIP14 Thermal resistance junction to case SO-14 TSSOP14 DIP14 HBM: human body model(5) °C °C -65 to +150 103 100 80 31 32 33 500 100 (7) Rthja °C/W Rthjc °C/W V V V ESD MM: machine model(6) CDM: charged device model 800 1. All values, except differential voltage are with respect to network ground terminal. 2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. 3. The magnitude of the input and the output voltages must never exceed the magnitude of the positive supply voltage. 4. Short-circuits can cause excessive heating and destructive dissipation. Values are typical. 5. Human body model: A 100pF capacitor is charged to the specified voltage, then discharged through a 1.5kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. 6. Machine model: A 200pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5Ω). This is done for all couples of connected pin combinations while the other pins are floating. 7. Charged device model: all pins and the package are charged together to the specified voltage and then discharged directly to the ground through only one pin. This is done for all pins. Table 3. Symbol VCC+ Vicm Toper Operating conditions Parameter Supply voltage Common mode input voltage range Operating free-air temperature range TS274C TS274I 0 to Value 3 to 16 VCC+ - 1.5 Unit V V °C 0 to 70 -40 to 125 2/14 TS274 Block diagram and circuit schematics 2 Block diagram and circuit schematics Figure 1. Block diagram VCC Current source xI Input differential Second stage Output stage Output VCC E E 3/14 4/14 Figure 2. VCC Block diagram and circuit schematics T24 T 25 T 26 T6 T8 T27 T5 T 10 T 15 R2 T 28 T1 Input R1 C1 Input T2 T11 T 12 Schematic diagram (for 1/4 TS274) T17 T 18 T7 T 23 T3 Output T19 T4 T16 T9 T 13 T 14 T20 T 22 T21 T29 VCC TS274 TS274 Electrical characteristics 3 Table 4. Symbol Electrical characteristics VCC+ = +10V, VCC-= 0V, Tamb = +25°C (unless otherwise specified) TS274C/AC Parameter Conditions Min Vo = 1.4V, Vic = 0V TS274C/I TS274AC/AI Vio Input offset voltage Tmin ≤ Tamb ≤ Tmax TS274C/I TS274AC/AI 2 Vic = 5V, Vo = 5V Tmin ≤ Tamb ≤ Tmax Vic = 5V, Vo = 5V Tmin ≤ Tamb ≤ Tmax Vid = 100mV, RL = 10kΩ Tmin ≤ Tamb ≤ Tmax Vid = -100mV ViC = 5V, RL = 10kΩ, Vo = 1V to 6V Tmin ≤ Tamb ≤ Tmax Av = 40dB, RL = 10kΩ, CL = 100pF, fin = 100kHz Vic = 1V to 7.4V, Vo = 1.4V VCC+ = 5V to 10V, Vo = 1.4V Av = 1, no load, Vo = 5V Tmin ≤ Tamb ≤ Tmax 65 60 10 7 3.5 80 70 1000 1500 1600 60 45 5.5 40 30 f = 1kHz, Rs = 100Ω 30 120 65 60 15 8.2 8.1 1 100 1 150 8.4 50 10 6 3.5 80 70 1000 1500 1700 60 45 5.5 40 30 30 120 MHz dB dB µA mA mA V/µs Degrees % nV/√Hz dB 15 V/mV 8.2 8 8.4 50 1 300 Typ Max Min Typ Max TS274I/AI Unit 1.1 0.9 10 5 12 6.5 1.1 0.9 10 5 12 6.5 mV mV µV/°C DVio Iio Iib VOH VOL Avd Input offset voltage drift Input offset current (1) Input bias current (1) High level output voltage Low level output voltage Large signal voltage gain 2 1 200 pA pA V mV GBP CMR SVR ICC Io Isink SR φm KOV en Gain bandwidth product Common mode rejection ratio Supply voltage rejection ratio Supply current (per amplifier) Output short circuit current Vo = 0V, Vid = 100mV Output sink current Slew rate at unity gain Phase margin at unity gain Overshoot factor Equivalent input noise voltage Vo = VCC, Vid = -100mV , RL = 10kΩ CL = 100pF, Vin = 3 to 7V Av = 40dB, RL = 10kΩ , CL = 100pF Vo1/Vo2 Channel separation 1. Maximum values including unavoidable inaccuracies of the industrial test. 5/14 Electrical characteristics TS274 Figure 3. SUPPLY CURRENT, I CC (µ A) 2.0 1.5 1.0 0.5 Supply current (each amplifier) vs. Figure 4. supply voltage Tamb = 25°C AV = 1 VO = VCC / 2 OUTPUT VOLTAGE, V OH (V) 20 16 12 8 4 0 -50 High level output voltage vs. high level output current T amb = 25˚C V id = 100mV VCC = 16V VCC = 10V 0 4 8 12 SUPPLY VOLTAGE, VCC (V) 16 -40 -30 -20 OUTPUT CURRENT, I -10 OH (mA) 0 Figure 5. INPUT BIAS CURRENT, I IB (pA) 100 Input bias current vs. free-air temperature VCC = 10V Vic = 5V Figure 6. OUTPUT VOLTAGE, V OL (V) 1.0 0.8 0.6 0.4 0.2 Low level output voltage vs. low level output current V CC = 3V V CC = 5V 10 T amb = 25°C V ic = 0.5V V id = -100mV 1 2 OUTPUT CURRENT, I OL (mA) 3 1 25 50 75 100 125 TEMPERATURE, T amb (˚C) 0 Figure 7. 5 4 3 2 1 0 High level output voltage vs. high level output current Figure 8. OUTPUT VOLTAGE, VOL (V) 3 Low level output voltage vs. low level output current V CC = 10V VCC = 16V OUTPUT VOLTAGE, V OH (V) T amb = 25˚C V id = 100mV VCC = 5V 2 1 VCC = 3V T amb = 25°C V i = 0.5V V = -100mV id -10 -8 -6 -4 -2 OUTPUT CURRENT, I OH (mA) 0 0 4 8 12 16 OUTPUT CURRENT, I OL (mA) 20 6/14 TS274 Electrical characteristics Figure 9. 50 Open loop frequency response and Figure 10. Phase margin vs. capacitive load phase shift P H A S E M A R G IN , φ m (D e g re e s ) 70 Ta m b = 2 5 °C R L = 10k Ω AV = 1 VC C = 10V G A IN 30 P H A S E (D e g re e s ) 40 PHASE T a m b = 2 5 °C V C C+ = 1 0 V R L = 10k Ω C L = 100pF A VC L = 100 2 3 4 Phase Margin 0 45 90 135 60 G A IN (d B ) 20 10 0 -1 0 10 50 40 Gain Bandwidth Product 10 10 5 10 6 10 180 30 0 20 40 60 L 10 7 80 (p F ) 100 F R E Q U E N C Y , f (H z ) C A P A C IT A N C E , C Figure 11. Gain bandwidth product vs. supply Figure 12. Slew rate vs. supply voltage voltage G A IN B A N D W . P R O D ., G B P (M H z ) 5 7 S L E W R A T E S , S R (V / μ s ) 4 3 6 5 4 3 2 Ta m b = 2 5 °C R L = 10k Ω CL = 1 0 0 p F SR 2 1 Ta m b = 2 5 °C R L = 10k Ω CL = 1 0 0 p F AV = 1 4 8 12 16 SR 0 4 S U P P L Y V O L T A G E , V C C (V ) 6 8 10 12 S U P P L Y V O L T A G E , VC C 14 (V ) 16 Figure 13. Phase margin vs. supply voltage P H A S E M A R G IN , φ m (D e g re e s ) 48 44 40 Figure 14. Input voltage noise vs. frequency E Q U IV A L E N T IN P U T N O IS E V O L T A G E (n V /V H z ) 300 VC C = 1 0 V Tamb = 2 5 °C 200 R S = 1 0 0Ω 36 32 28 Ta m b = 2 5 °C R L = 10k Ω CL = 1 0 0 p F AV = 1 0 4 8 12 16 100 0 1 10 100 1000 F R E Q U E N C Y (H z ) S U P P L Y V O L T A G E , V C C (V ) 7/14 Macromodel TS274 4 4.1 Macromodel Important note concerning this macromodel Please consider the following remarks before using this macromodel. ● ● ● All models are a trade-off between accuracy and complexity (i.e. simulation time). Macromodels are not a substitute to breadboarding; rather, they confirm the validity of a design approach and help to select surrounding component values. A macromodel emulates the nominal performance of a typical device within specified operating conditions (temperature, supply voltage, for example). Thus the macromodel is often not as exhaustive as the datasheet, its purpose is to illustrate the main parameters of the product. Data derived from macromodels used outside of the specified conditions (VCC, temperature, for example) or even worse, outside of the device operating conditions (VCC, Vicm, for example), is not reliable in any way. 4.2 Macromodel code ******************************** .SUBCKT TS27X 1 2 3 4 5 *** INP- = 1, INP+ =2, OUT = 3 VDD=4 VSS = 5 *** TYPE = TS271/TS272/TS274 .MODEL MDTH D IS=1E-8 KF=2.664E-16 CJO=10F ***INPUT STAGE CIP 2 5 1E-12 CIN 1 5 1E-12 EIP 10 5 2 5 1 EIN 16 5 1 5 1 RIP 10 11 8 RIN 15 16 8 RIS 11 15 223.84 CPS 11 15 1E-9 DIP 11 120 MDTH 400E-12 DIN 15 140 MDTH 400E-12 RDEG1 12 120 4400 RDEG2 14 140 4400 VOFP 12 13 DC 0 VOFN 13 14 DC 0 IPOL 13 5 38E-6 ***ICC DICC1 4 31 MDTH 400E-12 DICC2 31 32 MDTH 400E-12 DICC3 32 33 MDTH 400E-12 DICC4 33 34 MDTH 400E-12 RICC 34 5 20E3 ICC 4 5 600E-6 ***COMMON MODE INPUT LIMITATION DINN 17 13 MDTH 400E-12 VIN 17 5 DC -0.1 8/14 TS274 DINR 15 18 MDTH 400E-12 VIP 4 18 DC 2.2 ***GM1 STAGE FGM1P 119 5 VOFP 1 FGM1N 119 5 VOFN 1 RAP 119 4 1E6 RAN 119 5 1E6 ***GM2 STAGE G2P 19 5 119 5 4E-4 G2N 19 5 119 4 4E-4 R2P 19 4 450E3 R2N 19 5 450E3 ***COMPENSATION CC 19 119 7p ***BUFFER EBUF 20 5 19 5 1 ***SHORT-CIRCUIT LIMITATIONS( ISINK, ISOURCE) DOPM 19 22 MDTH 400E-12 DONM 21 19 MDTH 400E-12 HOPM 22 28 VOUT 910 VIPM 28 4 DC 50 HONM 21 27 VOUT 1222 VINM 5 27 DC 50 VOUT 3 23 DC 0 ***VOH, VOL DEFINITIONS DOP 19 25 MDTH 400E-12 VOP 4 25 2.5 DON 24 19 MDTH 400E-12 VON 24 5 0.92 ***OUTPUT RESISTOR ROUT 23 20 10 .ENDS Macromodel 9/14 Package information TS274 5 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 5.1 DIP14 package information Figure 15. DIP14 package mechanical drawing Table 5. Ref. DIP14 package mechanical data Millimeters Min. Typ. Max. Min. 0.020 1.65 0.5 0.25 20 8.5 2.54 15.24 7.1 5.1 3.3 1.27 2.54 0.050 0.130 0.100 0.335 0.100 0.600 0.280 0.201 0.055 0.020 0.010 0.787 0.065 Inches Typ. Max. a1 B b b1 D E e e3 F I L Z 0.51 1.39 10/14 TS274 Package information 5.2 SO-14 package information Figure 16. SO-14 package mechanical drawing Table 6. SO-14 package mechanical data Dimensions Ref. Min. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 8.55 5.8 0.35 0.19 0.1 Millimeters Typ. Max. 1.75 0.2 1.65 0.46 0.25 0.5 45° (typ.) 8.75 6.2 1.27 7.62 4.0 5.3 1.27 0.68 8° (max.) 0.149 0.181 0.019 0.336 0.228 0.013 0.007 0.003 Min. Inches Typ. Max. 0.068 0.007 0.064 0.018 0.010 0.019 0.344 0.244 0.050 0.300 0.157 0.208 0.050 0.026 11/14 Package information TS274 5.3 TSSOP14 package information Figure 17. TSSOP14 package mechanical drawing A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 Figure 18. TSSOP14 package mechanical data Dimensions Ref. Min. A A1 A2 b c D E E1 e K L1 0° 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8° 0.75 0° 0.018 0.024 1 Millimeters Typ. Max. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8° 0.030 0.004 0.039 Min. Inches Typ. Max. 0.047 0.006 0.041 0.012 0.0089 0.201 0.260 0.176 12/14 TS274 Ordering information 6 Ordering information Table 7. Order codes Temperature range Package Packing Marking Order code TS274CD TS274CDT 274C SO-14 Tube or Tape & reel 274AC 0°C, +70°C DIP14 Tube TS274ACN 274C TSSOP14 Tape & reel 274AC 274I SO-14 Tube or Tape & reel 274AI -40°C, +125°C DIP14 Tube TS274AIN 274I TSSOP14 Tape & reel 274AI TS274IN TS274CN TS274ACD TS274ACDT TS274CN TS274ACN TS274CPT TS274ACPT TS274ID TS274IDT TS274AID TS274AIDT TS274IN TS274AIN TS274IPT TS274AIPT 7 Revision history Table 8. Date 19-Nov-2001 Document revision history Revision 1 Initial release. ESD protection inserted in Table 2. on page 2. Thermal resistance junction to case information added see Table 2. on page 2. Macromodel insertion in Section 4 on page 8. Added information on enhanced related families of devices on cover page. Removed TS274B version in AMR table and in order codes table. Changes 07-Apr-2006 2 01-Feb-2008 3 13/14 TS274 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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