TS274
High performance CMOS quad operational amplifier
Features
■
Output voltage can swing to ground
■
Excellent phase margin on capacitive loads
■
Gain bandwidth product: 3.5 MHz
■
Unity gain stable
■
Two input offset voltage selections
DIP14
(Plastic package)
Description
SO-14
(Plastic micropackage)
The TS274 devices are low cost, quad
operational amplifiers designed to operate with
single or dual supplies. These operational
amplifiers use the ST silicon gate CMOS process
giving an excellent consumption-speed ratio.
These series are ideally suited for low
consumption applications.
TSSOP14
(Thin shrink small outline package)
Three power consumptions are available thus
offering the best consumption-speed ratio for your
application:
■
ICC = 10 µA/amp: TS27L4 (very low power)
■
ICC = 150 µA/amp: TS27M4 (low power)
■
ICC = 1 mA/amp: TS274 (standard)
Pin connections (top view)
-
-
13 Inverting Input 4
+
+
12 Non-inverting Input 4
11 VCC -
Non-inverting Input 2 5
+
+
10 Non-inverting Input 3
Inverting Input 2 6
-
-
9
Inverting Input 3
8
Output 3
Output 2 7
For enhanced features of TS274, in particular railto-rail capability and low offset voltage, two new
Part
number
Inverting Input 1 2
Non-inverting Input 1 3
VCC + 4
These CMOS amplifiers offer very high input
impedance and extremely low input currents. The
major advantage versus JFET devices is the very
low input currents drift with temperature (see
Figure 5 on page 6).
Table 1.
14 Output 4
Output 1 1
families, TSV91x and TSV99x will better suit low
voltage applications.
Enhanced related families
VCC
range (V)
Rail-torail I/O
Vio max
(mV)
Iib max
(pA)
Avd min
(dB)
ICC max
(mA)
GBP typ
(MHz)
SR typ
(V/µs)
TSV914
2.5 - 5.5
I/O
1.5/4.5
10
80
1.1
8
4.5
SO-14,
TSSOP14
TSV994
2.5 - 5.5
I/O
1.5/4.5
10
80
1.1
20
(G ≥3)
10
SO-14,
TSSOP14
February 2008
Rev 3
Packages
1/14
www.st.com
14
Absolute maximum ratings and operating conditions
1
TS274
Absolute maximum ratings and operating conditions
Table 2.
Absolute maximum ratings (AMR)
Symbol
VCC+
Vid
Parameter
TS274C/AC
Supply voltage (1)
Differential input voltage
Unit
18
V
±18
V
-0.3 to 18
V
(2)
(3)
TS274I/AI
Vin
Input voltage
Io
Output current for VCC+ ≥ 15V
±30
mA
Iin
Input current
±5
mA
Toper
Operating free-air temperature range
Tstg
Storage temperature range
Rthja
Thermal resistance junction to ambient(4)
SO-14
TSSOP14
DIP14
103
100
80
Rthjc
Thermal resistance junction to case
SO-14
TSSOP14
DIP14
31
32
33
°C/W
HBM: human body model(5)
500
V
100
V
800
V
ESD
MM: machine
0 to +70
-40 to +125
°C
-65 to +150
model(6)
(7)
CDM: charged device model
°C
°C/W
1. All values, except differential voltage are with respect to network ground terminal.
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.
3. The magnitude of the input and the output voltages must never exceed the magnitude of the positive
supply voltage.
4. Short-circuits can cause excessive heating and destructive dissipation. Values are typical.
5. Human body model: A 100pF capacitor is charged to the specified voltage, then discharged through a
1.5kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.
6. Machine model: A 200pF capacitor is charged to the specified voltage, then discharged directly between
two pins of the device with no external series resistor (internal resistor < 5Ω). This is done for all couples of
connected pin combinations while the other pins are floating.
7. Charged device model: all pins and the package are charged together to the specified voltage and then
discharged directly to the ground through only one pin. This is done for all pins.
Table 3.
Operating conditions
Symbol
Value
Unit
Supply voltage
3 to 16
V
Vicm
Common mode input voltage range
VCC+
V
Toper
Operating free-air temperature range
TS274C
TS274I
VCC+
2/14
Parameter
0 to
- 1.5
0 to 70
-40 to 125
°C
TS274
2
Block diagram and circuit schematics
Block diagram and circuit schematics
Figure 1.
Block diagram
VCC
Current
source
xI
Input
differential
Second
stage
Output
stage
Output
VCC
E
E
3/14
4/14
T20
T19
T21
T 18
R2
T 25
VCC
T 22
T 23
T 26
T29
T 28
T27
Input
T3
T1
T5
T4
T2
C1
Input
R1
T7
T6
T9
T8
T 13
T11
T 10
T 14
T 12
T16
Output
T 15
Figure 2.
T17
T24
VCC
Block diagram and circuit schematics
TS274
Schematic diagram (for 1/4 TS274)
TS274
Electrical characteristics
3
Electrical characteristics
Table 4.
VCC+ = +10V, VCC-= 0V, Tamb = +25°C (unless otherwise specified)
TS274C/AC
Symbol
Parameter
Unit
Min
Vo = 1.4V, Vic = 0V
TS274C/I
TS274AC/AI
Vio
DVio
Input offset voltage
Typ
1.1
0.9
Tmin ≤ Tamb ≤ Tmax
TS274C/I
TS274AC/AI
Max Min Typ
10
5
1.1
0.9
12
6.5
Input offset voltage drift
2
Iio
Input offset current (1)
Vic = 5V, Vo = 5V
Tmin ≤ Tamb ≤ Tmax
1
Iib
Input bias current (1)
Vic = 5V, Vo = 5V
Tmin ≤ Tamb ≤ Tmax
1
VOH
High level output voltage
Vid = 100mV, RL = 10kΩ
Tmin ≤ Tamb ≤ Tmax
VOL
Low level output voltage
Vid = -100mV
Avd
Large signal voltage gain
ViC = 5V, RL = 10kΩ,
Vo = 1V to 6V
Tmin ≤ Tamb ≤ Tmax
mV
12
6.5
mV
µV/°C
200
1
8.4
300
8.2
8
8.4
50
10
10
5
1
150
8.2
8.1
Max
2
100
15
pA
V
50
10
pA
mV
15
V/mV
7
6
GBP
Gain bandwidth product
Av = 40dB, RL = 10kΩ,
CL = 100pF, fin = 100kHz
CMR
Common mode rejection
ratio
Vic = 1V to 7.4V, Vo = 1.4V
65
80
SVR
Supply voltage rejection
ratio
VCC+ = 5V to 10V, Vo = 1.4V
60
70
Supply current (per
amplifier)
Av = 1, no load, Vo = 5V
Tmin ≤ Tamb ≤ Tmax
ICC
TS274I/AI
Conditions
3.5
1000 1500
1600
3.5
MHz
65
80
dB
60
70
dB
1000 1500
1700
µA
Output short circuit current Vo = 0V, Vid = 100mV
60
60
mA
Isink
Output sink current
Vo = VCC, Vid = -100mV
45
45
mA
SR
Slew rate at unity gain
RL = 10kΩ, CL = 100pF,
Vin = 3 to 7V
5.5
5.5
V/µs
φm
Phase margin at unity gain
Av = 40dB, RL = 10kΩ,
CL = 100pF
40
40
Degrees
KOV
Overshoot factor
30
30
%
30
30
nV/√Hz
120
120
dB
Io
en
Equivalent input noise
voltage
f = 1kHz, Rs = 100Ω
Vo1/Vo2 Channel separation
1. Maximum values including unavoidable inaccuracies of the industrial test.
5/14
Electrical characteristics
Tamb = 25°C
AV = 1
VO = VCC / 2
1.5
1.0
0.5
0
4
8
12
SUPPLY VOLTAGE, VCC (V)
Figure 5.
INPUT BIAS CURRENT, I IB (pA)
OUTPUT VOLTAGE, V OH (V)
2.0
Supply current (each amplifier) vs. Figure 4.
supply voltage
Input bias current vs. free-air
temperature
16
VCC = 10V
Vic = 5V
10
12
4
0
-50
0.8
Figure 8.
T amb = 25˚C
V id = 100mV
4
3
VCC = 5V
2
VCC = 3V
1
0
6/14
OUTPUT VOLTAGE, VOL (V)
OUTPUT VOLTAGE, V OH (V)
5
-10
-8
-6
-4
-2
OUTPUT CURRENT, I OH (mA)
0
V CC = 3V
V CC = 5V
T amb = 25°C
V ic = 0.5V
V id = -100mV
0.2
TEMPERATURE, T amb (˚C)
Figure 7.
0
0.4
High level output voltage vs. high
level output current
100
-10
OH (mA)
Low level output voltage vs. low
level output current
0.6
0
75
-40
-30
-20
OUTPUT CURRENT, I
1.0
125
50
VCC = 10V
8
1
25
T amb = 25˚C
V id = 100mV
VCC = 16V
Figure 6.
100
High level output voltage vs. high
level output current
20
16
OUTPUT VOLTAGE, VOL (V)
SUPPLY CURRENT, I CC (µ A)
Figure 3.
TS274
3
1
2
OUTPUT CURRENT, I OL (mA)
Low level output voltage vs. low
level output current
V CC = 10V
VCC = 16V
2
1
3
T amb = 25°C
V i = 0.5V
V = -100mV
id
0
4
8
12
16
OUTPUT CURRENT, I OL (mA)
20
TS274
Electrical characteristics
Open loop frequency response and Figure 10. Phase margin vs. capacitive load
phase shift
40
0
G A IN
G A IN (d B )
30
45
PHASE
20
Phase
Margin
T a m b = 2 5 °C
V C C+ = 1 0 V
R L = 10kΩ
C L = 100pF
A VC L = 100
10
0
135
10
10
3
180
Gain
Bandwidth
Product
-1 0
2
90
10
4
10
5
10
6
10
P H A S E (D e g re e s )
50
P H A S E M A R G IN , φ m (D e g re e s )
Figure 9.
70
Ta m b = 2 5 °C
R L = 10kΩ
AV = 1
VC C = 10V
60
50
40
30
7
0
20
40
60
C A P A C IT A N C E , C
F R E Q U E N C Y , f (H z )
80
L
100
(p F )
7
5
S L E W R A T E S , S R (V / μs )
G A IN B A N D W . P R O D ., G B P (M H z )
Figure 11. Gain bandwidth product vs. supply Figure 12. Slew rate vs. supply voltage
voltage
4
3
2
Ta m b = 2 5 °C
R L = 10kΩ
CL = 1 0 0 p F
AV = 1
1
4
0
8
12
4
SR
3
4
6
8
10
12
S U P P L Y V O L T A G E , VC C
S U P P L Y V O L T A G E , V C C (V )
48
44
40
36
Ta m b = 2 5 °C
R L = 10kΩ
CL = 1 0 0 p F
AV = 1
32
28
0
4
8
12
S U P P L Y V O L T A G E , V C C (V )
16
14
(V )
16
Figure 14. Input voltage noise vs. frequency
E Q U IV A L E N T IN P U T N O IS E
V O L T A G E (n V /V H z )
P H A S E M A R G IN , φ m (D e g re e s )
Figure 13. Phase margin vs. supply voltage
SR
5
2
16
Ta m b = 2 5 °C
R L = 10kΩ
CL = 1 0 0 p F
6
300
VC C = 1 0 V
Tamb = 2 5 °C
R S = 1 0 0Ω
200
100
0
1
10
100
1000
F R E Q U E N C Y (H z )
7/14
Macromodel
TS274
4
Macromodel
4.1
Important note concerning this macromodel
Please consider the following remarks before using this macromodel.
●
All models are a trade-off between accuracy and complexity (i.e. simulation time).
●
Macromodels are not a substitute to breadboarding; rather, they confirm the validity of
a design approach and help to select surrounding component values.
●
A macromodel emulates the nominal performance of a typical device within specified
operating conditions (temperature, supply voltage, for example). Thus the
macromodel is often not as exhaustive as the datasheet, its purpose is to illustrate the
main parameters of the product.
Data derived from macromodels used outside of the specified conditions (VCC, temperature,
for example) or even worse, outside of the device operating conditions (VCC, Vicm, for
example), is not reliable in any way.
4.2
Macromodel code
********************************
.SUBCKT TS27X 1 2 3 4 5
*** INP- = 1, INP+ =2, OUT = 3 VDD=4 VSS = 5
*** TYPE = TS271/TS272/TS274
.MODEL MDTH D IS=1E-8 KF=2.664E-16 CJO=10F
***INPUT STAGE
CIP 2 5 1E-12
CIN 1 5 1E-12
EIP 10 5 2 5 1
EIN 16 5 1 5 1
RIP 10 11 8
RIN 15 16 8
RIS 11 15 223.84
CPS 11 15 1E-9
DIP 11 120 MDTH 400E-12
DIN 15 140 MDTH 400E-12
RDEG1 12 120 4400
RDEG2 14 140 4400
VOFP 12 13 DC 0
VOFN 13 14 DC 0
IPOL 13 5 38E-6
***ICC
DICC1 4 31 MDTH 400E-12
DICC2 31 32 MDTH 400E-12
DICC3 32 33 MDTH 400E-12
DICC4 33 34 MDTH 400E-12
RICC 34 5 20E3
ICC 4 5 600E-6
***COMMON MODE INPUT LIMITATION
DINN 17 13 MDTH 400E-12
VIN 17 5 DC -0.1
8/14
TS274
Macromodel
DINR 15 18 MDTH 400E-12
VIP 4 18 DC 2.2
***GM1 STAGE
FGM1P 119 5 VOFP 1
FGM1N 119 5 VOFN 1
RAP 119 4 1E6
RAN 119 5 1E6
***GM2 STAGE
G2P 19 5 119 5 4E-4
G2N 19 5 119 4 4E-4
R2P 19 4 450E3
R2N 19 5 450E3
***COMPENSATION
CC 19 119 7p
***BUFFER
EBUF 20 5 19 5 1
***SHORT-CIRCUIT LIMITATIONS( ISINK, ISOURCE)
DOPM 19 22 MDTH 400E-12
DONM 21 19 MDTH 400E-12
HOPM 22 28 VOUT 910
VIPM 28 4 DC 50
HONM 21 27 VOUT 1222
VINM 5 27 DC 50
VOUT 3 23 DC 0
***VOH, VOL DEFINITIONS
DOP 19 25 MDTH 400E-12
VOP 4 25 2.5
DON 24 19 MDTH 400E-12
VON 24 5 0.92
***OUTPUT RESISTOR
ROUT 23 20 10
.ENDS
9/14
Package information
5
TS274
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
5.1
DIP14 package information
Figure 15. DIP14 package mechanical drawing
Table 5.
DIP14 package mechanical data
Millimeters
Inches
Ref.
Min.
a1
0.51
B
1.39
Typ.
Min.
Typ.
Max.
0.020
1.65
0.055
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
15.24
0.600
F
7.1
0.280
I
5.1
0.201
L
Z
10/14
Max.
3.3
1.27
0.130
2.54
0.050
0.100
TS274
5.2
Package information
SO-14 package information
Figure 16. SO-14 package mechanical drawing
Table 6.
SO-14 package mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
A
a1
Inches
Max.
Min.
Typ.
1.75
0.1
0.2
a2
Max.
0.068
0.003
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45° (typ.)
D
8.55
8.75
0.336
0.344
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
7.62
0.300
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.68
0.026
8° (max.)
11/14
Package information
5.3
TS274
TSSOP14 package information
Figure 17. TSSOP14 package mechanical drawing
A
A2
A1
e
b
K
L
c
E
D
E1
PIN 1 IDENTIFICATION
1
Figure 18. TSSOP14 package mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
A
Max.
Min.
Typ.
1.2
A1
0.05
A2
0.8
b
Max.
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0089
D
4.9
5
5.1
0.193
0.197
0.201
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
e
12/14
Inches
1
0.65 BSC
K
0°
L1
0.45
0.60
0.0256 BSC
8°
0°
0.75
0.018
8°
0.024
0.030
TS274
6
Ordering information
Ordering information
Table 7.
Order codes
Order code
Temperature
range
Package
Packing
SO-14
Tube or
Tape & reel
TS274CD
TS274CDT
274C
TS274ACD
TS274ACDT
274AC
0°C, +70°C
TS274CN
TS274ACN
TS274CN
DIP14
Tube
TS274ACN
274C
TS274CPT
TS274ACPT
TSSOP14
Tape & reel
274AC
TS274ID
TS274IDT
274I
SO-14
TS274AID
TS274AIDT
Tube or
Tape & reel
274AI
-40°C, +125°C
TS274IN
TS274AIN
TS274IN
DIP14
Tube
TS274AIN
274I
TS274IPT
TS274AIPT
7
Marking
TSSOP14
Tape & reel
274AI
Revision history
Table 8.
Document revision history
Date
Revision
Changes
19-Nov-2001
1
Initial release.
07-Apr-2006
2
ESD protection inserted in Table 2. on page 2.
Thermal resistance junction to case information added see Table 2.
on page 2.
Macromodel insertion in Section 4 on page 8.
01-Feb-2008
3
Added information on enhanced related families of devices on cover
page.
Removed TS274B version in AMR table and in order codes table.
13/14
TS274
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14/14
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