TS27L2AC

TS27L2C,I,M PRECISION VERY LOW POWER CMOS DUAL OPERATIONAL AMPLIFIERS s VERY LOW POWER CONSUMPTION : 10µA/op s OUTPUT VOLTAGE CAN SWING TO GROUND s EXCELLENT PHASE MARGIN ON CAPACITIVE LOADS s STABLE AND LOW OFFSET VOLTAGE s THREE INPUT OFFSET VOLTAGE SELECTIONS DESCRIPTION These devices are low cost, low power dual operational amplifiers designed to operate with single or dual supplies. These operational amplifiers use the ST silicon gate CMOS process allowing an excellent consumption-speed ratio. These series are ideally suited for low consumption applications. Three power consumptions are available allowing to have always the best consumption-speed ratio: N DIP8 (Plastic Package) D SO8 (Plastic Micropackage) P TSSOP8 (Thin Shrink Small Outline Package) u ICC = 10µA/amp.: TS27L2 (very low power) u ICC = 150µA/amp.: TS27M2 (low power) u ICC = 1mA/amp.: TS272 (standard) These CMOS amplifiers offer very high input impedance and extremely low input currents. The major advantage versus JFET devices is the very low input currents drift with temperature (see figure 2). ORDER CODE Package Part Number Temperature Range N TS27L2C/AC/BC 0°C, +70°C TS27L2I/AI/BI -40°C, +125°C TS27L2M/AM/BM -55°C, +125°C Example : TS27L2ACN • • • D • • • P • • • PIN CONNECTIONS (top view) 1 2 3 4 + + 8 7 6 5 N = Dual in Line Package (DIP) D = Small Outline Package (SO) - also available in Tape & Reel (DT) P = T hin Shrink Small Outline Package (TSSOP) - only available in Tape & Reel (PT) 1 - Output 1 2 - Inverting Input 1 3 - Non-inverting Input 1 4 - V CC 5 - Non-inverting Input 2 6 - Inverting Input 2 7 - Output 2 8 - V CC + November 2001 1/9 TS27L2C,I,M BLOCK DIAGRAM VCC Current source xI Input differential Second stage Output stage Output VCC E E ABSOLUTE MAXIMUM RATINGS Symbol VCC Vid Vi Io Iin Toper Tstg + Parameter Supply Voltage 3) 1) 2) TS27L2C/AC/BC TS27L2I/AI/BI 18 ±18 -0.3 to 18 ±30 ±5 TS27L2M/AM/BM Unit V V V mA mA Differential Input Voltage Input Voltage Output Current for VCC+ ≥ 15V Input Current Operating Free-Air Temperature Range Storage Temperature Range 0 to +70 -40 to +125 -65 to +150 -55 to +125 °C °C 1. All values, except differential voltage are with respect to network ground terminal. 2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. 3. The magnitude of the input and the output voltages must never exceed the magnitude of the positive supply voltage. OPERATING CONDITIONS Symbol VCC+ Vicm Supply Voltage Common Mode Input Voltage Range Parameter Value 3 to 16 0 to VCC+ - 1.5 Unit V V 2/9 VCC T24 T 25 T 26 T6 T8 T27 T5 T 10 T 15 SCHEMATIC DIAGRAM (for 1/2 TS27L2) R2 T 28 T1 Input T 18 T2 Input R1 C1 T11 T 12 T17 T7 T 23 T3 Output T19 T4 T16 T9 T 13 T 14 T20 T 22 T21 T29 VCC TS27L2C,I,M 3/9 TS27L2C,I,M ELECTRICAL CHARACTERISTICS VCC+ = +10V, VCC-= 0V, Tamb = +25°C (unless otherwise specified) TS27L2C/AC/BC Symbol Parameter Min. Input Offset Voltage VO = 1.4V, Vic = 0V Vio Tmin ≤ Tamb ≤ Tmax TS27L2C/I/M TS27L2AC/AI/AM TS27L2B/C/I/M TS27L2C/I/M TS27L2AC/AI/AM TS27L2B/C/I/M Typ. 1.1 0.9 0.25 Max. 10 5 2 12 6.5 3 TS27L2I/AI/BI TS27L2M/AM/BM Min. Typ. Max. 10 5 2 12 6.5 3.5 Unit 1.1 0.9 0.25 mV DVio Iio Input Offset Voltage Drift Input Offset Current note 1) Vic = 5V, VO = 5V Tmin ≤ Tamb ≤ Tmax Input Bias Current - see note 1 Vic = 5V, VO = 5V Tmin ≤ Tamb ≤ Tmax High Level Output Voltage Vid = 100mV, RL = 1MΩ Tmin ≤ Tamb ≤ Tmax Low Level Output Voltage Vid = -100mV Large Signal Voltage Gain ViC = 5V, RL = 1MΩ, Vo = 1V to 6V Tmin ≤ Tamb ≤ Tmax Gain Bandwidth Product Av = 40dB, RL = 1MΩ, CL = 100pF, fin = 100kHz Common Mode Rejection Ratio ViC = 1V to 7.4V, Vo = 1.4V Supply Voltage Rejection Ratio VCC+ = 5V to 10V, Vo = 1.4V Supply Current (per amplifier) Av = 1, no load, Vo = 5V Tmin ≤ Tamb ≤ Tmax Output Short Circuit Current Vo = 0V, Vid = 100mV Output Sink Current Vo = VCC, Vid = -100mV Slew Rate at Unity Gain RL = 1MΩ, CL = 100pF, Vi = 3 to 7V Phase Margin at Unity Gain Av = 40dB, RL = 1MΩ, CL = 100pF Overshoot Factor Equivalent Input Noise Voltage f = 1kHz, Rs = 100Ω Channel Separation 65 60 60 45 8.8 8.7 2 1 100 1 150 9 8.8 8.6 50 100 60 40 2 1 200 1 300 9 µV/°C pA Iib pA VOH VOL Avd V 50 100 mV V/mV GBP CMR SVR 0.1 80 80 10 15 17 65 60 0.1 80 80 10 15 18 MHz dB dB ICC Io Isink SR φm KOV en Vo1/Vo2 1. µA 60 45 0.04 45 30 68 120 60 45 0.04 45 30 68 120 mA mA V/µs Degrees % nV ----------Hz dB Maximum values including unavoidable inaccuracies of the industrial test. 4/9 TS27L2C,I,M TYPICAL CHARACTERISTICS Figure 1 : Supply Current (each amplifier) versus Supply Voltage 20 Figure 3b : High Level Output Voltage versus High Level Output Current 20 OUTPUT VOLTAGE, V OH (V) SUPPLY CURRENT, I CC (µA) 15 Tamb = 25 °C AV = 1 VO = VCC / 2 Tamb = 25° C 16 12 8 4 0 -50 V id = 100mV VCC = 16V 10 VCC = 10V 5 0 4 8 12 16 SUPPLY VOLTAGE, VCC (V) -40 -30 -20 -10 OUTPUT CURRENT, I OH (mA) 0 Figure 2 : Input Bias Current versus Free Air Temperature 100 Figure 4a : Low Level Output Voltage versus Low Level Output Current 1 .0 O U T P U T V O L T A G E , V O L (V ) INPUT BIAS CURRENT, IIB (pA) VCC = 10V V i = 5V 0 .8 0 .6 0 .4 0 .2 V CC = 3V V CC = 5V 10 T amb = 2 5 °C V ic = 0 .5 V V id = -1 0 0 m V 1 2 3 1 25 50 100 TEMPERATURE, Tamb (°C) 75 125 0 O U T P U T C U R R E N T , I O L (m A ) Figure 3a : High Level Output Voltage versus High Level Output Current 5 Figure 4b : Low Level Output Voltage versus Low Level Output Current 3 O U T P U T V O L T A G E , V OL (V ) OUTPUT VOLTAGE, VOH (V) 4 3 2 1 0 -10 Tamb = 25° C V id = 100mV VCC= 5V V C C = 10V 2 VC C = 1 6 V 1 T amb = 2 5 °C V i = 0 .5 V Vid = -1 0 0 m V VCC = 3V -8 -6 -4 -2 0 0 4 8 12 16 20 OUTPUT CURRENT, I OH (mA) O U T P U T C U R R E N T , I OL (m A ) 5/9 TS27L2C,I,M Figure 5 : Open Loop Frequency Response and Phase Shift Figure 8 : Phase Margin versus Capacitive Load P H A S E M A R G IN , φ m (D e g re e s ) 80 T amb = 2 5 °C R L = 1MΩ AV = 1 V CC= 1 0 V 50 P H A S E (D e g re e s ) 40 G A IN 0 45 Phase Margin 90 135 70 G A IN (d B ) 30 PHASE T amb = 2 5 °C V CC+ = 1 0 V R L = 1 MΩ C L = 100pF A VCL = 1 0 0 2 3 4 20 10 0 -1 0 10 60 50 Gain Bandwidth Product 10 10 5 10 6 10 180 10 7 40 0 20 40 60 80 (p F ) 100 F R E Q U E N C Y , f (H z ) C A P A C IT A N C E , C L Figure 6 : Gain Bandwidth Product versus Supply Voltage G A IN B A N D W . P R O D ., G B P (M H z ) 120 100 80 Figure 9 : Slew Rate versus Supply Voltage S L E W R A T E S , S R (V /µ s ) T amb = 2 5 °C R L = 1M Ω C = 100pF L AV = 1 0 .0 5 T amb = 2 5 °C R L = 1M Ω C = 100pF L 0 .0 4 SR 60 40 SR 0 .0 3 0 .0 2 0 4 8 12 16 4 6 8 10 12 14 S U P P L Y V O L T A G E , VCC (V ) 16 S U P P L Y V O L T A G E , V CC (V ) Figure 7 : Phase Margin versus Supply Voltage Figure 10 : Input Voltage Noise versus Frequency 300 VCC = 1 0 V Tamb= 2 5 °C 200 R S= 1 0 0 Ω P H A S E M A R G IN , φ m (D e g re e s ) 60 T amb = 2 5 °C R L = 1 MΩ C = 100pF L AV = 1 E Q U IV A L E N T IN P U T N O IS E V O L T A G E (n V /V H z ) 50 40 100 30 0 4 8 12 16 0 1 10 100 1000 F R E Q U E N C Y (H z ) S U P P L Y V O L T A G E , V CC (V ) 6/9 TS27L2C,I,M PACKAGE MECHANICAL DATA 8 PINS - PLASTIC DIP Millimeters Dim. Min. A a1 B b b1 D E e e3 e4 F i L Z 0.51 1.15 0.356 0.204 7.95 2.54 7.62 7.62 6.6 5.08 3.81 1.52 Typ. 3.32 1.65 0.55 0.304 10.92 9.75 0.020 0.045 0.014 0.008 0.313 Max. Min. Inches Typ. 0.131 0.065 0.022 0.012 0.430 0.384 0.100 0.300 0.300 0260 0.200 0.150 0.060 Max. 3.18 0.125 7/9 TS27L2C,I,M PACKAGE MECHANICAL DATA 8 PINS - PLASTIC MICROPACKAGE (SO) L C a3 b1 c1 a2 b e3 A s E D M 8 5 F 1 4 Millimeters Dim. Min. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 0.1 0.65 0.35 0.19 0.25 4.8 5.8 1.27 3.81 3.8 0.4 4.0 1.27 0.6 8° (max.) 0.150 0.016 Typ. Max. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45° (typ.) 5.0 6.2 0.189 0.228 Min. 0.004 0.026 0.014 0.007 0.010 a1 Inches Typ. Max. 0.069 0.010 0.065 0.033 0.019 0.010 0.020 0.197 0.244 0.050 0.150 0.157 0.050 0.024 8/9 TS27L2C,I,M PACKAGE MECHANICAL DATA 8 PINS - THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) k c 0.25mm .010 inch GAGE PLANE L1 L L L1 E1 SEATING PLANE A A2 A1 5 D b 8 8 C E 4 e 5 PIN 1 IDENTIFICATION Millimeters Dim. Min. A A1 A2 b c D E E1 e k l L L1 0.05 0.80 0.19 0.09 2.90 4.30 0° 0.50 0.45 Typ. Max. 1.20 0.15 1.05 0.30 0.20 3.10 4.50 8° 0.75 0.75 Min. 0.01 0.031 0.007 0.003 0.114 0.169 0° 0.09 0.018 1 4 1 Inches Typ. Max. 0.05 0.006 0.041 0.15 0.012 0.122 0.177 8° 0.030 0.030 1.00 0.039 3.00 6.40 4.40 0.65 0.60 0.600 1.000 0.118 0.252 0.173 0.025 0.0236 0.024 0.039 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States © http://www.st.com 9/9