TS27L4AMDT

TS27L4C,I,M PRECISION VERY LOW POWER CMOS QUAD OPERATIONAL AMPLIFIER ■ VERY LOW POWER CONSUMPTION : 10µA/op ■ OUTPUT VOLTAGE CAN SWING TO GROUND ■ EXCELLENT PHASE MARGIN ON CAPACITIVE LOADS N DIP14 (Plastic Package) ■ STABLE AND LOW OFFSET VOLTAGE ■ THREE INPUT OFFSET VOLTAGE SELECTIONS DESCRIPTION These devices are low cost, low power quad operational amplifiers designed to operate with single or dual supplies. These operational amplifiers use the ST silicon gate CMOS process allowing an excellent consumption-speed ratio. These series are ideally suited for low consumption applications. Three power consumptions are available allowing to have always the best consumption-speed ratio: D SO14 (Plastic Micropackage) P TSSOP14 (Thin Shrink Small Outline Package) ❑ ICC = 10µA/amp.: TS27L4 (very low power) ❑ ICC = 150µA/amp.: TS27M4 (low power) ❑ ICC = 1mA/amp.: TS274 (standard) PIN CONNECTIONS (top view) These CMOS amplifiers offer very high input impedance and extremely low input currents. The major advantage versus JFET devices is the very low input currents drift with temperature (see figure 2). Output 1 1 ORDER CODE Package Part Number Temperature Range TS27L4C/AC/BC 0°C, +70°C TS27L4I/AI/BI* -40°C, +125°C TS27L4M/AM/BM -55°C, +125°C Example : TS27L4ACN N D P • • • • • • • • • 14 Output 4 Inverting Input 1 2 - - 13 Inverting Input 4 Non-inverting Input 1 3 + + 12 Non-inverting Input 4 11 VCC - VCC + 4 Non-inverting Input 2 5 + + 10 Non-inverting Input 3 Inverting Input 2 6 - - 9 Inverting Input 3 8 Output 3 Output 2 7 N = Dual in Line Package (DIP) D = Small Outline Package (SO) - also available in Tape & Reel (DT) P = Thin Shrink Small Outline Package (TSSOP) - only available in Tape & Reel (PT) * TS27L4BID : For delivery information, please contact your ST sales representative or distributor. June 2003 1/9 TS27L4C,I,M BLOCK DIAGRAM VCC Current source xI Input differential Output stage Second stage Output VCC E E ABSOLUTE MAXIMUM RATINGS Symbol VCC + Vid Parameter Supply Voltage TS27L4C/AC/BC 1) Differential Input Voltage 2) 3) TS27L4I/AI/BI TS27L4M/AM/BM Unit 18 V ±18 V -0.3 to 18 V Vi Input Voltage Io Output Current for VCC ≥ 15V ±30 mA Iin Input Current ±5 mA + Toper Operating Free-Air Temperature Range Tstg Storage Temperature Range 0 to +70 -40 to +125 -55 to +125 -65 to +150 °C °C 1. All values, except differential voltage are with respect to network ground terminal. 2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. 3. The magnitude of the input and the output voltages must never exceed the magnitude of the positive supply voltage. OPERATING CONDITIONS Symbol VCC+ Vicm 2/9 Parameter Supply Voltage Common Mode Input Voltage Range Value Unit 3 to 16 V + 0 to VCC - 1.5 V T20 T19 T17 T24 T21 T 18 R2 T 25 VCC T 22 T 23 T 26 T29 T 28 T27 Input T3 T1 T5 VCC T4 T2 C1 Input R1 T7 T6 T9 T8 T 13 T11 T 10 T 14 T 12 T16 Output T 15 TS27L4C,I,M SCHEMATIC DIAGRAM (for 1/4 TS27L4) 3/9 TS27L4C,I,M ELECTRICAL CHARACTERISTICS VCC+ = +10V, VCC-= 0V, Tamb = +25°C (unless otherwise specified) TS27L4C/AC/BC Symbol Parameter Min. Input Offset Voltage VO = 1.4V, Vic = 0V Vio DVio Iio Iib Tmin ≤ Tamb ≤ Tmax TS27L4C/I/M TS27L4AC/AI/AM TS27L4B/C/I/M TS27L4C/I/M TS27L4AC/AI/AM TS27L4B/C/I/M Input Offset Voltage Drift Input Offset Current note Vic = 5V, VO = 5V Tmin ≤ Tamb ≤ Tmax Typ. Max. 1.1 0.9 0.25 10 5 2 12 6.5 3 TS27L4I/AI/BI TS27L4M/AM/BM Min. Typ. 1.1 0.9 0.25 2 2 1 Input Bias Current - see note 1 Vic = 5V, VO = 5V Tmin ≤ Tamb ≤ Tmax High Level Output Voltage Vid = 100mV, RL = 1MΩ Tmin ≤ Tamb ≤ Tmax VOL Low Level Output Voltage Vid = -100mV Avd Large Signal Voltage Gain ViC = 5V, RL = 1MΩ, Vo = 1V to 6V Tmin ≤ Tamb ≤ Tmax 1 1 150 8.8 8.7 9 8.8 8.6 100 9 60 40 100 Common Mode Rejection Ratio ViC = 1V to 7.4V, Vo = 1.4V 65 80 65 80 SVR Supply Voltage Rejection Ratio VCC+ = 5V to 10V, Vo = 1.4V 60 80 60 80 0.1 10 V 50 CMR Supply Current (per amplifier) Av = 1, no load, Vo = 5V Tmin ≤ Tamb ≤ Tmax pA 300 50 60 45 pA 200 Gain Bandwidth Product Av = 40dB, RL = 1MΩ, CL = 100pF, fin = 100kHz V/mV MHz 0.1 15 17 10 mV dB dB 15 18 µA Io Output Short Circuit Current Vo = 0V, Vid = 100mV 60 60 Isink Output Sink Current Vo = VCC, Vid = -100mV 45 45 SR Slew Rate at Unity Gain RL = 1MΩ, CL = 100pF, Vi = 3 to 7V 0.04 0.04 φm Phase Margin at Unity Gain Av = 40dB, RL = 1MΩ, CL = 100pF 45 45 KOV Overshoot Factor 30 30 % Equivalent Input Noise Voltage f = 1kHz, Rs = 100Ω 68 68 nV -----------Hz Channel Separation 120 120 dB en Vo1/Vo2 4/9 mV µV/°C 1 100 GBP 1. 10 5 2 12 6.5 3.5 1) VOH ICC Unit Max. Maximum values including unavoidable inaccuracies of the industrial test. mA mA V/µs Degrees TS27L4C,I,M TYPICAL CHARACTERISTICS 2.0 Tamb = 25°C AV = 1 VO = VCC / 2 1.5 1.0 0.5 0 4 8 12 SUPPLY VOLTAGE, VCC (V) VCC = 10V Vic = 5V 10 1 75 100 VCC = 16V 12 4 0.8 T amb = 25˚C V id = 100mV VCC = 5V 2 0 VCC = 3V -10 -8 -6 -4 -2 OUTPUT CURRENT, I OH (mA) 0 0 V CC = 5V 0.4 T amb = 25°C V ic = 0.5V V id = -100mV 0.2 0 1 2 OUTPUT CURRENT, I OL (mA) 3 Figure 4b : Low Level Output Voltage versus Low Level Output Current OUTPUT VOLTAGE, VOL (V) OUTPUT VOLTAGE, V OH (V) 5 1 -10 OH (mA) V CC = 3V 0.6 125 Figure 3a : High Level Output Voltage versus High Level Output Current 3 -40 -30 -20 OUTPUT CURRENT, I 1.0 TEMPERATURE, T amb (˚C) 4 VCC = 10V 8 Figure 4a : Low Level Output Voltage versus Low Level Output Current 100 50 16 T amb = 25˚C V id = 100mV 0 -50 OUTPUT VOLTAGE, VOL (V) INPUT BIAS CURRENT, I IB (pA) 20 16 Figure 2 : Input Bias Current versus Free Air Temperature 25 Figure 3b : High Level Output Voltage versus High Level Output Current OUTPUT VOLTAGE, V OH (V) SUPPLY CURRENT, I CC (µ A) Figure 1 : Supply Current (each amplifier) versus Supply Voltage 3 V CC = 10V VCC = 16V 2 1 T amb = 25°C V i = 0.5V V = -100mV id 0 4 8 12 16 OUTPUT CURRENT, I OL (mA) 20 5/9 TS27L4C,I,M 40 0 G A IN G A IN (d B ) 30 45 PHASE 20 Phase Margin T amb = 2 5 °C V CC+ = 1 0 V R L = 1 MΩ C L = 100pF A VCL = 1 0 0 10 0 135 2 10 3 180 Gain Bandwidth Product -1 0 10 90 10 4 10 5 10 6 10 P H A S E (D e g re e s ) 50 7 Figure 8 : Phase Margin versus Capacitive Load P H A S E M A R G IN , φ m (D e g re e s ) Figure 5 : Open Loop Frequency Response and Phase Shift 80 T amb = 2 5 °C R L = 1MΩ AV = 1 V CC= 1 0 V 70 60 50 40 0 F R E Q U E N C Y , f (H z ) 20 40 60 80 100 C A P A C IT A N C E , C L (p F ) Figure 9 : Slew Rate versus Supply Voltage 120 100 80 0 .0 5 T amb = 2 5 °C R L = 1M Ω C = 100pF L AV = 1 S L E W R A T E S , S R (V /µ s ) G A IN B A N D W . P R O D ., G B P (M H z ) Figure 6 : Gain Bandwidth Product versus Supply Voltage 60 40 T amb = 2 5 °C R L = 1M Ω C = 100pF L SR 0 .0 4 SR 0 .0 3 0 .0 2 0 4 8 12 4 16 6 8 10 12 14 S U P P L Y V O L T A G E , VCC (V ) 16 S U P P L Y V O L T A G E , V CC (V ) 60 T amb = 2 5 °C R L = 1 MΩ C = 100pF L AV = 1 50 40 30 300 VCC = 10V Tamb = 25˚C R S = 100Ω 200 100 0 0 4 8 12 S U P P L Y V O L T A G E , V CC (V ) 6/9 Figure 10 : Input Voltage Noise versus Frequency EQUIVALENT INPUT NOISE VOLTAGE (nV/VHz) P H A S E M A R G IN , φ m (D e g re e s ) Figure 7 : Phase Margin versus Supply Voltage 16 1 100 10 FREQUENCY (Hz) 1000 TS27L4C,I,M PACKAGE MECHANICAL DATA 14 PINS - PLASTIC DIP Millimeters Inches Dim. Min. a1 B b b1 D E e e3 F i L Z Typ. 0.51 1.39 Max. Min. 1.65 0.020 0.055 0.5 0.25 Typ. 0.065 0.020 0.010 20 0.787 8.5 2.54 15.24 0.335 0.100 0.600 7.1 5.1 0.280 0.201 3.3 1.27 Max. 0.130 2.54 0.050 0.100 7/9 TS27L4C,I,M PACKAGE MECHANICAL DATA 14 PINS - PLASTIC MICROPACKAGE (SO) G c1 s e3 b1 e a1 b A a2 C L E D M 8 1 7 F 14 Millimeters Inches Dim. Min. A a1 a2 b b1 C c1 D (1) E e e3 F (1) G L M S Typ. Max. Min. 1.75 0.2 1.6 0.46 0.25 0.1 0.35 0.19 Typ. 0.069 0.008 0.063 0.018 0.010 0.004 0.014 0.007 0.5 Max. 0.020 45° (typ.) 8.55 5.8 8.75 6.2 0.336 0.228 1.27 7.62 3.8 4.6 0.5 0.344 0.244 0.050 0.300 4.0 5.3 1.27 0.68 0.150 0.181 0.020 0.157 0.208 0.050 0.027 8° (max.) Note : (1) D and F do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.066 inc) ONLY FOR DATA BOOK. 8/9 TS27L4C,I,M PACKAGE MECHANICAL DATA 14 PINS - THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) k c C SEATING PLANE E1 L1 L 0,25 mm .010 inch GAGE PLANE E A A2 7 aaa C D 8 e b A1 14 1 PIN 1 IDENTIFICATION Millimeters Inches Dim. Min. A A1 A2 b c D E E1 e k l 0.05 0.80 0.19 0.09 4.90 4.30 0° 0.50 Typ. 1.00 5.00 6.40 4.40 0.65 0.60 Max. Min. 1.20 0.15 1.05 0.30 0.20 5.10 0.01 0.031 0.007 0.003 0.192 4.50 0.169 8° 0.75 0° 0.09 Typ. 0.039 0.196 0.252 0.173 0.025 0.0236 Max. 0.05 0.006 0.041 0.15 0.012 0.20 0.177 8° 0.030 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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