TS4962MEIKJT

TS4962M 3 W filter-free class D audio power amplifier Datasheet - production data Related products • See TS2007 for further gain settings e.g. 6 or 12 dB • See TS2012 for stereo settings Applications • Portable gaming consoles • VR headsets • Smart phones • Tablets Description The TS4962M is a differential Class-D BTL power amplifier. It is able to drive up to 2.3 W into a 4 Ω load and 1.4 W into a 8 Ω load at 5 V. It achieves outstanding efficiency (88% typ.) compared to classical Class-AB audio amps. Features • Operating from VCC = 2.4 V to 5.5 V • Standby mode active low • Output power: 3 W into 4 Ω and 1.75 W into 8 Ω with 10% THD+N max. and 5 V power supply • Output power: 2.3 W @5 V or 0.75 W @ 3.0 V into 4 Ω with 1% THD+N max. • Output power: 1.4 W @5 V or 0.45 W @ 3.0 V into 8 Ω with 1% THD+N max. The gain of the device can be controlled via two external gain-setting resistors. Pop and click reduction circuitry provides low on/off switch noise while allowing the device to start within 5 ms. A standby function (active low) allows the reduction of current consumption to 10 nA typ. • Adjustable gain via external resistors • Low current consumption 2 mA @ 3 V • Efficiency: 88% typ. • Signal to noise ratio: 85 dB typ. • PSRR: 63 dB typ. @217 Hz with 6 dB gain • PWM base frequency: 250 kHz • Low pop and click noise • Available in Flip Chip 9 x 300 µm (Pb-free) March 2020 This is information on a product in full production. DocID11703 Rev 7 1/41 www.st.com Contents TS4962M Contents 1 Block diagram and pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Application component information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 Differential configuration principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 Gain in typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 Common-mode feedback loop limitations . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4 Low frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.5 Decoupling of the circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.6 Wake-up time (tWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.7 Shutdown time (tSTBY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.8 Consumption in shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.9 Single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.10 Output filter considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.11 Different examples with summed inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 Evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.1 9-bump Flip Chip package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2/41 DocID11703 Rev 7 TS4962M Block diagram and pinout Figure 1. Block diagram B1 B2 Vcc C2 Stdby 300k 1 Block diagram and pinout C1 A1 Internal Bias Out+ 150k C3 Output - InIn+ + PWM H Bridge A3 150k Out- Oscillator GND A2 B3 Figure 2. Pinout (top view) ,1 *1' 287 $ $ $ 9'' 9'' *1' % % % ,1 67%< 287 & & & 1. Legend: IN+ = positive differential input IN- = negative differential input VDD = analog power supply GND = power supply ground STBY = standby pin (active low) OUT+ = positive differential output OUT- = negative differential output 2. Bumps are underneath, bump diameter = 300 µm DocID11703 Rev 7 3/41 41 Application component information 2 TS4962M Application component information Table 1. Component information Component Functional description Cs Bypass supply capacitor. Install as close as possible to the TS4962M to minimize high-frequency ripple. A 100 nF ceramic capacitor should be added to enhance the power supply filtering at high frequency. Rin Input resistor to program the TS4962M differential gain (gain = 300 kΩ/Rin with Rin in kΩ). Input capacitor Due to common-mode feedback, these input capacitors are optional. However, they can be added to form with Rin a 1st order high-pass filter with -3 dB cut-off frequency = 1/(2*π*Rin*Cin). Figure 3. Typical application schematics Vcc B1 Vcc Cs 1u B2 Vcc In+ 300k C2 Stdby GND GND Rin + C1 Differential Input A1 - GND Out+ 150k C3 Output - InIn+ + Rin Input capacitors are optional In- Internal Bias H Bridge PWM SPEAKER A3 150k Out- Oscillator TS4962 GND A2 B3 GND GND Vcc B1 Vcc 300k C2 Stdby GND GND + Rin C1 Differential Input In- - A1 Internal Bias 4 Ohms LC Output Filter GND Out+ 150k C3 15µH Output - InIn+ + PWM 2µF H Bridge Rin Input capacitors are optional GND Cs 1u B2 Vcc In+ GND A3 150k Out- 2µF 15µH Oscillator GND TS4962 B3 A2 30µH GND 1µF GND 1µF 30µH 8 Ohms LC Output Filter 4/41 DocID11703 Rev 7 Load TS4962M 3 Absolute maximum ratings Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Parameter VCC Supply voltage (1) (2) Vin Input voltage (3) Value 6 GND to VCC Toper Operating free-air temperature range -40 to + 85 Tstg Storage temperature -65 to +150 Tj Maximum junction temperature 150 Rthja Thermal resistance junction to ambient 200 Pdiss Power dissipation ESD Human body model ESD Latch-up VSTBY Unit V °C °C/W Internally limited(4) 2 kV Machine model 200 V Latch-up immunity 200 mA GND to VCC V 260 °C Standby pin voltage maximum voltage (5) Lead temperature (soldering, 10 s) 1. Caution: this device is not protected in the event of abnormal operating conditions, such as for example, short-circuiting between any one output pin and ground, between any one output pin and VCC, and between individual output pins. 2. All voltage values are measured with respect to the ground pin. 3. The magnitude of the input signal must never exceed VCC + 0.3 V / GND - 0.3 V. 4. Exceeding the power derating curves during a long period causes abnormal operation. 5. The magnitude of the standby signal must never exceed VCC + 0.3 V / GND - 0.3 V. Table 3. Operating conditions Symbol Parameter VCC Supply voltage (1) VIC Common-mode input voltage range (2) Value 2.4 to 5.5 0.5 to VCC - 0.8 V Standby voltage input: (3) VSTBY RL Rthja Unit 1.4 ≤ VSTBY ≤ VCC GND ≤ VSTBY ≤ 0.4 (4) Device ON Device OFF Load resistor ≥4 Ω Thermal resistance junction to ambient (5) 90 °C/W 1. For VCC from 2.4 V to 2.5 V, the operating temperature range is reduced to 0 °C ≤ Tamb ≤ 70 °C. 2. For VCC from 2.4 V to 2.5 V, the common-mode input range must be set at VCC/2. 3. Without any signal on VSTBY, the device is in standby. 4. Minimum current consumption is obtained when VSTBY = GND. 5. With heat sink surface = 125 mm2. DocID11703 Rev 7 5/41 41 Electrical characteristics 4 TS4962M Electrical characteristics Table 4. VCC = 5 V, GND = 0 V, VIC = 2.5 V, tamb = 25 °C (unless otherwise specified) Symbol ICC Parameter Conditions Supply current (1) Typ. Max. Unit No input signal, no load 2.3 3.3 mA No input signal, VSTBY = GND 10 1000 nA 3 25 mV ISTBY Standby current VOO Output offset voltage No input signal, RL = 8 Ω Output power G=6 dB THD = 1% max., F = 1 kHz, RL = 4 Ω THD = 10% max., F = 1 kHz, RL = 4 Ω THD = 1% max., F = 1 kHz, RL = 8 Ω THD = 10% max., F = 1 kHz, RL = 8 Ω Total harmonic distortion + noise Pout = 900 mWRMS, G = 6 dB, 20 Hz < F < 20 kHz RL = 8 Ω + 15 µH, BW < 30 kHz Pout = 1 WRMS, G = 6 dB, F = 1 kHz, RL = 8 Ω + 15 µH, BW < 30 kHz Pout THD + N Efficiency Efficiency Min. 2.3 3 1.4 1.75 W 1 % 0.4 Pout = 2 WRMS, RL = 4 Ω + ≥ 15 µH Pout =1.2 WRMS, RL = 8 Ω+ ≥ 15 µH 78 88 % PSRR Power supply rejection ratio with inputs grounded (2) F = 21 Hz, RL = 8 Ω, G=6 dB, Vripple = 200 mVpp 63 dB CMRR Common-mode rejection ratio F = 217 Hz, RL = 8 Ω, G = 6 dB, ∆Vicm = 200 mVpp 57 dB Gain value Rin in kΩ Gain 273k Ω -----------------R in 300k Ω -----------------R in 327k Ω -----------------R in V/V RSTBY Internal resistance from Standby to GND 273 300 327 kΩ FPWM Pulse width modulator base frequency 180 250 320 kHz SNR Signal to noise ratio tWU Wake-up time 5 10 ms tSTBY Standby time 5 10 ms 6/41 A-weighting, Pout = 1.2 W, RL = 8 Ω DocID11703 Rev 7 85 dB TS4962M Electrical characteristics Table 4. VCC = 5 V, GND = 0 V, VIC = 2.5 V, tamb = 25 °C (unless otherwise specified) (continued) Symbol VN Parameter Output voltage noise Conditions Min. Typ. F = 20 Hz to 20 kHz, G = 6 dB Unweighted RL = 4 Ω A-weighted RL = 4 Ω 85 60 Unweighted RL = 8 Ω A-weighted RL = 8 Ω 86 62 Unweighted RL = 4 Ω + 15 µH A-weighted RL = 4 Ω + 15 µH 83 60 Unweighted RL = 4 Ω + 30 µH A-weighted RL = 4 Ω + 30 µH 88 64 Unweighted RL = 8 Ω + 30 µH A-weighted RL = 8 Ω + 30 µH 78 57 Unweighted RL = 4 Ω + filter A-weighted RL = 4 Ω + filter 87 65 Unweighted RL = 4 Ω + filter A-weighted RL = 4 Ω + filter 82 59 Max. Unit µVRMS 1. Standby mode is active when VSTBY is tied to GND. 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @ F = 217 Hz. DocID11703 Rev 7 7/41 41 Electrical characteristics TS4962M Table 5. VCC = 4.2V, GND = 0V, VIC = 2.5V, Tamb = 25°C (unless otherwise specified) (1) Symbol Typ. Max. Unit No input signal, no load 2.1 3 mA (2) No input signal, VSTBY = GND 10 1000 nA Output offset voltage No input signal, RL = 8 Ω 3 25 mV Output power G=6dB THD = 1% max, F = 1 kHz, RL = 4 Ω THD = 10% max, F = 1 kHz, RL = 4 Ω THD = 1% max, F = 1 kHz, RL = 8 Ω THD = 10% max, F = 1 kHz, RL = 8 Ω Total harmonic distortion + noise Pout = 600mWRMS, G = 6 dB, 20 Hz < F < 20k Hz RL = 8 Ω + 15 µH, BW < 30 kHz Pout = 700 mWRMS, G = 6 dB, F = 1 kHz, RL = 8 Ω + 15 µH, BW < 30 kHz Efficiency Pout = 1.45 WRMS, RL = 4 Ω + ≥ 15 µH Pout =0.9 WRMS, RL = 8 Ω+ ≥ 15 µH 78 88 % PSRR Power supply rejection ratio with inputs grounded (3) F = 217 Hz, RL = 8 Ω, G=6 dB, Vripple = 200 mVpp 63 dB CMRR Common-mode rejection ratio F = 217 Hz, RL = 8 Ω, G = 6 dB, ∆Vicm = 200 mVpp 57 dB Gain value Rin in kΩ ICC ISTBY VOO Pout THD + N Efficiency Gain 8/41 Parameter Supply current Standby current Conditions Min. 1.6 2 0.95 1.2 W 1 % 0.35 273k Ω -----------------R in 300k Ω -----------------R in 327k Ω -----------------R in V/V RSTBY Internal resistance from Standby to GND 273 300 327 kΩ FPWM Pulse width modulator base frequency 180 250 320 kHz SNR Signal to noise ratio tWU Wake-uptime 5 10 ms tSTBY Standby time 5 10 ms A-weighting, Pout = 0.9 W, RL = 8 Ω DocID11703 Rev 7 85 dB TS4962M Electrical characteristics Table 5. VCC = 4.2V, GND = 0V, VIC = 2.5V, Tamb = 25°C (unless otherwise specified) (1) Symbol VN Parameter Output voltage noise Conditions Min. Typ. F = 20Hz to 20 kHz, G = 6 dB Unweighted RL = 4 Ω A-weighted RL = 4 Ω 85 60 Unweighted RL = 8 Ω A-weighted RL = 8 Ω 86 62 Unweighted RL = 4 Ω + 15 µH A-weighted RL = 4 Ω + 15 µH 83 60 Unweighted RL = 4 Ω + 30 µH A-weighted RL = 4 Ω + 30 µH 88 64 Unweighted RL = 8 Ω + 30 µH A-weighted RL = 8 Ω + 30 µH 78 57 Unweighted RL = 4 Ω + filter A-weighted RL = 4 Ω + filter 87 65 Unweighted RL = 4 Ω + filter A-weighted RL = 4 Ω + filter 82 59 Max. Unit µVRMS 1. All electrical values are guaranteed with correlation measurements at 2.5 V and 5 V. 2. Standby mode is active when VSTBY is tied to GND. 3. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @ F = 217 Hz. DocID11703 Rev 7 9/41 41 Electrical characteristics TS4962M Table 6. VCC = 3.6 V, GND = 0 V, VIC = 2.5 V, Tamb = 25 °C (unless otherwise specified) (1) Symbol ICC Parameter Supply current (2) Conditions Typ. Max. Unit No input signal, no load 2 2.8 mA No input signal, VSTBY = GND 10 1000 nA 3 25 mV ISTBY Standby current VOO Output offset voltage No input signal, RL = 8 Ω Output power G=6dB THD = 1% max., F = 1 kHz, RL = 4 Ω THD = 10% max., F = 1 kHz, RL = 4 Ω THD = 1% max., F = 1 kHz, RL = 8 Ω THD = 10% max., F = 1 kHz, RL = 8 Ω Total harmonic distortion + noise Pout = 500 mWRMS, G = 6 dB, 20 Hz < F< 20 kHz RL = 8 Ω + 15 µH, BW < 30 kHz Pout = 500 mWRMS, G = 6 dB, F = 1 kHz, RL = 8 Ω + 15 µH, BW < 30 kHz Pout THD + N Efficiency Efficiency Min. 1.15 1.51 0.7 0.9 W 1 % 0.27 Pout = 1 WRMS, RL = 4 Ω + ≥ 15 µH Pout =0.65 WRMS, RL = 8 Ω+ ≥ 15 µH 78 88 % PSRR Power supply rejection ratio with inputs grounded (3) F = 217 Hz, RL = 8 Ω, G=6 dB, Vripple = 200 mVpp 62 dB CMRR Common-mode rejection ratio F = 217 Hz, RL = 8 Ω, G = 6 dB, ∆Vicm = 200 mVpp 56 dB Gain value Rin in kΩ Gain 273k Ω -----------------R in 300k Ω -----------------R in 327k Ω -----------------R in V/V RSTBY Internal resistance from Standby to GND 273 300 327 kΩ FPWM Pulse width modulator base frequency 180 250 320 kHz SNR Signal to noise ratio tWU Wake-uptime 5 10 ms tSTBY Standby time 5 10 ms 10/41 A-weighting, Pout = 0.6 W, RL = 8 Ω DocID11703 Rev 7 83 dB TS4962M Electrical characteristics Table 6. VCC = 3.6 V, GND = 0 V, VIC = 2.5 V, Tamb = 25 °C (unless otherwise specified) (1) Symbol VN Parameter Output voltage noise Conditions Min. Typ. F = 20 Hz to 20 kHz, G = 6 dB Unweighted RL = 4 Ω A-weighted RL = 4 Ω 83 57 Unweighted RL = 8 Ω A-weighted RL = 8 Ω 83 61 Unweighted RL = 4 Ω + 15 µH A-weighted RL = 4 Ω + 15 µH 81 58 Unweighted RL = 4 Ω + 30 µH A-weighted RL = 4 Ω + 30 µH 87 62 Unweighted RL = 8 Ω + 30 µH A-weighted RL = 8 Ω + 30 µH 77 56 Unweighted RL = 4 Ω + filter A-weighted RL = 4 Ω + filter 85 63 Unweighted RL = 4 Ω + filter A-weighted RL = 4 Ω + filter 80 57 Max. Unit µVRMS 1. All electrical values are guaranteed with correlation measurements at 2.5 V and 5 V. 2. Standby mode is active when VSTBY is tied to GND. 3. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @ F = 217 Hz. DocID11703 Rev 7 11/41 41 Electrical characteristics TS4962M Table 7. VCC = 3 V, GND = 0 V, VIC = 2.5 V, Tamb = 25 °C (unless otherwise specified) (1) Symbol ICC Parameter Supply current (2) Conditions Typ. Max. Unit No input signal, no load 1.9 2.7 mA No input signal, VSTBY = GND 10 1000 nA 3 25 mV ISTBY Standby current VOO Output offset voltage No input signal, RL = 8Ω Output power G=6dB THD = 1% max., F = 1 kHz, RL = 4 Ω THD = 10% max., F = 1 kHz, RL = 4 Ω THD = 1% max., F = 1 kHz, RL = 8 Ω THD = 10% max., F = 1 kHz, RL = 8 Ω Total harmonic distortion + noise Pout = 350 mWRMS, G = 6 dB, 20 Hz < F < 20 kHz RL = 8 Ω + 15 µH, BW < 30 kHz Pout = 350 mWRMS, G = 6 dB, F = 1 kHz, RL = 8 Ω + 15 µH, BW < 30 kHz Pout THD + N Efficiency Efficiency Min. 0.75 1 0.5 0.6 W 1 % 0.21 Pout = 0.7 WRMS, RL = 4 Ω + ≥ 15 µH Pout = 0.45 WRMS, RL = 8 Ω+ ≥ 15 µH 78 88 % PSRR Power supply rejection ratio with inputs grounded (3) F = 217 Hz, RL = 8 Ω, G=6 dB, Vripple = 200 mVpp 60 dB CMRR Common-mode rejection ratio F = 217Hz, RL = 8Ω, G = 6 dB, ∆Vicm = 200 mVpp 54 dB Gain value Rin in kΩ Gain 273k Ω -----------------R in 300k Ω -----------------R in 327k Ω -----------------R in V/V RSTBY Internal resistance from Standby to GND 273 300 327 kΩ FPWM Pulse width modulator base frequency 180 250 320 kHz SNR Signal to noise ratio tWU Wake-up time 5 10 ms tSTBY Standby time 5 10 ms 12/41 A-weighting, Pout = 0.4 W, RL = 8 Ω DocID11703 Rev 7 82 dB TS4962M Electrical characteristics Table 7. VCC = 3 V, GND = 0 V, VIC = 2.5 V, Tamb = 25 °C (unless otherwise specified) (1) (continued) Symbol VN Parameter Conditions Min. Typ. f = 20 Hz to 20 kHz, G = 6 dB Unweighted RL = 4 Ω A-weighted RL = 4 Ω 83 57 Unweighted RL = 8 Ω A-weighted RL = 8 Ω 83 61 Unweighted RL = 4 Ω + 15 µH A-weighted RL = 4 Ω + 15 µH 81 58 Output Voltage Noise Unweighted RL = 4 Ω + 30 µH A-weighted RL = 4 Ω + 30 µH 87 62 Unweighted RL = 8 Ω + 30 µH A-weighted RL = 8 Ω + 30 µH 77 56 Unweighted RL = 4 Ω + filter A-weighted RL = 4 Ω + filter 85 63 Unweighted RL = 4 Ω + filter A-weighted RL = 4 Ω + filter 80 57 Max. Unit µVRMS 1. All electrical values are guaranteed with correlation measurements at 2.5 V and 5 V. 2. Standby mode is active when VSTBY is tied to GND. 3. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @ F = 217 Hz. DocID11703 Rev 7 13/41 41 Electrical characteristics TS4962M Table 8. VCC = 2.5 V, GND = 0 V, VIC = 2.5 V, Tamb = 25 °C (unless otherwise specified) Symbol ICC Parameter Supply current (1) Conditions Typ. Max. Unit No input signal, no load 1.7 2.4 mA No input signal, VSTBY = GND 10 1000 nA 3 25 mV ISTBY Standby current VOO Output offset voltage No input signal, RL = 8 Ω Output power G=6dB THD = 1% max., F = 1 kHz, RL = 4 Ω THD = 10% max., F = 1 kHz, RL = 4 Ω THD = 1% max., F = 1 kHz, RL = 8 Ω THD = 10% max., F = 1 kHz, RL = 8 Ω Total harmonic distortion + noise Pout = 200 mWRMS, G = 6 dB, 20 Hz < F< 20 kHz RL = 8 Ω + 15 µH, BW < 30 kHz Pout = 200 WRMS, G = 6 dB, F = 1 kHz, RL = 8 Ω + 15 µH, BW < 30 kHz Pout THD + N Efficiency Efficiency Min. 0.52 0.71 0.33 0.42 W 1 % 0.19 Pout = 0.47 WRMS, RL = 4 Ω + ≥ 15 µH Pout = 0.3 WRMS, RL = 8 Ω+ ≥ 15 µH 78 88 % PSRR Power supply rejection ratio with inputs grounded (2) F = 217 Hz, RL = 8 Ω, G=6 dB, Vripple = 200 mVpp 60 dB CMRR Common-mode rejection ratio F = 217 Hz, RL = 8 Ω, G = 6 dB, ∆Vicm = 200 mVpp 54 dB Gain value Rin in kΩ Gain 273k Ω -----------------R in 300k Ω -----------------R in 327k Ω -----------------R in V/V RSTBY Internal resistance from Standby to GND 273 300 327 kΩ FPWM Pulse width modulator base frequency 180 250 320 kHz SNR Signal to noise ratio tWU Wake-up time 5 10 ms tSTBY Standby time 5 10 ms 14/41 A-weighting, Pout = 1.2 W, RL = 8 Ω DocID11703 Rev 7 80 dB TS4962M Electrical characteristics Table 8. VCC = 2.5 V, GND = 0 V, VIC = 2.5 V, Tamb = 25 °C (unless otherwise specified) (continued) Symbol VN Parameter Output voltage noise Conditions Min. Typ. F = 20Hz to 20kHz, G = 6 dB Unweighted RL = 4 Ω A-weighted RL = 4 Ω 85 60 Unweighted RL = 8 Ω A-weighted RL = 8 Ω 86 62 Unweighted RL = 4 Ω + 15 µH A-weighted RL = 4 Ω + 15 µH 76 56 Unweighted RL = 4 Ω + 30 µH A-weighted RL = 4 Ω + 30 µH 82 60 Unweighted RL = 8 Ω + 30 µH A-weighted RL = 8 Ω + 30 µH 67 53 Unweighted RL = 4 Ω + filter A-weighted RL = 4 Ω + filter 78 57 Unweighted RL = 4 Ω + filter A-weighted RL = 4 Ω + filter 74 54 Max. Unit µVRMS 1. Standby mode is active when VSTBY is tied to GND. 2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @ F = 217 Hz. DocID11703 Rev 7 15/41 41 Electrical characteristics TS4962M Table 9. VCC = 2.4 V, GND = 0 V, VIC = 2.5 V, Tamb = 25 °C (unless otherwise specified) Symbol ICC Parameter Supply current (1) Conditions No input signal, VSTBY = GND 10 nA 3 mV Output offset voltage No input signal, RL = 8 Ω Output power G=6dB THD = 1% max., F = 1 kHz, RL = 4 Ω THD = 10% max., F = 1 kHz, RL = 4 Ω THD = 1% max., F = 1 kHz, RL = 8 Ω THD = 10% max., F = 1 kHz, RL = 8 Ω Total harmonic distortion + noise Pout = 200 mWRMS, G = 6 dB, 20 Hz < F< 20 kHz RL = 8 Ω + 15 µH, BW < 30 kHz 1 % % Common-mode rejection ratio F = 217 Hz, RL = 8 Ω, G = 6 dB, ∆Vicm = 200 mVpp 54 dB Gain value Rin in kΩ Internal resistance from Standby to GND FPWM Pulse width modulator base frequency SNR Signal to noise ratio tWU tSTBY 273k Ω -----------------R in 300k Ω -----------------R in 327k Ω -----------------R in V/V 273 300 327 kΩ 250 kHz 80 dB Wake-up time 5 ms Standby time 5 ms Output voltage noise A Weighting, Pout = 1.2 W, RL = 8 Ω F = 20 Hz to 20 kHz, G = 6 dB Unweighted RL = 4 Ω A-weighted RL = 4 Ω 85 60 Unweighted RL = 8 Ω A-weighted RL = 8 Ω 86 62 Unweighted RL = 4 Ω + 15 µH A-weighted RL = 4 Ω + 15 µH 76 56 Unweighted RL = 4 Ω + 30 µH A-weighted RL = 4 Ω + 30 µH 82 60 Unweighted RL = 8 Ω + 30 µH A-weighted RL = 8 Ω + 30 µH 67 53 Unweighted RL = 4 Ω + Filter A-weighted RL = 4 Ω + Filter 78 57 Unweighted RL = 4 Ω + Filter A-weighted RL = 4 Ω + Filter 74 54 1. Standby mode is active when VSTBY is tied to GND. 16/41 W 77 86 RSTBY VN 0.48 0.65 0.3 0.38 Pout = 0.38 WRMS, RL = 4 Ω + ≥ 15 µH Pout = 0.25 WRMS, RL = 8 Ω+ ≥ 15 µH Efficiency Efficiency Gain Unit mA VOO CMRR Max. 1.7 Standby current THD + N Typ. No input signal, no load ISTBY Pout Min. DocID11703 Rev 7 µVRMS TS4962M 5 Electrical characteristic curves Electrical characteristic curves The graphs included in this section use the following abbreviations: • RL + 15 µH or 30 µH = pure resistor + very low series resistance inductor • Filter = LC output filter (1 µF+30 µH for 4 Ω and 0.5 µF+60 µH for 8 Ω) • All measurements made with Cs1=1 µF and Cs2=100 nF except for PSRR where Cs1 is removed. Figure 4. Test diagram for measurements Vcc 1uF Cs1 Cin 100nF Cs2 + GND GND Rin Out+ In+ 15uH or 30uH 150k TS4962 Cin Rin 4 or 8 Ohms 5th order or RL 50kHz low pass filter LC Filter InOut- 150k GND Audio Measurement Bandwidth < 30kHz Figure 5. Test diagram for PSRR measurements 100nF Cs2 20Hz to 20kHz Vcc GND 4.7uF GND Rin Out+ In+ 15uH or 30uH 150k TS4962 4.7uF Rin 4 or 8 Ohms or 5th order RL LC Filter In- 50kHz low pass filter Out- 150k GND GND 5th order 50kHz low pass Reference RMS Selective Measurement Bandwidth=1% of Fmeas filter DocID11703 Rev 7 17/41 41 Electrical characteristic curves TS4962M Figure 6. Current consumption vs. power supply voltage  1RORDG 7DPE q&  &XUUHQW&RQVXPSWLRQP$                9FF 9 1RORDG 7DPE q&    Figure 8. Current consumption vs. standby voltage at VCC = 3 V           9FF 9 9FF 9   9FF 9 1RORDG 7DPE q&  9FF 9  Figure 10. Efficiency vs. output power at VCC = 5 V and RL = 4 Ω      3RZHU 'LVVLSDWLRQ    9FF 9 5/ :tP+  ) N+] 7+'1d      2XWSXW3RZHU:  (IILFLHQF\ (IILFLHQF\  3RZHU'LVVLSDWLRQP:  18/41         Figure 11. Efficiency vs. output power at VCC = 3 V and RL = 4 Ω     &RPPRQ0RGH,QSXW9ROWDJH9 6WDQGE\9ROWDJH9 (IILFLHQF\  * G% 7DPE q&  9RR P9 &XUUHQW&RQVXPSWLRQP$     Figure 9. Output offset voltage vs. common-mode input voltage     6WDQGE\9ROWDJH9 3RZHU6XSSO\9ROWDJH9  (IILFLHQF\   3RZHU 'LVVLSDWLRQ     DocID11703 Rev 7   9FF 9  5/ :tP+ ) N+] 7+'1d        2XWSXW3RZHU: 3RZHU'LVVLSDWLRQP: &XUUHQW&RQVXPSWLRQP$  Figure 7. Current consumption vs. standby voltage at VCC = 5 V TS4962M Electrical characteristic curves Figure 12. Efficiency vs. output power at VCC = 5 V and RL = 8 Ω      3RZHU 'LVVLSDWLRQ 9FF 9 5/ :tP+ ) N+] 7+'1d        2XWSXW3RZHU:       3RZHU 'LVVLSDWLRQ     (IILFLHQF\    9FF 9 5/ :tP+ ) N+] 7+'1d   2XWSXW3RZHU: 3RZHU'LVVLSDWLRQP:   (IILFLHQF\ (IILFLHQF\ 3RZHU'LVVLSDWLRQP:   (IILFLHQF\ Figure 13. Efficiency vs. output power at VCC = 3 V and RL = 8 Ω     Figure 14. Output power vs. power supply voltage at RL = 4 Ω Figure 15. Output power vs. power supply voltage at RL = 8 Ω  5/ :tP+ ) N+]  %:N+] 7DPE q&  7+'1  2XWSXWSRZHU: 2XWSXWSRZHU:    7+'1   5/ :tP+ ) N+] %:N+]  7DPE q& 7+'1    7+'1        9FF9     Figure 16. PSRR vs. frequency at RL = 4 Ω + 15 µH   9FF9     9ULSSOH P9SS ,QSXWV *URXQGHG * G%&LQ P) 5/ :P+ '55d 7DPE q&     9FF 999         )UHTXHQF\+]  N 9FF 999    9ULSSOH P9SS ,QSXWV *URXQGHG * G%&LQ P) 5/ :P+ '55d 7DPE q&  3655G%  3655G%  Figure 17. PSRR vs. frequency at RL = 4 Ω + 30 µH      DocID11703 Rev 7   )UHTXHQF\+]  N 19/41 41 Electrical characteristic curves TS4962M Figure 18. PSRR vs. frequency at RL = 4 Ω + filter Figure 19. PSR R vs. frequency at RL = 8 Ω + 15 µH   9ULSSOH P9SS ,QSXWV *URXQGHG * G%&LQ P) 5/ :)LOWHU '55d 7DPE q& 3655G%     9FF 999          N  )UHTXHQF\+]  Figure 20. PSRR vs. frequency at RL = 8 Ω + 30 µH   )UHTXHQF\+]  N   9ULSSOH P9SS ,QSXWV *URXQGHG * G%&LQ P) 5/ :P+ '55d 7DPE q&     9FF 999          N  )UHTXHQF\+] 9FF 999    9ULSSOH P9SS ,QSXWV *URXQGHG * G%&LQ P) '55d 5/ :)LOWHU 7DPE q&  3655G%    Figure 21. PSRR vs. frequency at RL = 8 Ω + filter  3655G% 9FF 999    9ULSSOH P9SS ,QSXWV *URXQGHG * G%&LQ P) 5/ :P+ '55d 7DPE q&  3655G%     )UHTXHQF\+]  N  Figure 22. PSRR vs. common-mode input voltage Figure 23. CMRR vs. frequency at RL = 4 Ω + 15 µH      9ULSSOH P9SS ) +]* G% 5/ t:tP+ 7DPE q& 9FF 9  &055G% 3655G%  9FF 9  5/ :P+ * G% '9LFP P9SS '55d &LQ P) 7DPE q&   9FF 999      9FF 9            &RPPRQ0RGH,QSXW9ROWDJH9 20/41 DocID11703 Rev 7   )UHTXHQF\+]  N TS4962M Electrical characteristic curves Figure 24. CMRR vs. frequency at RL = 4 Ω + 30 µH Figure 25. CMRR vs. frequency at RL = 4 Ω + filter   5/ :P+ * G% '9LFP P9SS '55d &LQ P) 7DPE q&   &055G% &055G%   9FF 999    )UHTXHQF\+] 5/ :P+ * G% '9LFP P9SS '55d &LQ P) 7DPE q&  &055G% &055G%  N  5/ :P+ * G% '9LFP P9SS '55d &LQ P) 7DPE q&   )UHTXHQF\+] Figure 27. CMRR vs. frequency at RL = 8 Ω + 30 µH      N Figure 26. CMRR vs. frequency at RL = 8 Ω + 15 µH 9FF 999   9FF 999     )UHTXHQF\+]    N Figure 28. CMRR vs. frequency at RL = 8 Ω + filter  )UHTXHQF\+]  N Figure 29. CMRR vs. common-mode input voltage   5/ :)LOWHU * G% '9LFP P9SS '55d &LQ P) 7DPE q&   &055G% &055G% 9FF 999    5/ :)LOWHU * G% '9LFP P9SS '55d &LQ P) 7DPE q&  '9LFP P9SS ) +] * G% 5/ t:tP+ 7DPE q& 9FF 9  9FF 999 9FF 9   9FF 9    )UHTXHQF\+]  N   DocID11703 Rev 7           &RPPRQ0RGH,QSXW9ROWDJH9 21/41 41 Electrical characteristic curves TS4962M Figure 30. THD+N vs. output power at RL = 4 Ω + 15 µH, F = 100 Hz  5/ :P+ ) +] * G% %:N+] 7DPE q& 9FF 9 9FF 9  (   2XWSXW3RZHU:   (   2XWSXW3RZHU:   Figure 33. THD+N vs. output power at RL = 8 Ω + 30 µH or filter, F = 100 Hz  5/ :P+ ) +] * G% %:N+] 7DPE q& 5/ :P+RU)LOWHU ) +] * G% %:N+] 7DPE q& 9FF 9 9FF 9 9FF 9 7+'1 7+'1 9FF 9   Figure 32. THD+N vs. output power at RL = 8 Ω + 15 µH, F = 100 Hz   9FF 9 9FF 9 9FF 9   (   2XWSXW3RZHU:   Figure 34. THD+N vs. output power at RL = 4 Ω + 15 µH, F = 1 kHz  (   2XWSXW3RZHU:   Figure 35. THD+N vs. output power at RL = 4 Ω + 30 µH or filter, F = 1 kHz  5/ :P+ ) N+] * G% %:N+] 7DPE q& 9FF 9 9FF 9   ( 5/ :P+RU)LOWHU ) N+] * G% %:N+] 7DPE q& 9FF 9 7+'1 7+'1 9FF 9 9FF 9   22/41 5/ :P+RU)LOWHU ) +] * G% %:N+] 7DPE q& 9FF 9 7+'1 7+'1  Figure 31. THD+N vs. output power at RL = 4 Ω + 30 µH or filter, F = 100 Hz   2XWSXW3RZHU:   9FF 9 9FF 9 9FF 9   ( DocID11703 Rev 7   2XWSXW3RZHU:   TS4962M Electrical characteristic curves Figure 36. THD+N vs. output power at RL = 8 Ω + 15 µH, F = 1 kHz Figure 37. THD+N vs. output power at RL = 8 Ω + 30 µH or filter, F = 1 kHz  5/ :P+ ) N+] * G% %:N+] 7DPE q& 9FF 9 9FF 9   ( 5/ :P+RU)LOWHU ) N+] * G% %:N+] 7DPE q& 9FF 9 7+'1 7+'1    2XWSXW3RZHU:  Figure 38. THD+N vs. frequency at RL = 4 Ω + 15 µH, VCC = 5 V    5/ :P+ * G% %ZN+] 9FF 9 7DPE q&  3R :    5/ :P+RU)LOWHU * G% %ZN+] 9FF 9 7DPE q& 3R : 7+'1 7+'1   2XWSXW3RZHU: Figure 39. THD+N vs. frequency at RL = 4 Ω + 30 µH or filter, VCC = 5 V  3R :   )UHTXHQF\+]  N    )UHTXHQF\+]  N Figure 41. THD+N vs. frequency at RL = 4 Ω + 30 H or filter, VCC = 3.6 V   5/ :P+RU)LOWHU * G% %ZN+] 9FF 9 7DPE q& 3R : 7+'1 5/ :P+ * G% %ZN+] 9FF 9 7DPE q& 3R :  Figure 40. THD+N vs. frequency at RL = 4 Ω + 15 µH, VCC = 3.6 V 7+'1 9FF 9 9FF 9   (  9FF 9  3R :  3R : 3R :      )UHTXHQF\+]  N  DocID11703 Rev 7   )UHTXHQF\+]  N 23/41 41 Electrical characteristic curves TS4962M Figure 42. THD+N vs. frequency at RL = 4 Ω + 15 µH, VCC = 2.5 V Figure 43. THD+N vs. frequency at RL = 4 Ω + 30 µH or filter, VCC = 2.5 V   5/ :P+RU)LOWHU * G% %ZN+] 9FF 9 7DPE q& 3R : 7+'1 7+'1 5/ :P+ * G% %ZN+] 9FF 9 7DPE q&  3R :  3R :  3R :    )UHTXHQF\+] N  Figure 44. THD+N vs. frequency at RL = 8 Ω + 15 µH, VCC = 5 V  3R : 7+'1 7+'1  N  5/ :P+ * G% %ZN+] 9FF 9 7DPE q&    )UHTXHQF\+] 7+'1 3R :   )UHTXHQF\+]  N  )UHTXHQF\+] 5/ :P+RU)LOWHU * G% %ZN+] 9FF 9 7DPE q& 3R :   3R :  3R :    3R : Figure 47. THD+N vs. frequency at RL = 8 Ω + 30 µH or filter, VCC = 3.6 V      N Figure 46. THD+N vs. frequency at RL = 8 Ω + 15 µH, VCC = 3.6 V 5/ :P+ * G% %ZN+] 9FF 9 7DPE q& 5/ :P+RU)LOWHU * G% %ZN+] 9FF 9 7DPE q&  3R :  7+'1  )UHTXHQF\+] Figure 45. THD+N vs. frequency at RL = 8 Ω + 30 µH or filter, VCC = 5 V  24/41    N 3R :  DocID11703 Rev 7   )UHTXHQF\+]  N TS4962M Electrical characteristic curves Figure 48. THD+N vs. frequency at RL = 8 Ω + 15 µH, VCC = 2.5 V Figure 49. THD+N vs. frequency at RL = 8 Ω + 30 µH or filter, VCC = 2.5 V   5/ :P+ * G% %ZN+] 9FF 9 7DPE q&  3R : 7+'1 7+'1  5/ :P+RU)LOWHU * G% %ZN+] 9FF 9 7DPE q&   3R :     )UHTXHQF\+] 3R :  N       9FF 999 5/ :P+ * G% 9LQ P9SS &LQ P) 7DPE q&      N     'LIIHUHQWLDO*DLQG% 'LIIHUHQWLDO*DLQG%   9FF 999 5/ :)LOWHU * G% 9LQ P9SS &LQ P) 7DPE q&    )UHTXHQF\+]  N 9FF 999   N 5/ :P+ * G% 9LQ P9SS &LQ P) 7DPE q&    )UHTXHQF\+]  Figure 53. Gain vs. frequency at RL = 8 Ω + 15 µH    N 5/ :P+ * G% 9LQ P9SS &LQ P) 7DPE q&  Figure 52. Gain vs. frequency at RL = 4 Ω + filter   )UHTXHQF\+] 9FF 999    )UHTXHQF\+]  Figure 51. Gain vs. frequency at RL = 4 Ω + 30 µH 'LIIHUHQWLDO*DLQG% 'LIIHUHQWLDO*DLQG% Figure 50. Gain vs. frequency at RL = 4 Ω + 15 µH  3R :  DocID11703 Rev 7   )UHTXHQF\+]  N 25/41 41 Electrical characteristic curves TS4962M Figure 55. Gain vs. frequency at RL = 8 Ω + filter     'LIIHUHQWLDO*DLQG% 'LIIHUHQWLDO*DLQG% Figure 54. Gain vs. frequency at RL = 8 Ω + 30 µH 9FF 999  5/ :P+ * G% 9LQ P9SS &LQ P) 7DPE q&      )UHTXHQF\+]  N Figure 56. Gain vs. frequency at RL = no load 9FF 999  5/ :)LOWHU * G% 9LQ P9SS &LQ P) 7DPE q&      )UHTXHQF\+]  N Figure 57. Startup and shutdown time VCC = 5 V, G = 6 dB, Cin = 1 µF (5 ms/div)  'LIIHUHQWLDO*DLQG% Vo1  Vo2 9FF 999  Standby 5/ 1R/RDG * G% 9LQ P9SS &LQ P) 7DPE q&     Vo1-Vo2  )UHTXHQF\+]  N Figure 58. Startup and shutdown time VCC = 3 V, Figure 59. Startup and shutdown time VCC = 5 V, G = 6 dB, Cin = 1 µF (5 ms/div) G = 6 dB, Cin = 100 nF (5 ms/div) Vo1 Vo1 Vo2 Vo2 Standby Standby Vo1-Vo2 26/41 Vo1-Vo2 DocID11703 Rev 7 TS4962M Electrical characteristic curves Figure 60. Startup and shutdown time VCC = 3 V, Figure 61. Startup and shutdown time VCC = 5 V, G = 6 dB, Cin = 100 nF (5 ms/div) G = 6 dB, No Cin (5 ms/div) Vo1 Vo1 Vo2 Vo2 Standby Standby Vo1-Vo2 Vo1-Vo2 Figure 62. Startup and shutdown time VCC = 3 V, G = 6 dB, no Cin (5 ms/div) Vo1 Vo2 Standby Vo1-Vo2 DocID11703 Rev 7 27/41 41 Application information TS4962M 6 Application information 6.1 Differential configuration principle The TS4962M is a monolithic fully-differential input/output class D power amplifier. The TS4962M also includes a common-mode feedback loop that controls the output bias value to average it at VCC/2 for any DC common-mode input voltage. This allows the device to always have a maximum output voltage swing, and by consequence, maximizes the output power. Moreover, as the load is connected differentially compared to a single-ended topology, the output is four times higher for the same power supply voltage. The advantages of a full-differential amplifier are: • High PSRR (power supply rejection ratio) • High common-mode noise rejection • Virtually zero pop without additional circuitry, giving a faster start-up time compared to conventional single-ended input amplifiers. • Easier interfacing with differential output audio DAC • No input coupling capacitors required due to common-mode feedback loop The main disadvantage is: • 6.2 As the differential function is directly linked to external resistor mismatching, particular attention to this mismatching is mandatory to obtain the best performance from the amplifier. Gain in typical application schematic Typical differential applications are shown in Figure 3 on page 4. In the flat region of the frequency-response curve (no input coupling capacitor effect), the differential gain is expressed by the relation: + AV diff - Out – Out 300 = ------------------------------ = ---------+ R in In – In with Rin expressed in kΩ. Due to the tolerance of the internal 150 kΩ feedback resistor, the differential gain will be in the range (no tolerance on Rin): 273 327 ---------- ≤ A V ≤ ---------d iff R in R in 28/41 DocID11703 Rev 7 TS4962M 6.3 Application information Common-mode feedback loop limitations The common-mode feedback loop allows the output DC bias voltage to be averaged at VCC/2 for any DC common-mode bias input voltage. However, due to Vicm limitation in the input stage (see Table 3: Operating conditions on page 5), the common-mode feedback loop can ensure its role only within a defined range. This range depends upon the values of VCC and Rin (AVdiff). To have a good estimation of the Vicm value, we can apply this formula (no tolerance on Rin): VCC × R in + 2 × V IC × 150kΩ V icm = ---------------------------------------------------------------------------2 × ( R in + 150kΩ ) (V) with + - In + In V IC = --------------------2 (V) and the result of the calculation must be in the range: 0.5V ≤ V icm ≤ V CC – 0.8V Due to the ±9% tolerance on the 150kΩ resistor, it is also important to check Vicm in these conditions: VCC × R in + 2 × V IC × 163.5kΩ V CC × R in + 2 × V IC × 136.5kΩ --------------------------------------------------------------------------------- ≤ V icm ≤ --------------------------------------------------------------------------------2 × ( R in + 136.5kΩ ) 2 × ( R in + 163.5kΩ ) If the result of the Vicm calculation is not in the previous range, input coupling capacitors must be used (with VCC from 2.4V to 2.5V, input coupling capacitors are mandatory). Example With VCC = 3 V, Rin = 150 k and VIC = 2.5 V, we typically find Vicm = 2 V and this is lower than 3V - 0.8 V = 2.2 V. With 136.5 kΩ we find 1.97 V, and with 163.5 kΩ we have 2.02 V. So, no input coupling capacitors are required. 6.4 Low frequency response If a low frequency bandwidth limitation is requested, it is possible to use input coupling capacitors. In the low frequency region, Cin (input coupling capacitor) starts to have an effect. Cin forms, with Rin, a first order high-pass filter with a -3dB cut-off frequency: 1 F CL = -----------------------------------2π × R in × C in (Hz) So, for a desired cut-off frequency we can calculate Cin, 1 C in = -------------------------------------2π × Rin × F CL (F) with Rin in Ω and FCL in Hz. DocID11703 Rev 7 29/41 41 Application information 6.5 TS4962M Decoupling of the circuit A power supply capacitor, referred to as CS, is needed to correctly bypass the TS4962M. The TS4962M has a typical switching frequency at 250 kHz and an output fall and rise time about 5ns. Due to these very fast transients, careful decoupling is mandatory. A 1 µF ceramic capacitor is enough, but it must be located very close to the TS4962M in order to avoid any extra parasitic inductance created by an overly long track wire. In relation with dI/dt, this parasitic inductance introduces an overvoltage that decreases the global efficiency and, if it is too high, may cause a breakdown of the device. In addition, even if a ceramic capacitor has an adequate high-frequency ESR value, its current capability is also important. A 0603 size is a good compromise, particularly when a 4 Ω load is used. Another important parameter is the rated voltage of the capacitor. A 1 µF/6.3 V capacitor used at 5 V, loses about 50% of its value. In fact, with a 5V power supply voltage, the decoupling value is about 0.5 µF instead of 1µF. As CS has particular influence on the THD+N in the medium-high frequency region, this capacitor variation becomes decisive. In addition, less decoupling means higher overshoots, which can be problematic if they reach the power supply AMR value (6 V). 6.6 Wake-up time (tWU) When the standby is released to set the device ON, there is a wait of about 5ms. The TS4962M has an internal digital delay that mutes the outputs and releases them after this time in order to avoid any pop noise. 6.7 Shutdown time (tSTBY) When the standby command is set, the time required to put the two output stages into high impedance and to put the internal circuitry in shutdown mode, is about 5 ms. This time is used to decrease the gain and avoid any pop noise during shutdown. 6.8 Consumption in shutdown mode Between the shutdown pin and GND there is an internal 300 kΩ resistor. This resistor forces the TS4962M to be in standby mode when the standby input pin is left floating. However, this resistor also introduces additional power consumption if the shutdown pin voltage is not 0 V. For example, with a 0.4 V standby voltage pin, Table 3: Operating conditions on page 5, shows that you must add 0.4 V/300 kΩ = 1.3 µA in typical (0.4 V/273 kΩ = 1.46 µA in maximum) to the shutdown current specified in Table 4 on page 6. 30/41 DocID11703 Rev 7 TS4962M Single-ended input configuration It is possible to use the TS4962M in a single-ended input configuration. However, input coupling capacitors are needed in this configuration. The schematic in Figure 63 shows a single-ended input typical application. Figure 63. Single-ended input typical application Vcc B1 Cs 1u B2 Vcc Standby Cin GND Rin C2 Stdby 300k Ve C1 Internal Bias C3 Output - A1 GND Out+ 150k InIn+ + H Bridge PWM SPEAKER Rin Cin A3 150k Out- Oscillator GND GND TS4962 A2 B3 GND All formulas are identical except for the gain (with Rin in kΩ): AV sin gle Ve 300 = ------------------------------- = ---------+ R in Out – Out And, due to the internal resistor tolerance we have: 327 273 ---------- ≤ A V ≤ ---------sin g le R in R in In the event that multiple single-ended inputs are summed, it is important that the impedance on both TS4962M inputs (In- and In+) are equal. Figure 64. Typical application schematic with multiple single-ended inputs Vcc Vek Standby Cink B1 Rink C2 Stdby GND Ve1 Cin1 Rin1 C1 A1 GND Ceq GND Cs 1u B2 Vcc 300k 6.9 Application information Internal Bias GND Out+ 150k C3 Output - InIn+ + PWM H Bridge SPEAKER Req A3 150k Out- Oscillator GND TS4962 A2 B3 GND DocID11703 Rev 7 31/41 41 Application information TS4962M We have the following equations: + 300 300 Out – Out = V e1 × ------------- + … + V ek × ------------R R in1 ink (V) k C eq = C inj Σ Cinj j=1 1 = ---------------------------------------------------2×π×R ×F inj CLj (F) 1 R eq = ------------------k 1  --------Rinj j =1 In general, for mixed situations (single-ended and differential inputs), it is best to use the same rule, that is, to equalize impedance on both TS4962M inputs. 6.10 Output filter considerations The TS4962M is designed to operate without an output filter. However, due to very sharp transients on the TS4962M output, EMI radiated emissions may cause some standard compliance issues. These EMI standard compliance issues can appear if the distance between the TS4962M outputs and loudspeaker terminal is long (typically more than 50mm, or 100mm in both directions, to the speaker terminals). As the PCB layout and internal equipment device are different for each configuration, it is difficult to provide a one-size-fits-all solution. However, to decrease the probability of EMI issues, there are several simple rules to follow: • Reduce, as much as possible, the distance between the TS4962M output pins and the speaker terminals. • Use ground planes for “shielding” sensitive wires • Place, as close as possible to the TS4962M and in series with each output, a ferrite bead with a rated current at minimum 2A and impedance greater than 50Ω at frequencies above 30MHz. If, after testing, these ferrite beads are not necessary, replace them by a short-circuit. Murata BLM18EG221SN1 or BLM18EG121SN1 are possible examples of devices you can use. • Allow enough of a footprint to place, if necessary, a capacitor to short perturbations to ground (see the schematics in Figure 65). Figure 65. Method for shorting pertubations to ground Ferrite chip bead To speaker From TS4962 output about 100pF Gnd 32/41 DocID11703 Rev 7 TS4962M Application information In the case where the distance between the TS4962M outputs and speaker terminals is high, it is possible to have low frequency EMI issues due to the fact that the typical operating frequency is 250kHz. In this configuration, we recommend using an output filter (as shown in Figure 3: Typical application schematics on page 4). It should be placed as close as possible to the device. Different examples with summed inputs Example 1: Dual differential inputs Figure 66. Typical application schematic with dual differential inputs Vcc Standby B1 Cs 1u B2 Vcc C2 Stdby R2 300k 6.11 E2+ R1 C1 E1+ E1- A1 Internal Bias Out+ 150k GND C3 Output - InIn+ + PWM H Bridge SPEAKER R1 A3 150k E2R2 Out- Oscillator GND A2 B3 TS4962 GND With (Ri in kΩ): + - + - 300 Out – Out - = ---------A V = -----------------------------+ 1 R1 E1 – E1 Out – Out 300 A V = ------------------------------ = ---------+ 2 R2 E2 – E2 V CC × R 1 × R 2 + 300 × ( V IC1 × R 2 + V IC2 × R 1 ) 0.5V ≤ --------------------------------------------------------------------------------------------------------------------------- ≤ VCC – 0.8V 300 × ( R 1 + R 2 ) + 2 × R 1 × R 2 + - + - E1 + E1 E2 + E2 V IC = ------------------------ and V IC = -----------------------1 2 2 2 DocID11703 Rev 7 33/41 41 Application information TS4962M Example 2: One differential input plus one single-ended input Figure 67. Typical application schematic with one differential input plus one single-ended input Vcc Standby B1 Cs 1u B2 Vcc C2 Stdby 300k R2 E2+ C1 R1 E1+ E2- C1 A1 Internal Bias Out+ 150k Output - InIn+ + PWM H Bridge SPEAKER R2 A3 150k GND C1 R1 Out- Oscillator GND A2 B3 GND With (Ri in kΩ): + - + - Out – Out 300 A V = ------------------------------ = ---------+ 1 R1 E1 Out – Out 300 - = ---------A V = -----------------------------+ 2 R2 E2 – E2 1 C 1 = -----------------------------------2π × R1 × F CL 34/41 GND C3 DocID11703 Rev 7 (F) TS4962 TS4962M Evaluation board An evaluation board for the TS4962M is available with a Flip Chip to DIP adapter. For more information about this board, refer to AN2134. Figure 68. Schematic diagram of mono class D evaluation board for TS4962M Vcc Vcc Cn1 + J1 1 2 3 + Cn2 GND GND C1 2.2uF/10V GND Vcc Cn4 + J2 3 8 U1 Vcc C2 300k 4 Stdby R1 Internal Bias Out+ 150k 6 Cn3 100nF 150k Positive Input Negative input 100nF R2 C3 5 1 - InIn+ + Positive Output H Bridge PWM Negative Output 10 150k 150k Cn6 Output Out- Oscillator GND TS4962 Flip-Chip to DIP Adapter 3 2 Cn5 + J3 GND pin8 Pin3 Figure 69. Diagram for Flip Chip to DIP adapter R1 OR + C1 C2 1uF 100nF B1 B2 Vcc Pin1 C1 A1 Internal Bias Out+ 150k C3 Pin6 Output - InIn+ + PWM H Bridge A3 150k Pin10 Out- Oscillator GND A2 B3 TS4962 R2 OR DocID11703 Rev 7 Pin9 Pin5 C2 Stdby Pin2 Pin4 300k 7 Evaluation board 35/41 41 Evaluation board TS4962M Figure 70. Top view Figure 71. Bottom layer Figure 72. Top layer 36/41 DocID11703 Rev 7 TS4962M 8 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 8.1 9-bump Flip Chip package information Figure 73. 9-bump Flip Chip package outline PP PP PP PP %DFNVLGH FRDWLQJ RSWLRQDO ‡ PP —P Table 10. 9-bump Flip Chip mechanical data Parameter Dimensions Die size 1.6 mm x 1.6 mm ±30 µm Die height (including bumps) 600 µm Bump diameter 315 µm ±50 µm Bump diameter before re-flow 300 µm ±10 µm Bump height 250 µm ±40 µm Die height 350 µm ±20 µm Pitch 500 µm ±50 µm Coplanarity 50 µm max. Backside coating (optional, only for the TS4962MEIKJT) 25 µm ±3 µm DocID11703 Rev 7 37/41 41 Package information TS4962M Figure 74. 9-bump Flip Chip marking (top view) E XXX YWW 1. Legend: ST logo E = symbol for lead-free First two “XX” = product code = 62 Third X = assembly code Three-digit date code, Y = year, WW = week Black dot is for marking pin A1 Figure 75. 9-bump Flip Chip recommended footprint 500µm 75µm min. 100µm max. 500µm Track Φ=400µm typ. 150µm min. Φ=340µm min. 500µm 500µm Φ=250µm Non Solder mask opening Pad in Cu 18µm with Flash NiAu (2-6µm, 0.2µm max.) 38/41 DocID11703 Rev 7 TS4962M 9 Ordering information Ordering information Table 11. Order code table Part number Temperature range TS4962MEIJT TS4962MEIKJT Package Packing Marking Tape and reel 62L Lead-free Flip Chip -40 °C to 85 °C Lead-free Flip Chip with backside coating DocID11703 Rev 7 39/41 41 Revision history 10 TS4962M Revision history Table 12. Document revision history 40/41 Date Revision Changes Oct. 2005 1 First release corresponding to the product preview version. Nov. 2005 2 Electrical data updated for output voltage noise, see Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9 Formatting changes throughout. Dec. 2005 3 Product in full production. 10-Jan-2007 4 Template update, no technical changes. 10-Oct-2016 5 Updated datasheet layout Added package silhouettes Added Related products Updated Applications Section 5: Electrical characteristic curves: updated titles of graphs which had same titles. Figure 73: 9-bump Flip Chip package outline: updated diagram to display the optional backside coating for order code TS4962MEIKJT. Added Table 10 to display package mechanical data as a separate table (with information concerning the optional backside coating for order code TS4962MEIKJT). Table 11: Order code table: updated marking of order code TS4962MEIJT, added order code TS4962MEIKJT. 15-Jan-2018 6 Updated Table 10: 9-bump Flip Chip mechanical data. 17-Mar-2020 7 Removed feature on the cover page and footnote Rthja parameter in Table 2. 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For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DocID11703 Rev 7 41/41 41