TS4972EIJT

TS4972 1.2W Audio Power Amplifier with Standby Mode Active High ■ ■ ■ ■ ■ ■ ■ ■ ■ Operating from VCC = 2.5V to 5.5V Rail-to-rail output 1.2W output power @ Vcc=5V, THD=1%, F=1kHz, with 8Ω load Ultra low consumption in standby mode (10nA) 75dB PSRR @ 217Hz from 2.5 to 5V Low pop & click Ultra low distortion (0.05%) Unity gain stable Flip-chip package 8 x 300µm bumps Pin Connections (top view) 7 + Vin 8 The TS4972 is an Audio Power Amplifier capable of delivering 1.6W of continuous RMS ouput power into a 4Ω load @ 5V. This Audio Amplifier is exhibiting 0.1% distortion level (THD) from a 5V supply for a Pout = 250mW RMS. An external standby mode control reduces the supply current to less than 10nA. An internal shutdown protection is provided. o r P 5 Vcc Stdby ■ ■ ■ ■ t e l o Gnd Bypass 1 2 3 s b O Cfeed Rfeed VCC Cs 6 VCC Audio Input Rin 1 Vin- - 7 Vin+ + Vout 1 Cin The unity-gain stable amplifier can be configured by external gain setting resistors. Applications r P e 4 Vout2 Vin ) (s u d o TYPICAL APPLICATION SCHEMATIC t c u d The TS4972 has been designed for high quality audio applications such as mobile phones and to minimize the number of external components. 6 Vout1 Description e t e ol ) s ( ct TS4972JT - FLIP CHIP 8 RL 8 Ohms VCC AV = -1 3 Bypass 5 Standby Vout 2 4 + Rstb s b O Mobile phones (cellular / cordless) PDAs Laptop/notebook computers Portable audio devices Bias GND Cb TS4972 2 Order Codes Part Number Temperature Range Package Packing Marking TS4972IJT TS4972EIJT1 -40, +85°C Flip-Chip Tape & Reel 4972 1) Lead free Flip-Chip part number October 2004 Revision 2 1/30 TS4972 1 Absolute Maximum Ratings Absolute Maximum Ratings Table 1: Key parameters and their absolute maximum ratings Symbol VCC Parameter Supply voltage Value 1 2 Vi Unit 6 V V -40 to + 85 °C Toper Input Voltage Operating Free Air Temperature Range GND to VCC Tstg Storage Temperature -65 to +150 °C Maximum Junction Temperature 150 °C Thermal Resistance Junction to Ambient 3 Power Dissipation 200 °C/W Tj Rthja Pd Internally Limited4 2 200 Class A 250 ESD Human Body Model ESD Machine Model Latch-up Latch-up Immunity Lead Temperature (soldering, 10sec) 2) The magnitude of input signal must never exceed VCC + 0.3V / GND - 0.3V 3) Device is protected in case of over temperature by a thermal shutdown active @ 150°C. s b O 4) Exceeding the power derating curves during a long period, involves abnormal operating condition. Symbol Supply Voltage Common Mode Input Voltage Range VSTB Standby Voltage Input : Device ON Device OFF RL Rthja r P e t e l o s b O t(s uc od Load Resistor Thermal Resistance Junction to Ambient 1 1) With Heat Sink Surface = 125mm2 2/30 )- Parameter VCC VICM u d o r P e °C t e l o 1) All voltages values are measured with respect to the ground pin. Table 2: Operating Conditions kV V Value Unit 2.5 to 5.5 GND to VCC - 1.2V V GND ≤ VSTB ≤ 0.5V VCC - 0.5V ≤ VSTB ≤ VCC V V 4 - 32 Ω 90 °C/W ) s ( ct Electrical Characteristics 2 TS4972 Electrical Characteristics Table 3: VCC = +5V, GND = 0V, Tamb = 25°C (unless otherwise specified) Symbol Typ. Max. Unit Supply Current No input signal, no load 6 8 mA Standby Current 1 No input signal, Vstdby = Vcc, RL = 8Ω 10 1000 nA Voo Output Offset Voltage No input signal, RL = 8Ω 5 20 mV Po Output Power THD = 1% Max, f = 1kHz, RL = 8Ω 1.2 W Total Harmonic Distortion + Noise Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8Ω 0.1 % Power Supply Rejection Ratio2 f = 217Hz, RL = 8Ω, RFeed = 22KΩ, Vripple = 200mV rms 75 dB ΦM Phase Margin at Unity Gain RL = 8Ω, CL = 500pF 70 GM Gain Margin RL = 8Ω, CL = 500pF GBP Gain Bandwidth Product RL = 8Ω ICC ISTANDBY THD + N PSRR Parameter Min. t e l o bs 20 ) s ( ct 1) Standby mode is actived when Vstdby is tied to Vcc -O 2 r P e u d o Degrees dB MHz 2) Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ f = 217Hz u d o r P e t e l o s b O 3/30 ) s ( ct TS4972 Electrical Characteristics Table 4: VCC = +3.3V, GND = 0V, Tamb = 25°C (unless otherwise specified)3) Symbol Typ. Max. Unit Supply Current No input signal, no load 5.5 8 mA Standby Current 1 No input signal, Vstdby = Vcc, RL = 8Ω 10 1000 nA Voo Output Offset Voltage No input signal, RL = 8Ω 5 20 mV Po Output Power THD = 1% Max, f = 1kHz, RL = 8Ω 500 mW Total Harmonic Distortion + Noise Po = 250mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8Ω 0.1 % Power Supply Rejection Ratio2 f = 217Hz, RL = 8Ω, RFeed = 22KΩ, Vripple = 200mV rms 75 dB ΦM Phase Margin at Unity Gain RL = 8Ω, CL = 500pF 70 GM Gain Margin RL = 8Ω, CL = 500pF 20 GBP Gain Bandwidth Product RL = 8Ω ICC ISTANDBY THD + N PSRR Parameter Min. ) (s 1) Standby mode is actived when Vstdby is tied to Vcc 2) Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ f = 217Hz 3. All electrical values are made by correlation between 2.6V and 5V measurements d t c u e t e ol s b O 4/30 o r P t e l o s b O 2 r P e u d o Degrees dB MHz ) s ( ct Electrical Characteristics TS4972 Table 5: VCC = 2.6V, GND = 0V, Tamb = 25°C (unless otherwise specified) Symbol Typ. Max. Unit Supply Current No input signal, no load 5.5 8 mA Standby Current 1 No input signal, Vstdby = Vcc, RL = 8Ω 10 1000 nA Voo Output Offset Voltage No input signal, RL = 8Ω 5 20 mV Po Output Power THD = 1% Max, f = 1kHz, RL = 8Ω 300 mW Total Harmonic Distortion + Noise Po = 200mW rms, Gv = 2, 20Hz < f < 20kHz, RL = 8Ω 0.1 % Power Supply Rejection f = 217Hz, RL = 8Ω, RFeed = 22KΩ, Vripple = 200mV rms 75 dB ΦM Phase Margin at Unity Gain RL = 8Ω, CL = 500pF 70 GM Gain Margin RL = 8Ω, CL = 500pF 20 GBP Gain Bandwidth Product RL = 8Ω ICC ISTANDBY THD + N PSRR Parameter Min. Ratio2 ) (s 1) Standby mode is actived when Vstdby is tied to Vcc t e l o s b O 2 r P e Degrees dB MHz 2) Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ f = 217Hz Table 6: Components description Components t c u Functional Description d Rin Inverting input resistor which sets the closed loop gain in conjunction with Rfeed. This resistor also forms a high pass filter with Cin (fc = 1 / (2 x Pi x Rin x Cin)) Cin Input coupling capacitor which blocks the DC voltage at the amplifier input terminal o r P Rfeed Feed back resistor which sets the closed loop gain in conjunction with Rin Cs Supply Bypass capacitor which provides power supply filtering Cb Bypass pin capacitor which provides half supply filtering Cfeed Low pass filter capacitor allowing to cut the high frequency (low pass filter cut-off frequency 1 / (2 x Pi x Rfeed x Cfeed)) Rstb Gv e t e ol u d o s b O Pull-up resistor which fixes the right supply level on the standby pin Closed loop gain in BTL configuration = 2 x (Rfeed / Rin) Remarks: 1. All measurements, except PSRR measurements, are made with a supply bypass capacitor Cs = 100µF. 2. External resistors are not needed for having better stability when supply @ Vcc down to 3V. By the way, the quiescent current remains the same. 3. The standby response time is about 1µs. 5/30 ) s ( ct TS4972 Electrical Characteristics Figure 1: Open Loop Frequency Response Figure 4: Open Loop Frequency Response 0 -40 -60 40 -80 -100 20 -120 -140 0 Vcc = 5V ZL = 8Ω + 560pF Tamb = 25°C -120 -140 0 10 100 1000 10000 -180 -40 0.3 Figure 2: Open Loop Frequency Response 1 10 60 Vcc = 33V RL = 8Ω Tamb = 25°C -60 20 -120 -140 0 -160 Gain (dB) -100 40 Phase 20 t(s -20 -200 -220 1 10 100 1000 Frequency (kHz) 10000 c u d -40 0.3 -240 o r P Figure 3: Open Loop Frequency Response Gain 60 ol Gain (dB) 40 20 0 -20 1 1 10 Gain 60 -40 -60 -100 -120 -140 -160 so b O 100 1000 Frequency (kHz) 10000 -240 -60 -80 -100 -120 -160 -180 -200 -220 100 1000 Frequency (kHz) 10000 Vcc = 2.6V ZL = 8Ω + 560pF Tamb = 25°C -240 -20 -40 -60 -80 40 Phase -100 -120 20 -140 -160 0 -180 -200 -20 -220 -220 10 -40 -140 -180 -200 -20 0 -20 -80 O -40 0.3 6/30 bs Phase let Vcc = 3.3V ZL = 8Ω + 560pF Tamb = 25°C 80 0 Vcc = 2.6V RL = 8Ω Tamb = 25°C Phase (Deg) ete 80 r P e Figure 6: Open Loop Frequency Response Gain (dB) -40 0.3 )- 0 -180 -20 -220 0 Gain 60 -40 -80 Phase 10000 80 -20 Phase (Deg) Gain (dB) 40 100 1000 Frequency (kHz) Figure 5: Open Loop Frequency Response 0 Gain u d o -200 -220 Frequency (kHz) 80 ) s ( ct -160 -20 -200 1 -60 -100 20 -180 -40 0.3 -40 -80 Phase -160 -20 -20 Phase (Deg) Phase Gain Phase (Deg) 60 -40 0.3 1 10 100 1000 Frequency (kHz) 10000 -240 Phase (Deg) Gain (dB) 40 0 -20 Gain (dB) Vcc = 5V RL = 8Ω Tamb = 25°C Gain Phase (Deg) 60 Electrical Characteristics TS4972 Figure 7: Open Loop Frequency Response 100 -80 80 -100 Phase -30 -160 20 -180 0 Vcc = 5V CL = 560pF Tamb = 25°C -20 -40 0.3 1 10 Phase (Deg) -140 40 PSRR (dB) -120 Gain 80 -80 10 10000 Phase -80 -10 -100 -20 -160 20 -180 0 10 -220 100 1000 Frequency (kHz) 10000 o r P bs 80 Phase Gain (dB) 20 O -20 -160 0 -40 0.3 -200 Vcc = 3.3V CL = 560pF Tamb = 25°C 1 10 100 1000 Frequency (kHz) 10000 Vcc = 5, 3.3 & 2.6V Rfeed = 22k Rin = 22k, Cin = 1µF Rg = 100Ω, RL = 8Ω Tamb = 25°C Cb=47µF 100 1000 10000 100000 Figure 12: Power Supply Rejection Ratio (PSRR) vs Feedback Resistor -10 -140 t e l o Frequency (Hz) -100 -180 -20 u d o r P e Cb=100µF -80 10 -120 Gain 40 -70 -80 -30 Phase (Deg) e t e ol -50 s ( t c du -240 Figure 9: Open Loop Frequency Response 100 )- -40 -60 PSRR (dB) 1 -30 -200 Vcc = 2.6V CL = 560pF Tamb = 25°C 100000 s b O Cb=10µF PSRR (dB) -140 40 1000 10000 Frequency (Hz) Cb=1µF Phase (Deg) Gain (dB) Gain 100 Figure 11: Power Supply Rejection Ratio (PSRR) vs Bypass Capacitor -120 60 -40 0.3 ) s ( ct Vcc = 5V, 3.3V & 2.6V Cb = 1µF & 0.1µF -60 -220 100 1000 Frequency (kHz) 100 -20 -50 -70 -200 Figure 8: Open Loop Frequency Response 60 Vripple = 200mVrms Rfeed = 22Ω Input = floating RL = 8Ω Tamb = 25°C -40 60 Gain (dB) Figure 10: Power Supply Rejection Ratio (PSRR) vs Power supply -40 Vcc = 5, 3.3 & 2.6V Cb = 1µF & 0.1µF Vripple = 200mVrms Input = floating RL = 8Ω Tamb = 25°C Rfeed=110kΩ Rfeed=47kΩ -50 -60 Rfeed=22kΩ -220 -70 -240 -80 10 Rfeed=10kΩ 100 1000 10000 Frequency (Hz) 100000 7/30 TS4972 Electrical Characteristics Figure 13: Power Supply Rejection Ratio (PSRR) vs Feedback Capacitor Figure 16: Power Dissipation vs Pout 1.4 -10 PSRR (dB) -30 -40 Vcc = 5, 3.3 & 2.6V Cb = 1µF & 0.1µF Rfeed = 22kΩ Vripple = 200mVrms Input = floating RL = 8Ω Tamb = 25°C Vcc=5V 1.2 F=1kHz THD+N 4.4ms). Increasing Cin value increases the pop and click phenomena to an unpleasant sound at power supply ON and standby function ON/OFF. First of all, we must calculate the minimum power supply voltage to obtain 0.5W into 8Ω. With curves in fig. 15, we can read 3.5V. Thus, the power supply voltage value min. will be 3.5V. Following equation power 2 Vcc r P e dissipation 2 t e l o π2RL (W) with 3.5V we have Pdissmax=0.31W. s b O Refer to power derating curves (fig. 20), with 0.31W the maximum ambient temperature will be 100°C. This last value could be higher if you follow the example layout shown on the demoboard (better dissipation). Hypothesis : • Cs = 100µF • Supply voltage = 5V • Supply voltage internal resistor = 0.1Ω • Supply current of the amplifier Icc = 6mA ) (s t c u The gain of the amplifier in flat region will be: At power ON of the supply, the supply capacitor is charged through the internal power supply resistor. So, to reach 5V you need about five to ten times the charging time constant of Cs (τs = 0.1xCs (s)). Then, this time equal 50µs to 100µs > tdischCs. Power amplifier design examples u d o V OUT PP 2 2R L P OUT G V = --------------------- = ------------------------------------ = 5.65 V IN PP V IN PP We have Rin > 10kΩ. Let's take Rin = 10kΩ, then Rfeed = 28.25kΩ. We could use for Rfeed = 30kΩ in normalized value and the gain will be Gv = 6. In lower frequency we want 20 Hz (-3dB cut off frequency). Then: 1 C IN = ------------------------------ = 795nF 2π RinF CL So, we could use for Cin a 1µF capacitor value which gives 16Hz. In Higher frequency we want 20kHz (-3dB cut off frequency). The Gain Bandwidth Product of the TS4972 is 2MHz typical and doesn't change when the amplifier delivers power into the load. The first amplifier has a gain of: Rfeed ----------------- = 3 Rin 23/30 ) s ( ct TS4972 Application Information and the theoretical value of the -3dB cut-off higher frequency is 2MHz/3 = 660kHz. We can keep this value or limit the bandwidth by adding a capacitor Cfeed, in parallel on Rfeed. Then: 1 C F EED = --------------------------------------- = 265pF 2π R F EE D F C H So, we could use for Cfeed a 220pF capacitor value that gives 24kHz. Now, we can calculate the value of Cb with the formula τb = 50kΩxCb >> τin = (Rin+Rfeed)xCin which permits to reduce the pop and click effects. Then Cb >> 0.8µF. We can choose for Cb a normalized value of 2.2µF that gives good results in THD+N and PSRR. In the following tables, you could find three another examples with values required for the demoboard. Application n°1 : 20Hz to 20kHz bandwidth and 6dB gain BTL power amplifier 22k / 0.125W R4 22k / 0.125W R6 Short Cicuit R7 100k / 0.125W R8 Short Circuit 22k / 0.125W R6 Short Cicuit R7 100k / 0.125W R8 Short Cicuit C5 470nF C6 100µF C7 100nF Short Circuit C10 Short Circuit C12 s ( t c 2mm insulated Plug 10.16mm pitch 3 pts connector 2.54mm pitch SMB Plug du Application n°3 : 50Hz to 10kHz bandwidth and 10dB gain BTL power amplifier ro t e l o Components: Designator Part Type R1 33k / 0.125W R2 Short Circuit R4 22k / 0.125W R6 Short Cicuit R7 100k / 0.125W R8 Short Cicuit C2 470pF C5 150nF C6 100µF C7 100nF C9 Short Circuit 100µF s b O 100nF Short Circuit Short Circuit C12 1µF S1, S2, S6, S7 2mm insulated Plug 10.16mm pitch S8 3 pts connector 2.54mm pitch P1 SMB Plug u d o r P e s b O 1µF )- ) s ( ct t e l o C9 470nF C6 24/30 110k / 0.125W R4 P1 P e C5 Part Type R1 Part Type R1 C10 Designator S8 Designator C9 Components: S1, S2, S6, S7 Components: C7 Application n°2 : 20Hz to 20kHz bandwidth and 20dB gain BTL power amplifier Application Information TS4972 C10 Short Circuit For Vcc=5V, a 20Hz to 20kHz bandwidth and 20dB gain BTL power amplifier you could follow the bill of material below. C12 1µF Components: S1, S2, S6, S7 2mm insulated Plug 10.16mm pitch R1 110k / 0.125W S8 3 pts connector 2.54mm pitch R4 22k / 0.125W SMB Plug R5 22k / 0.125W R6 110k / 0.125W Designator Part Type P1 Designator Application n°4 : Differential inputs BTL power amplifier Part Type R7 100k / 0.125W In this configuration, we need to place these components : R1, R4, R5, R6, R7, C4, C5, C12. R8 Short circuit We have also : R4 = R5, R1 = R6, C4 = C5. C4 470nF The differential gain of the amplifier is: C5 470nF C6 100µF R1 G VDI F F = 2 -------R4 C7 Note : Due to the VICM range (see Operating Condition), GVDIFF must have a minimum value shown in figure 84. C9 Figure 84: Minimum Differential Gain vs Power Supply Voltage C12 40 Differential Gain min. (dB) 30 e t e ol 25 20 15 s b O 10 2.5 3.0 3.5 4.0 4.5 Power Supply Voltage (V) o r P 5.0 u d o r P e t e l o s b O 100nF Short Circuit ) (s C10 t c u d 35 ) s ( ct Short Circuit 1µF S1, S2, S6, S7 2mm insulated Plug 10.16mm pitch S8 3 pts connector 2.54mm pitch P1, P2 SMB Plug 5.5 25/30 TS4972 ■ Application Information How we measure the PSRR ? Note on how to use the PSRR curves (page 7) Figure 86: PSRR measurement schematic We have finished a design and we have chosen the components values : Rfeed • Rin=Rfeed=22kΩ • Cin=100nF • Cb=1µF Vripple VCC 6 Vcc 1 Vin- - 7 Vin+ + Vout 1 Now, on fig. 13, we can see the PSRR (input grounded) vs frequency curves. At 217Hz we have a PSRR value of -36dB. In reality we want a value about -70dB. So, we need a gain of 34dB ! Now, on fig. 12 we can see the effect of Cb on the PSRR (input grounded) vs. frequency. With Cb=100µF, we can reach the -70dB value. Rin 8 Vout 2 AV = -1 3 Bypass 5 Standby 4 Bias r P e TS4972 Cb Figure 85: PSRR changes with Cb ■ 2 t e l o Principle of operation • We fixed the DC voltage supply (Vcc) • We fixed the AC sinusoidal ripple voltage (Vripple) • No bypass capacitor Cs is used ) (s s b O The PSRR value for each frequency is: Cin=100nF Cb=1µF PSRR (dB) -40 -50 Cin=100nF Cb=100µF -60 e t e ol -70 10 ■ Rms ( V ri ppl e ) PSRR ( dB ) = 20 x Log 10 -------------------------------------------Rms ( Vs + - Vs - ) Vcc = 5, 3.3 & 2.6V Rfeed = 22k, Rin = 22k Rg = 100Ω, RL = 8Ω Tamb = 25°C 100 s b O 1000 d o r P 10000 100000 Frequency (Hz) Note on PSRR measurement What is the PSRR? The PSRR is the Power Supply Rejection Ratio. It's a kind of SVR in a determined frequency range. The PSRR of a device, is the ratio between a power supply disturbance and the result on the output. We can say that the PSRR is the ability of a device to minimize the impact of power supply disturbances to the output. 26/30 t c u u d o Vs+ + GND Rg 100 Ohms The process to obtain the final curve (Cb=100µF, Cin=100nF, Rin=Rfeed=22kΩ) is a simple transfer point by point on each frequency of the curve on fig. 13 to the curve on fig. 12. The measurement result is shown on the next figure. -30 ) s ( ct Vs- RL Cin Remark : The measure of the Rms voltage is not a Rms selective measure but a full range (2 Hz to 125 kHz) Rms measure. It means that we measure the effective Rms signal + the noise. Mechanical Data 4 TS4972 Mechanical Data Figure 87: TS4972 Footprint Recommendation (Non Solder Mask Defined) 500µm 75µm min. 100µm max. 500µm Φ=250µm Track 500µm Φ=400µm ) s ( ct 150µm min. u d o 500µm r P e Solder mask opening t e l o s b O Pad in Cu 35µm with Flash NiAu (6µm, 0.15µm) Figure 88: Top View Of The Daisy Chain Mechanical Data ( all drawings dimensions are in millimeters 8 7 6 Vin+ Vcc r P e Vin so b O Remarks: let t c u od Vout1 1 ) (s 5 Gnd 2 Stdby Vout2 4 1.6 mm Bypass 3 2.26 mm Daisy chain sample is featuring pins connection two by two. The schematic above is illustrating the way connecting pins each other. This sample is used for testing continuity on board. PCB needs to be designed on the opposite way, where pin connections are not done on daisy chain samples. By that way, just connecting an Ohmeter between pin 8 and pin 1, the soldering process continuity can be tested. Order Codes Package Part Number Temperature Range Marking J TSDC03IJT -40, +85°C • DC3 27/30 TS4972 Mechanical Data Figure 89: Tape & reel specification (top view) 1.5 4 1 A A m µ0 7 + Y zeis ieD 8 t e l o 4 ) (s All dimensions are in mm User direction of feed t c u d s b O 28/30 o r P u d o r P e Die size X + 70µm e t e ol ) s ( ct 1 s b O Package Mechanical Data 5 TS4972 Package Mechanical Data 5.1 Flip-Chip - 8 BUMPS 0.5 0.5 0.5 ■ ■ ■ ■ ■ 1.6 0.5 Die size : (2.26mm ±10%) x (1.6mm ±10%) Die height (including bumps) : 650µm ± 50 Bumps diameter : 315µm ±15µm Silicon thickness : 400µm ±25µm Pitch: 500µm ±10µm r P e t e l o 2.26 400µm 650µm 250µm ) (s Figure 90: Pin Out (top view) s b O Figure 91: Marking (top view) t c u E d s b O ol ete u d o o r P A72 YWW ■ Balls are underneath 29/30 ) s ( ct TS4972 Package Mechanical Data Revision History Date Revision Description of Changes January 2003 1 First Release October 2004 2 Update Mechanical Data for Flip-Chip package ) s ( ct u d o r P e t e l o ) (s s b O t c u d e t e ol o r P s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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