TS612D

TS612 DUAL WIDE BAND OPERATIONAL AMPLIFIER WITH HIGH OUTPUT CURRENT s LOW NOISE : 3nV/√Hz, 1.2pA/√Hz s HIGH OUTPUT CURRENT : 200mA s VERY LOW HARMONIC AND INTERMODULATION DISTORTION s HIGH SLEW RATE : 40V/µs s SPECIFIED FOR 25Ω LOAD DESCRIPTION The TS612 is a dual operational amplifier featuring a high output current (200mA min.), large gain-bandwidth product (130MHz) and capable of driving a 25Ω load with a 160mA output current at ±6V power supply. This device is particularly intended for applications where multiple carriers must be amplified simultaneously with very low intermodulation products. The TS612 is housed in SO20 batwing plastic package for a very low thermal resistance. The TS612 is fitted out with Power Down function in order to decrease the consumption. APPLICATION Power Down 1 D SO-20 Batwing (Plastic Micropackage) PIN CONNECTIONS (top view) 1 2 3 4 5 6 7 8 9 10 Top view 20 Vcc+ 1 Output 1 VccVcc Vcc Vcc Vcc GND Inverting input 1 Non-inverting input 1 Vcc Vcc Vcc Vcc Non-Inverting input 2 Inverting input 2 Power Down 2 _ + 19 18 17 16 15 14 s UPSTREAM line driver for Assymetric Digital Subscriber Line (ADSL) (NT). ORDER CODE Package Part Number TS612ID Temperature Range D -40, +85°C • + _ 13 12 Output 2 11 Vcc+ 2 D = Small Outline Package (SO) - also available in Tape & Reel (DT) May 2000 1/11 TS612 ABSOLUTE MAXIMUM RATINGS Symbol VCC Vid Vin Toper Tstd Tj Rthjc Rthja Pmax. Supply voltage 1) 2) Parameter Value ±7 ±2 ±6 -40 to + 85 -65 to +150 150 25 45 2.6 4) Unit V V V °C °C °C °C/W °C/W W Differential Input Voltage Input Voltage Range 3) Operating Free Air Temperature Range TS612ID Storage Temperature Maximum Junction Temperature Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Area Maximum Power Dissipation (@25°C) Output Short Circuit Duration 1. All voltages values, except differential voltage are with respect to network terminal. 2. Differential voltages are non-inverting input terminal with respect to the inverting input terminal. 3. The magnitude of input and output voltages must never exceed VCC +0.3V. 4. An output current limitation protects the circuit from transient currents. Short-circuits can cause excessive heating. Destructive dissipation can result from short circuit on amplifiers. OPERATING CONDITIONS Symbol VCC Vicm Supply Voltage Common Mode Input Voltage Parameter Value ±2.5 to ±6 (VCC) +2 to (VCC+) -1 Unit V V 2/11 TS612 ELECTRICAL CHARACTERISTICS VCC = ±6Volts, Tamb = 25°C (unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max Unit DC PERFORMANCE Vio ∆Vio Iio Input Offset Voltage Differential Input Offset Voltage Input Offset Current Tamb Tmin. < Tamb < Tmax. Tamb = 25°C Tamb Tmin. < Tamb < Tmax. Tamb Tmin. < Tamb < Tmax. Vic = 2V to 2V, Tamb Tmin. < Tamb < Tmax. Vic = ±6V to ±4V, Tamb Tmin. < Tamb < Tmax. No load, Vout = 0 90 70 70 50 14 mA 88 dB 108 5 0.2 -6 -1 6 10 6 3 5 15 30 mV mV µA µA Iib Input Bias Current CMR Common Mode Rejection Ratio dB SVR ICC Supply Voltage Rejection Ratio Total Supply Current per Operator DYNAMIC PERFORMANCE VOH VOL High Level Output Voltage Low Level Output Voltage Iout = 160mA RL connected to GND Iout = 160mA RL connected to GND Vout = 7V peak RL = 25Ω, Tamb Tmin. < Tamb < Tmax. GBP SR Iout Isink Gain Bandwidth Product Slew Rate Output Short Circuit Current Output Sink Current Vic = ±6V, Tamb Tmin. < Tamb < Tmax. Vic = ±6V, Tamb Tmin. < Tamb < Tmax. RL = 25Ω//15pF RL = 25Ω//15pF 60 40 +200 +180 -200 -180 mA ° ° mA AVCL = +11, f = 20MHz RL = 100Ω AVCL = +7, RL = 50Ω 6500 5000 80 23 130 40 ±320 MHz V/µs mA 4 4.5 -4.5 -4 V V AVD Large Signal Voltage Gain 11000 V/V Isource ΦM14 ΦM6 Output Source Current Phase Margin at AVCL = 14dB Phase Margin at AVCL = 6dB 3/11 TS612 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max Unit NOISE AND DISTORTION en in THD Equivalent Input Noise Voltage Equivalent Input Noise Current Total Harmonic Distortion f = 100kHz f = 100kHz Vout = 4Vpp, f = 100kHz AVCL = -10 RL = 25Ω//15pF Vout = 4Vpp, f = 100kHz AVCL = -10 Load =25Ω//15pF Vout = 4Vpp, f = 100kHz AVCL = +2 Load =25Ω//15pF Vout = 4Vpp, f = 1MHz AVCL = +2 Load =25Ω//15pF Vout = 4Vpp, f = 100kHz AVCL = -10 Load =25Ω//15pF F1 = 80kHz, F2 = 70kHz Vout = 8Vpp, AVCL = -10 Load = 25Ω//15pF F1 = 80kHz, F2 = 70kHz Vout = 8Vpp, AVCL = -10 Load = 25Ω//15pF 3 1.2 -69 nV/√Hz pA/√Hz dB HD2-10 2nd Harmonic Distortion -70 dBc HD2+2 2nd Harmonic Distortion -74 dBc HD3+2 3rd Harmonic Distortion -79 dBc HD3-10 3rd Harmonic Distortion -80 dBc IM2-10 2nd Order Intermodulation Product -77 dBc IM3-10 3rd Order Intermodulation Product -77 dBc 4/11 TS612 POWER DOWN MODE VCC = ±6Volts, Tamb = 25°C Symbol Vpdw Iccpdw Rpdw Cpdw Power Down Mode Current Consumption Power Down Mode Ouput Impedance Power Down Mode Output Capacitance Parameter Pin (1)(7) Thershold Voltage for Power Down Mode Low Level High Level Min. Typ. 0 3.3 Max 0.8 75 3 TBD Unit V µA Ω µA 2 STANDBY CONTROL pin (1) operator 1 Vhigh level Vhigh level Vlow level Vlow level pin (7) operator 2 Vlow level Vhigh level Vlow level Vhigh level OPERATOR STATUS operator 1 Standby Standby Active Active operator 2 Active Standby Active Standby POWER DOWN EQUIVALENT SHEMATIC OUPUT IMPEDANCE IN POWER DOWN MODE In Power Down Mode the output of the driver is in "high impedance" state. It is really the case for the static mode. Regarding the dynamic mode, the impedance decreases due to a capacitive effect of the collector-substrat and base collector junction. The impedance behaviour comes capacitive, typically: 1.4MΩ // 33pF. Vcc + + _ Vcc - . . 32:(5 '2:1 .. . Ouput 5/11 TS612 INTERMODULATION DISTORTION The curves shown below are the measurements results of a single operator wired as an adder with a gain of 15dB. The operational amplifier is supplied by a symmetric ±6V and is loaded with 25Ω. Two synthesizers (Rhode & Schwartz SME) generate two frequencies (tones) (70 & 80kHz or 180 & 280kHz). An HP3585 spectrum analyzer measures the spurious level at different frequencies. The curves are traced for different output levels (the value in the X ax is the value of each tone). The output levels of the two tones are the same. The generators and spectrum analyzer are phase locked to enhance measurement precision. 3rd ORDER INTERMODULATION (2 tones : 70kHz and 80kHz) 3rd ORDER INTERMODULATION (2 tones : 180kHz and 280kHz) 0 -10 -20 0 -10 -20 -30 IM3 (dBc) IM3 (dBc) -30 -40 -50 230kHz 90kHz -40 -50 -60 -70 -80 80kHz 380kHz -60 -70 -80 -90 -100 1 1,5 2 60kHz 220kHz -90 -100 3 3,5 4 4,5 640kHz 740kHz 2,5 1 1,5 2 2,5 3 3,5 4 4,5 Vout peak (V) Vout peak (V) 2nd ORDER INTERMODULATION Spurious measurement @ 100kHz (2 tones : 180kHz and 280kHz) -55 IM2 (dBc) -60 -65 -70 1,5 2 2,5 3 3,5 4 4,5 Vout peak (V) 6/11 TS612 Closed Loop Gain and Phase vs. Frequency Gain=+2, Vcc=±6V, RL=25Ω Closed Loop Gain and Phase vs. Frequency Gain=+6, Vcc=±6V, RL=25Ω 10 200 20 200 Gain 15 0 100 Phase (degrees) 10 Gain 100 Phase (degrees) Gain (dB) -10 Phase Gain (dB) 5 Phase 0 -5 0 0 -20 -100 -10 -15 -100 -30 -200 -20 -200 10kHz 100kHz 1MHz 10MHz 100MHz 10kHz 100kHz 1MHz 10MHz 100MHz Frequency Frequency Closed Loop Gain and Phase vs. Frequency Gain=+11, Vcc=±6V, RL=25Ω Equivalent Input Voltage Noise Gain=+100, Vcc=±6V, no load 30 200 20 Gain 20 100 15 en (nV/VHz) + _ 10k 10 Phase 0 0 Phase (degrees) Gain (dB) 10 100 -10 -20 -30 -100 5 -200 0 100Hz 1kHz 10kHz 100kHz 1MHz Frequency 10kHz 100kHz 1MHz 10MHz Frequency 100MHz Maximum Output Swing Vcc=±6V, RL=25Ω Channel Separation (Xtalk) vs. Frequency XTalk=20Log(V2/V1), Vcc=±6V, RL=25Ω 5 4 3 2 VIN -10 output -20 -30 + 49.9Ω _ V1 1kΩ 25Ω 100Ω + 49.9Ω _ swing (V) Xtalk (dB) 1 0 -1 -2 -3 -4 -5 0 2 input -40 -50 -60 -70 -80 -90 V2 1kΩ 25Ω 100Ω 4 6 8 10 - 100 10kHz 100kHz 1MHz 10MHz Time (µs) Frequency 7/11 TYPICAL APPLICATION : TS612 AS DRIVER FOR ADSL LINE INTERFACES A SINGLE SUPPLY IMPLEMENTATION WITH PASSIVE OR ACTIVE IMPEDANCE MATCHING by C. PRUGNE ADSL CONCEPT Asymmetric Digital Subscriber Line (ADSL), is a new modem technology, which converts the existing twisted-pair telephone lines into access paths for multimedia and high speed data communications. ADSL transmits more than 8 Mbps to a subscriber, and can reach 1Mbps from the subscriber to the central office. ADSL can literally transform the actual public information network by bringing movies, television, video catalogs, remote CD-ROMs, LANs, and the Internet into homes. An ADSL modem is connected to a twisted-pair telephone line, creating three information channels: a high speed downstream channel (up to 1.1MHz) depending on the implementation of the ADSL architecture, a medium speed upstream channel (up to 130kHz) and a POTS (Plain Old Telephone Service), split off from the modem by filters. THE LINE INTERFACE - ADSL Remote Terminal (RT): The Figure1 shows a typical analog line interface used for ADSL. The upstream and downstream signals are separated from the telephone line by using an hybrid circuit and a line transformer. On this note, the accent will be made on the emission path. Figure 1 : Typical ADSL Line Interface The TS612 is used as a dual line driver for the upstream signal. For the remote terminal it is required to create an ADSL modem easy to plug in a PC. In such an application, the driver should be implemented with a +12 volts single power supply. This +12V supply is available on PCI connector of purchase. The figure 2 shows a single +12V supply circuit that uses the TS612 as a remote terminal transmitter in differential mode. Figure 2 : TS612 as a differential line driver with a +12V single supply 1µ 100n 3 +12V 1k + 20 +12V 19 12.5 10n 2_ Vi 47k R1 R2 1:2 Vo 25Ω Hybrid & Transformer 100Ω Vi 1k 10µ 47k 100n 9 + R3 11 +12V 12 Vo 12.5 GND 8_ 100n GND 4,5,6,7,14,15,16,17,18 high output current digital to analog emission (analog) LP filter upstream impedance matching HYBRID CIRCUIT digital treatment TS612 Line Driver analog to digital reception (analog) reception circuits twisted-pair telephone line downstream The driver is biased with a mid supply (nominaly +6V), in order to maintain the DC component of the signal at +6V. This allows the maximum dynamic range between 0 and +12 V. Several options are possible to provide this bias supply (such as a virtual ground using an operational amplifier), such as a two-resistance divider which is the cheapest solution. A high resistance value is required to limit the current consumption. On the other hand, the current must be high enough to bias the inverting input of the TS612. If we consider this bias current (5µA) as the 1% of the current through the resistance divider (500µA) to keep a stable mid supply, two 47kΩ resistances can be used. The input provides two high pass filters with a break frequency of about 1.6kHz which is necessary to remove the DC component of the input signal. To avoid DC current flowing in the primary of the transformer, an output capacitor is used. The 8/11 TS612 1µF capacitance provides a path for low frequencies, the 10nF capacitance provides a path for high end of the spectrum. In differential mode the TS612 is able to deliver a typical amplitude signal of 18V peak to peak. The dynamic line impedance is 100Ω. The typical value of the amplitude signal required on the line is up to 12.4V peak to peak. By using a 1:2 transformer ratio the reflected impedance back to the primary will be a quarter (25Ω) and therefore the amplitude of the signal required with this impedance will be the half (6.2 V peak to peak). Assuming the 25Ω series resistance (12.5 Ω for both outputs) necessary for impedance matching, the output signal amplitude required is 12.4 V peak to peak. This value is acceptable for the TS612. In this case the load impedance is 25Ω for each driver. For the ADSL upstream path, a lowpass filter is absolutely necessary to cutoff the higher frequencies from the DAC analog output. In this simple non-inverting amplification configuration, it will be easy to implement a Sallen-Key lowpass filter by using the TS612. For ADSL over POTS, a maximum frequency of 135kHz is reached. For ADSL over ISDN, the maximum frequency will be 276kHz. INCREASING THE LINE LEVEL BY USING AN ACTIVE IMPEDANCE MATCHING With passive matching, the output signal amplitude of the driver must be twice the amplitude on the load. To go beyond this limitation an active maching impedance can be used. With this technique it is possible to keep good impedance matching with an amplitude on the load higher than the half of the ouput driver amplitude. This concept is shown in figure3 for a differential line. Figure 3 : TS612 as a differential line driver with an active impedance matching 1µ 100n 3 +12V 1k + 20 +12V 19 Component calculation: Let us consider the equivalent circuit for a single ended configuration, figure4. Figure 4 : Single ended equivalent circuit + Rs1 Vi _ R2 Vo° Vo -1 R3 1/2R1 1/2RL Let us consider the unloaded system. Assuming the currents through R1, R2 and R3 as respectively: 2 Vi ( Vi – Vo ° ) ( Vi + Vo ) -------- , ------------------------- and ----------------------R1 R2 R3 As Vo° equals Vo without load, the gain in this case becomes : 2R2 1 + ---------- + R 2 - -----( ) R1 R3 G = Vo noload - = --------------------------------------------------------------Vi 1 – R2 -----R3 The gain, for the loaded system will be (1): 2R2 1 + ---------- + R 2 - -----1 R1 R3 Vo ( withload ) = -- ---------------------------------- ,( 1 ) GL = ----------------------------------2 Vi 1 – R2 -----R3 As shown in figure5, this system is an ideal generator with a synthesized impedance as the internal impedance of the system. From this, the output voltage becomes: Vo = ( ViG ) – ( RoIout ) ,( 2 ) with Ro the synthesized impedance and Iout the output current. On the other hand Vo can be expressed as: 2R2 2 Vi  1 + ---------- + R - - ----- R 1 R 3 Rs 1 Iout Vo = ---------------------------------------------- – --------------------- ,( 3 ) 2 1–R-----1 – R2 -----R3 R3 12.5 10n 2_ Vi 47k R2 R3 R5 Vo° Vo 1:2 25Ω Vo Hybrid & Transformer R1 100Ω Vi 1k 10µ 47k 100n 9 + R4 11 +12V 12 Vo° 12.5 GND 8_ 100n GND 4,5,6,7,14,15,16,17,18 9/11 TS612 By identification of both equations (2) and (3), the synthesized impedance is, with Rs1=Rs2=Rs: Rs Ro = ---------------- ,( 4 ) 1 – R2 -----R3 GL (gain for the loaded system) R1 R2 (=R4) R3 (=R5) Rs GL is fixed for the application requirements GL=Vo/Vi=0.5(1+2R2/R1+R2/R3)/(1-R2/R3) 2R2/[2(1-R2/R3)GL-1-R2/R3] Abritrary fixed R2/(1-Rs/0.5RL) 0.5RL(k-1) Figure 5 : Equivalent schematic. Ro is the synthesized impedance CAPABILITIES The table below shows the calculated components for different values of k. In this case R2=1000Ω and the gain=16dB. The last column displays the maximum amplitude level on the line regarding the TS612 maximum output capabilities (18Vpp diff.) and a 1:2 line transformer ratio. Active matching R1 (Ω) 820 490 360 270 240 Passive R3 (Ω) Rs (Ω) TS612 Output Level to get 12.4Vpp on the line (Vpp diff) 8 8.7 9.3 9.9 10.5 12.4 Maximum Line level (Vpp diff) 27.5 25.7 25.3 23.7 22.3 18 Ro Iout Vi.Gi 1/2RL k Unlike the level Vo° required for a passive impedance, Vo° will be smaller than 2Vo in our case. Let us write Vo°=kVo with k the matching factor varying between 1 and 2. Assuming that the current through R3 is negligeable, it comes the following resistance divider: kVoRL Ro = --------------------------RL + 2 Rs 1 1.3 1.4 1.5 1.6 1.7 1500 3.9 1600 5.1 2200 6.2 2400 7.5 3300 9.1 matching After choosing the k factor, Rs will equal to 1/2RL(k-1). A good impedance matching assumes: 1 R o = -- RL ,( 5 ) 2 MEASUREMENT OF THE POWER CONSUMPTION IN THE ADSL APPLICATION Conditions: Passive impedance matching Transformer turns ratio: 2 Maximun level required on the line: 12.4Vpp Maximum output level of the driver: 12.4Vpp Crest factor: 5.3 (Vp/Vrms) The TS612 power consumption during emission on 900 and 4550 meter twisted pair telephone lines: 450mW From (4) and (5) it becomes: 2 Rs R2 ------ = 1 – --------- , ( 6 ) RL R3 By fixing an arbitrary value for R2, (6) gives: R2 R 3 = ------------------2 Rs 1 – --------RL Finally, the values of R2 and R3 allow us to extract R1 from (1), and it comes: 2R2 R 1 = --------------------------------------------------------- ,( 7 ) R 2 GL – 1 – R 2 2  1 – ---------- R 3 R3 with GL the required gain. 10/11 TS612 PACKAGE MECHANICAL DATA 8 PINS - PLASTIC MICROPACKAGE (SO) Millimeters Dim. Min. A a1 a2 b b1 C c1 D E e e3 F L M S 0.1 0.35 0.23 0.5 45° (typ.) 12.6 10 1.27 11.43 7.4 0.5 7.6 1.27 0.75 8° (max.) 0.291 0.020 13.0 10.65 0.496 0.394 Typ. Max. 2.65 0.3 2.45 0.49 0.32 Min. 0.004 0.014 0.009 Inches Typ. Max. 0.104 0.012 0.096 0.019 0.013 0.020 0.512 0.419 0.050 0.450 0.299 0.050 0.030 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom © http://www.st.com 11/11