TS922AIDT

TS922, TS922A Datasheet Rail-to-rail, high output current, dual operational amplifier Features Flip-chip with backcoating • • • • • • • • • Rail-to-rail input and output Low noise: 9 nV/√Hz Low distortion High output current: 80 mA (able to drive 32 Ω loads) High-speed: 4 MHz, 1 V/μs Operating from 2.7 to 12 V Low input offset voltage: 900 μV max. (TS922A) ESD internal protection: 2 kV Latch-up immunity SO8 Applications • • • • TSSOP8 Product status link TS922 and TS922A Line drivers and actuator drivers Portable speakers Instrumentation with low noise as key factor Multimedia systems and portable equipments Description The TS922 and the TS922A devices are rail-to-rail dual BiCMOS operational amplifiers optimized and fully specified for 3 V and 5 V operations. These devices have high output currents which allow low-load impedances to be driven. Very low noise, low distortion, low offset, and a high output current capability make these devices an excellent choice for high quality, low voltage, or battery operated audio systems. The devices are stable for capacitive loads up to 500 pF. DS1117 - Rev 13 - July 2018 For further information contact your local STMicroelectronics sales office. www.st.com TS922, TS922A Pin diagrams 1 Pin diagrams Figure 1. Pinout for Flip-chip package (top view) Figure 2. Pin connections for SO8 and TSSOP8 (top view) DS1117 - Rev 13 page 2/18 TS922, TS922A Absolute maximum ratings and operating conditions 2 Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings (AMR) Symbol Parameter VCC Supply voltage Vid Differential input voltage (2) Vin Input voltage (3) Tstg Storage temperature Value (1) 14 ±1 -65 to 150 Maximum junction temperature 150 — Soldering temperature (10 s), leaded version 250 — Soldering temperature (10 s), unleaded version 260 Rthjc Thermal resistance junction-to-ambient (4) Thermal resistance junction-to-case (4) HBM: human body model ESD MM: machine model V (VCC-) - 0.3 to (VCC+) + 0.3 Tj Rthja Unit Flip-chip 90 SO8 125 TSSOP8 120 SO8 40 TSSOP8 37 (5) 120 — Latch-up immunity — Output short-circuit duration °C/W 2000 (6) CDM: charged device model °C (7) V 1500 200 mA See note (8) 1. All voltage values, except the differential voltage are with respect to network ground terminal. 2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal. If Vid > ±1 V, the maximum input current must not exceed ±1 mA. In this case (Vid > ±1 V), an input series resistor must be added to limit the input current. 3. Do not exceed 14 V. 4. Short-circuits can cause excessive heating. Destructive dissipation can result from simultaneous shortcircuits on all amplifiers. These values are typical. 5. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin combinations with other pins floating. 6. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω). This is done for all couples of pin combinations with other pins floating. 7. Charged device model: all pins and plus package are charged together to the specified voltage and then discharged directly to ground. 8. There is no short-circuit protection inside the device: short-circuits from the output to VCC can cause excessive heating. The maximum output current is approximately 80 mA, independent of the magnitude of VCC. Destructive dissipation can result from simultaneous short-circuits on all amplifiers. Table 2. Operating conditions DS1117 - Rev 13 Symbol Parameter Value VCC Supply voltage 2.7 to 12 Vicm Common mode input voltage range (VCC-) - 0.2 to (VCC+) + 0.2 Toper Operating free air temperature range -40 to 125 Unit V °C page 3/18 TS922, TS922A Electrical characteristics 3 Electrical characteristics Table 3. Electrical characteristics measured at VCC = 3 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL connected to VCC/2 (unless otherwise specified) Symbol Parameter Test conditions Min. Typ. TS922 Vio ΔVio/ΔT Iio Iib VOH Input offset voltage Input bias current High level output voltage TS922A 0.9 TS922EIJT 1.5 Tmin ≤ Tamb ≤ Tmax, TS922 5 Tmin ≤ Tamb ≤ Tmax, TS922A 1.8 Tmin ≤ Tamb ≤ Tmax, TS922EIJT 2.5 2 Vout = VCC/2 1 Tmin ≤ Tamb ≤ Tmax Vout = VCC/2 15 Tmin ≤ Tamb ≤ Tmax Low level output voltage Avd Large signal voltage gain 2.90 Tmin ≤ Tamb ≤ Tmax 2.90 RL = 600 Ω 2.87 Tmin ≤ Tamb ≤ Tmax 2.87 Total supply current GBP Gain bandwidth product CMR Common mode rejection ratio SVR Supply voltage rejection ratio Io Output short-circuit current DS1117 - Rev 13 100 nA V 2.63 RL= 10 kΩ 50 Tmin ≤ Tamb ≤ Tmax 50 RL = 600 Ω 100 Tmin ≤ Tamb ≤ Tmax 100 RL = 32 Ω 180 RL= 10 kΩ, Vout = 2 Vp - p 200 mV 70 RL = 600 Ω, Vout = 2 Vp - p Tmin ≤ Tamb ≤ Tmax ICC 30 100 RL= 10 kΩ Tmin ≤ Tamb ≤ Tmax mV μV/°C 30 RL = 32 Ω VOL Unit 3 Input offset voltage drift Input offset current Max. 35 V/mV 15 RL = 32 Ω, Vout = 2 Vp - p 16 No load, Vout = VCC/2 2 Tmin ≤ Tamb ≤ Tmax 3 3.2 RL = 600 Ω 4 Vicm = 0 to 3 V 60 Tmin ≤ Tamb ≤ Tmax 56 VCC = 2.7 to 3.3 V 60 Tmin ≤ Tamb ≤ Tmax 60 50 80 85 80 mA MHz dB dB mA page 4/18 TS922, TS922A Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit 0.7 1.3 V/μs SR Slew rate ɸm Phase margin at unit gain RL = 600 Ω, CL = 100 pF 68 Degrees Gm Gain margin RL = 600 Ω, CL = 100 pF 12 dB en Equivalent input noise voltage f = 1 kHz 9 nV/√Hz Total harmonic distortion Vout = 2 Vp - p , f = 1 kHz, Av = 1, RL = 600 Ω 0.005 % 120 dB THD Cs Channel separation Table 4. Electrical characteristics measured at VCC = 5 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. TS922 Vio ΔVio/ΔT Iio Iib VOH Input offset voltage Input bias current High level output voltage TS922A 0.9 TS922EIJT 1.5 Tmin ≤ Tamb ≤ Tmax, TS922 5 Tmin ≤ Tamb ≤ Tmax, TS922A 1.8 Tmin ≤ Tamb ≤ Tmax, TS922EIJT 2.5 2 Vout = VCC/2 1 Tmin ≤ Tamb ≤ Tmax Vout = VCC/2 15 Tmin ≤ Tamb ≤ Tmax Low level output voltage Avd Large signal voltage gain 4.9 Tmin ≤ Tamb ≤ Tmax 4.9 RL = 600 Ω 4.85 Tmin ≤ Tamb ≤ Tmax 4.85 Total supply current DS1117 - Rev 13 100 4.4 50 Tmin ≤ Tamb ≤ Tmax 50 RL = 600 Ω 120 Tmin ≤ Tamb ≤ Tmax 120 RL = 32 Ω 300 RL= 10 kΩ, Vout = 2 Vp - p 200 mV 70 RL = 600 Ω, Vout = 2 Vp - p 35 V/mV 20 RL = 32 Ω, Vout = 2 Vp - p 16 No load, Vout = VCC/2 2 Tmin ≤ Tamb ≤ Tmax nA V RL= 10 kΩ Tmin ≤ Tamb ≤ Tmax Icc 30 100 RL= 10 kΩ Tmin ≤ Tamb ≤ Tmax mV μV/°C 30 RL = 32 Ω VOL Unit 3 Input offset voltage drift Input offset current Max. 3 3.2 mA page 5/18 TS922, TS922A Electrical characteristics Symbol Parameter GBP Gain bandwidth product CMR Common mode rejection ratio SVR Io Supply voltage rejection ratio Conditions Min. RL = 600 Ω Typ. 4 Vicm = 0 to 5 V 60 Tmin ≤ Tamb ≤ Tmax 56 VCC = 4.5 to 5.5 V 60 Tmin ≤ Tamb ≤ Tmax 60 Max. Unit MHz 80 85 dB Output short-circuit current 50 80 mA SR Slew rate 0.7 1.3 V/μs ɸm Phase margin at unit gain 68 Degrees Gm Gain margin 12 dB en Equivalent input noise voltage f = 1 kHz 9 nV/√Hz Total harmonic distortion Vout = 2 Vp - p , f = 1 kHz, Av = 1, RL = 600 Ω 0.005 % 120 dB THD Cs Channel separation DS1117 - Rev 13 RL = 600 Ω, CL =100 pF page 6/18 TS922, TS922A Electrical characteristic curves 4 Electrical characteristic curves Figure 4. Total supply current vs. supply voltage Supply current (mA) Output short-circuit current (mA) Figure 3. Output short-circuit current vs. output voltage Sink VCC = 0/3 V Source Output voltage (V) Supply voltage (V) Figure 5. Voltage gain and phase vs. frequency 60 Figure 6. Equivalent input noise voltage vs. frequency 180 30 Gain G ain ( d B) 120 RI = 10 kΩ CI = 100 pF 20 60 0 Phase (deg.) 40 Equi valent input noise (nV/√Hz) Phase 0 25 V CC = ±1.5 V 20 R L = 100 Ω 15 10 5 0 -20 1E+02 1E+03 1E+04 1E+05 1E+06 1E+07 0.01 -60 1E+08 0.1 1 10 100 Frequency (kHz) Frequency (Hz) Figure 7. THD + noise vs. frequency (RL = 2 kΩ, Vo = 10 Vpp, VCC = ± 6 V) Figure 8. THD + noise vs. frequency (RL = 32 Ω, Vo = 4 Vpp, VCC = ± 2.5 V) 0.04 0.02 THD + noise (%) THD + noise (%) 0.032 0.015 R L = 2 kΩ, Vo = 10 Vpp V CC = ±6 V, Av = 1 0.01 R L = 32 Ω, Vo = 4 Vpp V CC = ±2.5 V, Av = 1 0.024 0.016 0.005 0.008 0 0 0.01 0.1 1 Frequency (kHz) DS1117 - Rev 13 10 100 0.01 0.1 1 10 100 Frequency (kHz) page 7/18 TS922, TS922A Electrical characteristic curves Figure 9. THD + noise vs. frequency (RL = 32 Ω, Vo = 2 Vpp, VCC = ± 1.5 V) Figure 10. THD + noise vs. output voltage (RL = 600 Ω, f = 1 kHz, VCC = 0/3 V) 10,000 0.7 THD + noise (%) THD + noise (%) 0.6 0.5 R L = 32 Ω, Vo = 2 Vpp 0.4 VCC = ±1.5 V, Av = 10 0.3 0.2 1,000 0,100 R L = 600 Ω, f = 1 kHz V CC = 0/3 V, Av = 10 0,010 0.1 0 0,001 0.01 0.1 1 10 0 100 0,2 0,4 Frequency (kHz) 0,6 0,8 1 1,2 V out (Vrms) Figure 11. THD + noise vs. output voltage (RL = 32 Ω, f = 1 kHz, VCC = ± 1.5 V) Figure 12. THD + noise vs. output voltage (RL = 2 kΩ, f = 1 kHz, VCC = ± 1.5 V) 10 1 THD + noise (%) THD + noise (%) 10 1 R = 32 Ω, f = 1 kHz L VCC = ±1.5 V, Av = 1 0.1 0.1 R = 2 kΩ, f = 1 kHz L V = ±1.5 V, Av = -1 CC 0.01 0.01 0 0.2 0.4 V 0.6 out 0. 0.001 (Vrms) 0 0.2 0.4 0.6 V out 0.8 1 1.2 (Vrms) Figure 13. Open loop gain and phase vs. frequency 50 180 120 C = 500 pF L 30 20 60 Phase (deg.) Gain (dB) 40 10 0 0 1E+2 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8 Frequency (Hz) DS1117 - Rev 13 page 8/18 TS922, TS922A Package information 5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.1 8-bump Flip-chip package information Figure 14. 8-bump Flip-chip package dimensions (top view) 1. DS1117 - Rev 13 Die size: 1600 µm x 1600 µm ±30 µm, Die height: 350 µm ±20 µm, die height (including bumps): 650 µm, bump diameter: 315 µm ±50 µm, bump height: 250 µm ±40 µm, pitch: 500 µm ±10 µm, backcoating. page 9/18 TS922, TS922A 8-bump Flip-chip package information Figure 15. 8-bump Flip-chip recommended footprint (TS922EIJT) Figure 16. 8-bump Flip-chip marking (top view) 1. 2. 3. 4. DS1117 - Rev 13 ST logo Part number Date code: Y = year, WW = week This dot indicates the bump corner 1A page 10/18 TS922, TS922A 8-bump Flip-chip package information Figure 17. 8-bump Flip-chip tape and reel specification (top view) 1 A 1 A Use r direc tion of fee d 1. DS1117 - Rev 13 Device orientation: the devices are oriented in the carrier pocket with bump number A1 adjacent to the pocket holes. page 11/18 TS922, TS922A SO8 package information 5.2 SO8 package information Figure 18. SO8 package outline Table 5. SO8 package mechanical data Dimensions Millimeters Ref. Min. Typ. A Max. Min. Typ. 1.75 0.25 Max. 0.069 A1 0.10 A2 1.25 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.010 D 4.80 4.90 5.00 0.189 0.193 0.197 E 5.80 6.00 6.20 0.228 0.236 0.244 E1 3.80 3.90 4.00 0.150 0.154 0.157 e 0.004 0.010 0.049 1.27 0.050 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 L1 k ccc DS1117 - Rev 13 Inches 1.04 0° 0.040 8° 0.10 0° 8° 0.004 page 12/18 TS922, TS922A TSSOP8 package information 5.3 TSSOP8 package information Figure 19. TSSOP8 package outline aaa Table 6. TSSOP8 mechanical data Dimensions Millimeters Ref. Min. Typ. A Max. Min. Typ. 1.2 A1 0.05 A2 0.80 b Max. 0.047 0.15 0.002 1.05 0.031 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 D 2.90 3.00 3.10 0.114 0.118 0.122 E 6.20 6.40 6.60 0.244 0.252 0.260 E1 4.30 4.40 4.50 0.169 0.173 0.177 e DS1117 - Rev 13 Inches 1.00 0.65 k 0° L 0.45 0.60 0.006 0.039 0.041 0.0256 8° 0° 0.75 0.018 8° 0.024 L1 1 0.039 aaa 0.1 0.004 0.030 page 13/18 TS922, TS922A Ordering information 6 Ordering information Table 7. Ordering information Order code Temperature range Package Packing TS922ID 922I TS922IDT SO8 TS922AID Tube or tape and reel TS922AIDT TS922IYDT (1) TS922AIYDT (1) TS922IPT -40 °C to 125 °C TS922AIYPT TS922EIJT 922AIY 922I Tape and reel (1) (1) TSSOP8 (automotive grade) Flip-chip with backcoating 922AI 922IY SO8 (automotive grade) TSSOP8 TS922AIPT TS922IYPT Marking 922AI 922IY 922AY 922 1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 and Q 002 or equivalent. DS1117 - Rev 13 page 14/18 TS922, TS922A Revision history Table 8. Document revision history Date Revision Changes 01-Feb-2001 1 First release. 01-Jul-2004 2 Flip-chip package inserted in the document. 02-May-2005 3 Modifications in AMR Table 1 (explanation of Vid and Vi limits, ESD MM and CDM values added, Rthja added). 01-Aug-2005 4 PPAP references inserted in the datasheet, see Table 8. 01-Mar-2006 5 TS922EIJT part number inserted in the datasheet, see Table 8. 26-Jan-2007 6 Modifications in AMR Table 1 (Rthjc added), parameter limits on full temperature range added in Table 3 and Table 4. 12-Nov-2007 7 Added notes on ESD in AMR table. Re-formatted package information. Added notes for automotive grade in order codes table. Document reformatted. 02-Feb-2010 8 Added root part number TS922A on cover page. Removed TS922AIYD order code from Table 8. Added MiniSO8 package. Modified test conditions for CMR in Table 3 and Table 4. 15-Jan-2013 9 Replaced VDD by VCC- in title of Table 3, Table 4, and Table 5. Updated titles of Figure 7 to Figure 12 (added conditions to differentiate them). Removed TS922IYD device from Table 8. Minor corrections throughout document. Features: updated package information for Flip-chip Figure 2: Updated title Table 1: updated footnotes 5, 6, and 7 04-Jun-2013 10 Table 3 and Table 4: replaced DVio with ΔVio/ΔT Figure 14: added backcoating to package information Figure 16: updated footnote 3 Table 8: updated package information for Flip-chip 27-Jun-2013 11 Figure 14: updated to include new height for backcoating Updated document layout Removed MiniSO8 and DIP8 packages 20-Jan-2016 12 Updated cover image: removed J, D (plastic micropackage), and P (thin shrink small outline package) respectively from Flip-chip with backcoating, SO8, and TSSOP packages. Table 6: updated SO8 information for min “k” parameter (mm dimensions) Table 7: updated “aaa” information. These are “typ” not "max" values. Table 8: "Order codes": removed following order codes: TS922IST, TS922AIST, TS922IN, TS922IYST. TS922AIYST, and TS922IJT. DS1117 - Rev 13 page 15/18 TS922, TS922A Date Revision Changes Updated features and applications in cover page. Updated Figure 1. Pinout for Flip-chip package (top view). 20-Jul-2018 13 Updated Section 6 Ordering information. Removed "Macromodel" section. Minor text changes. DS1117 - Rev 13 page 16/18 TS922, TS922A Contents Contents 1 Pin diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 5.1 8-bump Flip-chip package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 SO8 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 DS1117 - Rev 13 page 17/18 TS922, TS922A IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS1117 - Rev 13 page 18/18