TSA1203
DUAL-CHANNEL, 12-BIT, 40MSPS, 230mW A/D CONVERTER
■ Low power consumption: 230mW@40Msps
■ Single supply voltage: 2.5V
D1
D0(LSB)
VCCBE
GNDBE
44 43 42
VCCBI
VCCBI
OEB
48 47 46 45
AVCC
AVCC
INCMI
index
corner
REFMI
REFPI
■
■
■
■
■
■
Independent supply for CMOS output stage
with 2.5V/3.3V capability
SFDR= -68.3 dBc @ Fin=10MHz
1GHz analog bandwidth Track-and-Hold
Common clocking between channels
Dual simultaneous Sample and Hold inputs
Multiplexed outputs
Built-in reference voltage with external bias
capability
PIN CONNECTIONS (top view)
41 40 39 38 37
36 D2
AGND 1
2
35 D3
AGND 3
34 D4
INIB 4
33 D5
INI
AGND 5
32 D6
IPOL 6
31 D7
TSA1203
AVCCB 7
30 D8
29 D9
DESCRIPTION
AGND 8
The TSA1203 is a new generation of high speed,
dual-channel Analog to Digital converter processed in a mainstream 0.25µm CMOS technology yielding high performances and very low power
consumption.
The TSA1203 is specifically designed for applications requiring very low noise floor, high SFDR
and good isolation between channels. It is based
on a pipeline structure and digital error correction
to provide high static linearity at Fs=40Msps, and
Fin=10MHz.
For each channel, a voltage reference is integrated to simplify the design and minimize external
components. It is nevertheless possible to use the
circuit with external references.
Each ADC outputs are multiplexed in a common
bus with small number of pins. A tri-state capability is available for the outputs, allowing chip selection. The inputs of the ADC must be differentially
driven.
The TSA1203 is available in extended (0 to
+85°C) temperature range, in a small 48 pins
TQFP package.
AGND 10
27 D11(MSB)
INBQ 11
26 VCCBE
INQ 9
GNDBI
DVCC
DGND
SELECT
CLK
DGND
DVCC
AVCC
AGND
INCMQ
CLK
SELECT OEB
VCCBE
Timing
VINI
AD 12
I channel
VINBI
VINCMI
12
common mode
VREFPI
REF I
VREFMI
IPOL
M
U
X
Polar.
12
12
Buffers
D0
TO
D11
VREFPQ
REF Q
VREFMQ
VINCMQ
common mode
AD 12
Q channel
12
GNDBE
7 × 7 mm TQFP48
Package
Conditioning
TSA1203IF
0°C to +85°C
TQFP48
Tray
SA1203I
TSA1203IFT
0°C to +85°C
TQFP48
Tape & Reel
SA1203I
February 2003
REFMQ
+2.5V/3.3V
PACKAGE
Temperature
Range
EVAL1203/BA
17 18 19 20 21 22 23 24
GND
ORDER CODE
Part Number
14 15 16
BLOCK DIAGRAM
VINBQ
Medical imaging and ultrasound
3G basestation
I/Q signal processing applications
High speed data acquisition system
Portable instrumentation
13
REFPQ
■
■
■
■
■
25 GNDBE
AGND 12
VINQ
APPLICATIONS
28 D10
Marking
Evaluation board
1/20
TSA1203
CONDITIONS
AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps, Fin=10.13MHz, Vin@ -1dBFS, VREFP=0.8V, VREFM=0V
Tamb = 25°C (unless otherwise specified)
DYNAMIC CHARACTERISTICS
Symbol
SFDR
Parameter
Test conditions
Min
Spurious Free Dynamic Range
SNR
Signal to Noise Ratio
THD
Total Harmonics Distortion
60.7
Typ
Max
Unit
-68.3
-59.5
dBc
66.1
-66.6
dB
-58
dBc
SINAD
Signal to Noise and Distortion Ratio
56.5
62.8
dB
ENOB
Effective Number of Bits
9.1
10.3
bits
Min
Typ
TIMING CHARACTERISTICS
Symbol
Parameter
Test conditions
Max
Unit
40
MHz
55
%
FS
Sampling Frequency
0.5
DC
Clock Duty Cycle
45
50
TC1
Clock pulse width (high)
22.5
25
ns
TC2
Clock pulse width (low)
22.5
25
ns
Tod
Data Output Delay (Clock edge to Data Valid)
9
ns
10pF load capacitance
Tpd I
Data Pipeline delay for I channel
7
cycles
Tpd Q
Data Pipeline delay for Q channel
7.5
cycles
Ton
Falling edge of OEB to digital output valid data
1
ns
Toff
Rising edge of OEB to digital output tri-state
1
ns
2/20
TSA1203
TIMING DIAGRAM
Simultaneous sampling
on I/Q channels
N+4
N+5
N+13
N+3
N+12
N+6
I
N-1
N
N+11
N+7
N+2
N+1
N+8
N+9
Q
N+10
CLK
Tpd I + Tod
Tod
SELECT
CLOCK AND SELECT CONNECTED TOGETHER
OEB
sample N-8
I channel
sample N-6
Q channel
sample N
Q channel
sample N+1
Q channel
sample N+2
Q channel
DATA
OUTPUT
sample N-9
I channel
sample N-7
Q channel
sample N+1 sample N+2
I channel
I channel
sample N+3
I channel
PIN CONNECTIONS (top view)
D1
D0(LSB)
VCCBE
GNDBE
VCCBI
44 43 42
VCCBI
OEB
AVCC
47 46 45
AVCC
REFMI
48
INCMI
REFPI
index
corner
41 40 39 38 37
36 D2
AGND 1
2
35 D3
AGND 3
34 D4
INIB 4
33 D5
INI
AGND 5
32 D6
IPOL 6
31 D7
TSA1203
AVCCB 7
30 D8
29 D9
AGND 8
INQ 9
28 D10
27 D11(MSB)
AGND 10
INBQ 11
26 VCCBE
AGND 12
25 GNDBE
GNDBI
DVCC
DGND
AVCC
SELECT
REFMQ
CLK
REFPQ
DGND
23 24
DVCC
17 18 19 20 21 22
AGND
14 15 16
INCMQ
13
3/20
TSA1203
PIN DESCRIPTION
Pin No
Name
Description
Observation
1
AGND
2
INI
3
AGND
4
INBI
5
AGND
6
IPOL
Analog bias current input
7
AVCC
Analog power supply
8
AGND
Analog ground
Analog ground
0V
I channel analog input
Analog ground
0V
I channel inverted analog input
0V
9
INQ
AGND
Analog ground
11
INBQ
Q channel inverted analog input
AGND
Analog ground
REFPQ
Q channel top reference voltage
14
REFMQ
Q channel bottom reference
voltage
15
INCMQ
Q channel input common mode
16
AGND
Analog ground
17
AVCC
Analog power supply
GNDBE
Digital buffer ground
0V
VCCBE
Digital Buffer power supply
2.5V/3.3V
D11(MSB) Most Significant Bit output
D10
Digital output
CMOS output (2.5V/3.3V)
Digital output
CMOS output (2.5V/3.3V)
2.5V
31
D7
Digital output
CMOS output (2.5V/3.3V)
0V
32
D6
Digital output
CMOS output (2.5V/3.3V)
33
D5
Digital output
CMOS output (2.5V/3.3V)
34
D4
Digital output
CMOS output (2.5V/3.3V)
35
D3
Digital output
CMOS output (2.5V/3.3V)
0V
36
D2
Digital output
CMOS output (2.5V/3.3V)
37
D1
Digital output
CMOS output (2.5V/3.3V)
38
D0(LSB)
Least Significant Bit output
CMOS output (2.5V/3.3V)
39
VCCBE
Digital Buffer power supply
2.5V/3.3V - See Application
Note
0V
40
GNDBE
Digital buffer ground
0V
2.5V
41
VCCBI
Digital Buffer power supply
2.5V
0V
DVCC
Digital power supply
2.5V
42
VCCBI
DGND
Digital ground
0V
43
OEB
CLK
SELECT
22
23
24
CMOS output (2.5V/3.3V)
D9
19
21
CMOS output (2.5V/3.3V)
Digital output
D8
18
20
Observation
29
0V
13
25
26
27
Description
30
Q channel analog input
12
Name
28
Analog ground
10
Pin No
Digital Buffer power supply
2.5V
Output Enable input
2.5V/3.3V CMOS input
Clock input
2.5V CMOS input
44
AVCC
Analog power supply
2.5V
Channel selection
2.5V CMOS input
45
AVCC
Analog power supply
2.5V
DGND
Digital ground
0V
46
INCMI
I channel input common mode
DVCC
Digital power supply
2.5V
47
REFMI
I channel bottom reference voltage 0V
GNDBI
Digital buffer ground
0V
48
REFPI
I channel top reference voltage
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Symbol
AVCC
DVCC
VCCBE
VCCBI
IDout
Tstg
ESD
Parameter
Analog Supply voltage
Digital Supply voltage
1)
1)
Digital buffer Supply voltage
1)
Digital buffer Supply voltage
Digital output current
Storage temperature
1)
HBM: Human Body Model2)
CDM: Charged Device
Model3)
Latch-up Class4)
Values
Unit
0 to 3.3
V
0 to 3.3
V
0 to 3.6
V
0 to 3.3
V
-100 to 100
+150
mA
°C
2
1.5
kV
A
1). All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3V or VCC
2). ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5kΩ
3). Discharge to Ground of a device that has been previously charged.
4). Corporate ST Microelectronics procedure number 0018695
4/20
TSA1203
OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
AVCC
Analog Supply voltage
2.25
2.5
2.7
V
DVCC
Digital Supply voltage
2.25
2.5
2.7
V
VCCBE
External Digital buffer Supply voltage
2.25
2.5
3.5
V
VCCBI
Internal Digital buffer Supply voltage
2.25
2.5
2.7
V
Forced top voltage reference
0.94
1.4
V
0
0.4
V
0.2
1
V
VREFPI
VREFPQ
VREFMI
Forced bottom reference voltage
VREFMQ
INCMI
INCMQ
Forced input common mode voltage
ANALOG INPUTS
Symbol
Parameter
VIN-VINB Full scale reference voltage
Test conditions
Differential inputs mandatory
Min
Typ
Max
Unit
1.1
2.0
2.8
Vpp
Cin
Input capacitance
7.0
pF
Req
Equivalent input resistor
10
KΩ
BW
Analog Input Bandwidth
1000
MHz
ERB
Effective Resolution Bandwidth
70
MHz
Vin@Full Scale, Fs=40Msps
DIGITAL INPUTS AND OUTPUTS
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
0
0.8
V
Clock and Select inputs
VIL
Logic "0" voltage
VIH
Logic "1" voltage
2.0
2.5
V
OEB input
VIL
Logic "0" voltage
VIH
Logic "1" voltage
0
0.25 x
VCCBE
0.75 x
VCCBE
VCCBE
V
V
Digital Outputs
VOL
VOH
Logic "0" voltage
Logic "1" voltage
Iol=10µA
Ioh=10µA
IOZ
High Impedance leakage current OEB set to VIH
CL
Output Load Capacitance
0
0.1 x
VCCBE
0.9 x
VCCBE
VCCBE
-1.67
0
V
V
1.67
µA
15
pF
5/20
TSA1203
CONDITIONS
AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=0.8V, VREFM=0V
Tamb = 25°C (unless otherwise specified)
REFERENCE VOLTAGE
Symbol
VREFPI
VREFPQ
VINCMI
VINCMQ
Parameter
Test conditions
Min
Typ
Max
Unit
Top internal reference voltage
0.81
0.88
0.94
V
Input common mode voltage
0.41
0.46
0.50
V
POWER CONSUMPTION
Symbol
Parameter
Min
Typ
Max
Unit
ICCA
Analog Supply current
82
96.5
mA
ICCD
Digital Supply Current
4.4
4.9
mA
ICCBE
Digital Buffer Supply Current (10pF load)
6.6
9.4
mA
ICCBI
Digital Buffer Supply Current
274
440
µA
Power consumption in normal operation mode
230
271
mW
Thermal resistance (TQFP48)
80
Pd
Rthja
°C/W
ACCURACY
Symbol
Parameter
Min
Typ
Max
Unit
OE
Offset Error
2.97
LSB
GE
Gain Error
0.1
%
±0.52
LSB
±3
LSB
DNL
Differential Non Linearity
INL
Integral Non Linearity
-
Monotonicity and no missing codes
Guaranteed
MATCHING BETWEEN CHANNELS
Symbol
6/20
Parameter
Min
Typ
Max
Unit
1
%
GM
Gain match
0.04
OM
Offset match
0.88
LSB
PHM
Phase match
1
dg
XTLK
Crosstalk rejection
85
dB
TSA1203
DEFINITIONS OF SPECIFIED PARAMETERS
Signal to Noise Ratio (SNR)
STATIC PARAMETERS
Static measurements are performed through
method of histograms on a 2MHz input signal,
sampled at 40Msps, which is high enough to fully
characterize the test frequency response. The
input level is +1dBFS to saturate the signal.
The ratio of the rms value of the fundamental
component to the rms sum of all other spectral
components in the Nyquist band (fs/2) excluding
DC, fundamental and the first five harmonics.
SNR is reported in dB.
Differential Non Linearity (DNL)
Signal to Noise and Distortion Ratio (SINAD)
The average deviation of any output code width
from the ideal code width of 1 LSB.
Integral Non linearity (INL)
An ideal converter presents a transfer function as
being the straight line from the starting code to the
ending code. The INL is the deviation for each
transition from this ideal curve.
DYNAMIC PARAMETERS
Similar ratio as for SNR but including the harmonic
distortion components in the noise figure (not DC
signal). It is expressed in dB.
From the SINAD, the Effective Number of Bits
(ENOB) can easily be deduced using the formula:
SINAD= 6.02 × ENOB + 1.76 dB.
When the applied signal is not Full Scale (FS), but
has an A0 amplitude, the SINAD expression
becomes:
Dynamic measurements are performed by
spectral analysis, applied to an input sine wave of
various frequencies and sampled at 40Msps.
The input level is -1dBFS to measure the linear
behavior of the converter. All the parameters are
given without correction for the full scale amplitude performance except the calculated ENOB
parameter.
SINAD2Ao =6.02 × ENOB + 1.76 dB + 20 log (2A 0/
FS)
Spurious Free Dynamic Range (SFDR)
The ENOB is expressed in bits.
The ratio between the power of the worst spurious
signal (not always an harmonic) and the amplitude
of fundamental tone (signal power) over the full
Nyquist band. It is expressed in dBc.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first five harmonic
distortion components to the rms value of the
fundamental line. It is expressed in dB.
SINAD2Ao =SINADFull Scale+ 20 log (2A0/FS)
Analog Input Bandwidth
The maximum analog input frequency at which the
spectral response of a full power signal is reduced
by 3dB. Higher values can be achieved with
smaller input levels.
Effective Resolution Bandwidth (ERB)
The band of input signal frequencies that the ADC
is intended to convert without loosing linearity i.e.
the maximum analog input frequency at which the
SINAD is decreased by 3dB or the ENOB by 1/2
bit.
Pipeline delay
Delay between the initial sample of the analog
input and the availability of the corresponding
digital data output, on the output bus. Also called
data latency. It is expressed as a number of clock
cycles.
7/20
TSA1203
Static parameter: Integral Non Linearity
Fs=40MSPS; Icca=60mA; Fin=2MHz
2.5
2
INL (LSBs)
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
500
1000
1500
2000
2500
3000
3500
4000
2500
3000
3500
4000
Output Code
Static parameter: Differential Non Linearity
Fs=40MSPS; Icca=60mA; Fin=2MHz
0.6
DNL (LSBs)
0.4
0.2
0
-0.2
-0.4
-0.6
0
500
1000
1500
2000
Output Code
Linearity vs. Fs
Fin=5MHz
Distortion vs. Fs
Fin=5MHz
12
ENOB_I
75
11
10.5
70
10
SNR_I
9.5
SNR_Q
65
9
8.5
60
SINAD_I
8
SINAD_Q
7.5
55
7
35
40
45
Fs (MHz)
8/20
-40
11.5
50
Dynamic parameters (dBc)
ENOB_Q
ENOB (bits)
Dynamic parameters (dB)
80
-50
THD_Q
SFDR_Q
-60
-70
-80
THD_I
-90
SFDR_I
-100
35
40
45
Fs (MHz)
50
TSA1203
Distortion vs. Fin
Fs=40MHz; Icca=60mA
Linearity vs. Fin
Fs=40MHz; Icca=60mA
ENOB_Q
85
11
80
10
75
SNR_Q
SNR_I
70
9
ENOB_I
65
8
ENOB (bits)
Dynamic parameters
(dB)
12
60
SINAD_I
7
SINAD_Q
55
50
Dynamic parameters (dBc)
-40
90
6
0
20
40
60
-50
-60
SFDR_Q
THD_Q
-70
-80
THD_I
SFDR_I
-90
-100
80
0
20
40
Fin (MHz)
100
85
11
80
10
ENOB_Q
75
9
SNR_I
8
65
7
60
6
SINAD_Q
SNR_Q
55
5
50
-40
10
Dynamic parameters (dBc)
12
ENOB_I
ENOB (bits)
Dynamic parameters (dB)
90
SINAD_I
4
110
60
95
90
85
80
SFDR_Q
75
THD_Q
70
65
THD_I
60
50
-40
10
11.5
SINAD_Q
11
62
SINAD_I
SNR_I
10.5
58
10
56
ENOB_I
ENOB_Q
54
9.5
52
50
2.25
9
2.35
2.45
2.55
AVCC (V)
2.65
Dynamic Parameters (dBc)
12
68
60
110
Distortion vs. AVCC
Fs=40MSPS; Icca=60mA; Fin=10MHz
ENOB (bits)
Dynamic parameters (dB)
70
SNR_Q
60
Temperature (°C)
Linearity vs. AVCC
Fs=40MSPS; Icca=60mA; Fin=10MHz
64
SFDR_I
55
Temperature (°C)
66
80
Distortion vs.Temperature
Fs=40MSPS; Icca=60mA; Fin=2MHz
Linearity vs. Temperature
Fs=40MHz; Icca=60mA; Fin=2MHz
70
60
Fin (MHz)
-50
-55
-60
SFDR_I
-65
SFDR_Q
-70
-75
THD_I
-80
-85
-90
-95
-100
2.25
THD_Q
2.35
2.45
2.55
2.65
AVCC (V)
9/20
TSA1203
12
68
66
11.5
SNR_Q
SINAD_Q
64
11
62
60
SINAD_I
10.5
SNR_I
58
10
56
ENOB_I
ENOB (bits)
Dynamic parameters (dB)
70
ENOB_Q
54
9.5
52
50
2.25
Dynamic Parameters (dBc)
Distortion vs. DVCC
Fs=40MSPS; Icca=60mA; Fin=10MHz
Linearity vs. DVCC
Fs=40MSPS; Icca=60mA; Fin=10MHz
2.45
2.55
-55
-60
2.65
SFDR_I
-65
SFDR_Q
-70
-75
-80
THD_Q
THD_I
-85
-90
2.25
9
2.35
-50
2.35
2.45
DVCC (V)
11.5
SINAD_Q
64
11
62
60
SINAD_I
SNR_I
10.5
58
10
56
ENOB_I
ENOB (bits)
Dynamic parameters (dB)
68
ENOB_Q
54
9.5
52
50
2.25
Dynamic Parameters (dBc)
12
70
SNR_Q
2.45
2.55
-50
-55
-60
2.65
SFDR_I
-65
SFDR_Q
-70
-75
-80
THD_I
THD_Q
-85
-90
2.25
9
2.35
2.35
2.45
11.5
ENOB_I
ENOB_Q
67
10.5
66
SNR_I
64
SINAD_Q
9
SINAD_I
8.5
61
60
2.25
8
2.75
VCCBE (V)
10/20
10
9.5
63
62
11
3.25
ENOB (bits)
Dynamic parameters (dB)
69
Dynamic Parameters (dBc)
12
70
SNR_Q
2.65
Distortion vs. VCCBE
Fs=40MSPS; Icca=60mA; Fin=5MHz
Linearity vs. VCCBE
Fs=40MSPS; Icca=60mA; Fin=5MHz
65
2.55
VCCBI (V)
VCCBI (V)
68
2.65
Distortion vs. VCCBI
Fs=40MSPS; Icca=60mA; Fin=10MHz
Linearity vs. VCCBI
Fs=40MSPS; Icca=60mA; Fin=10MHz
66
2.55
DVCC (V)
-40
-50
-60
SFDR_Q
SFDR_I
-70
-80
-90
THD_I
THD_Q
-100
-110
2.25
2.75
VCCBE (V)
3.25
TSA1203
Linearity vs. Duty Cycle
Fs=40MHz; Icca=60mA; Fin=5MHz
Distortion vs. Duty Cycle
Fs=40MHz; Icca=60mA; Fin=5MHz
12
Dynamic parameters (dBc)
-40
ENOB_I
11
90
10
80
9
ENOB_Q
SNR_I SINAD_I
70
8
7
60
SNR_Q
50
ENOB (bits)
Dynamic parameters (dB)
100
6
SINAD_Q
5
40
4
48
49
50
51
-50
SFDR_Q
THD_Q
-60
-70
THD_I
-80
SFDR_I
-90
-100
52
48
Positive Duty Cycle (%)
49
50
51
52
Positive Duty Cycle (%)
Single-tone 8K FFT at 40Msps - Q Channel
Fin=5MHz; Icca=60mA, Vin@-1dBFS
Power spectrum (dB)
0
-20
-40
-60
-80
-100
-120
-140
2
4
6
8
10
12
14
16
18
20
Frequency (MHz)
Power spectrum (dB)
Dual-tone 8K FFT at 40Msps - Q Channel
Fin1=0.93MHz; Fin2=1.11MHz; Icca=70mA, Vin1@-7dBFS; Vin2@-7dBFS; IMD=-69dBc
0
-20
-40
-60
-80
-100
-120
2.5
5
7.5
10
12.5
15
17.5
20
Frequency (MHz)
11/20
TSA1203 APPLICATION NOTE
DETAILED INFORMATION
The TSA1203 is a dual-channel, 12-bit resolution
high speed analog to digital converter based on a
pipeline structure and the latest deep sub micron
CMOS process to achieve the best performances
in terms of linearity and power consumption.
Each channel achieves 12-bit resolution through
the pipeline structure which consists of 12 internal
conversion stages in which the analog signal is
fed and sequentially converted into digital data. A
latency time of 7 clock periods is necessary to obtain the digitized data on the output bus.
The input signals are simultaneously sampled on
both channels on the rising edge of the clock. The
output data are valid on the rising edge of the
clock for I channel and on the falling edge of the
clock for Q channel. The digital data out from the
different stages must be time delayed depending
on their order of conversion. Then a digital data
correction completes the processing and ensures
the validity of the ending codes on the output bus.
The structure has been specifically designed to
accept differential signals.
The TSA1203 is pin to pin compatible with the
dual 10 bits/20Msps, TSA1005-20, the dual 10bits
/40Msps, TSA1005-40 and the dual 12bits/
20Msps,TSA1204.
COMPLEMENTARY FUNCTIONS
Some functionalities have been added in order to
simplify as much as possible the application
board. These operational modes are described as
followed.
Output Enable (OEB)
When set to low level (VIL), all digital outputs
remain active and are in low impedance state.
When set to high level (VIH), all digital outputs
buffers are in high impedance state while the
converter goes on sampling. When OEB is set to a
low level again, the data are then present on the
output with a very short Ton delay.
Therefore, this allows the chip select of the device.
The timing diagram summarizes this functionality.
In order to remain in the normal operating mode,
this pin should be grounded through a low value of
resistor.
12/20
SELECT
The digital data out from each ADC cores are multiplexed together to share the same output bus.
This prevents from increasing the number of pins
and enables to keep the same package as single
channel ADC like TSA1201.
The selection of the channel information is done
through the "SELECT" pin. When set to high level
(VIH), the I channel data are present on the bus
D0-D11. When set to low level (VIL), the Q channel data are on the output bus D0-D11.
Connecting SELECT to CLK allows I and Q channels to be simultaneously present on D0-D11; I
channel on the rising edge of the clock and Q
channel on the falling edge of the clock. (see timing diagram page 2).
REFERENCES AND COMMON MODE
CONNECTION
VREFM must be always connected externally.
Internal reference and common mode
In the default configuration, the ADC operates with
its own reference and common mode voltages
generated by its internal bandgap. VREFM pins
are connected externally to the Analog Ground
while VREFP (respectively INCM) are set to their
internal voltage of 0.89V (respectively 0.46V). It is
recommended to decouple the VREFP and INCM
in order to minimize low and high frequency noise
(refer to Figure 1).
Figure 1 : Internal reference and common mode
setting
1.03V
VIN
TSA1203
VINB
330pF 10nF
4.7uF
VREFP
INCM
VREFM
0.57V
330pF 10nF
4.7uF
TSA1203
External reference and common mode
Each of the voltages VREFP and INCM can be
fixed externally to better fit to the application
needs
(Refer
to
Table
’OPERATING
CONDITIONS’ page 5 for min/max values).
The VREFP, VREFM voltages set the analog
dynamic at the input of the converter that has a full
scale amplitude of 2*(VREFP-VREFM). Using
internal references, the dynamic range is 1.8V.
The best linearity and distortion performances are
achieved with a dynamic range above 2Vpp and
by increasing the VREFM voltage instead of
lowering the VREFP one.
The INCM is the mid voltage of the analog input
signal.
It is possible to use an external reference voltage
device for specific applications requiring even
better
linearity,
accuracy
or
enhanced
temperature behavior.
Using the STMicroelectronics TS821 or
TS4041-1.2 Vref leads to optimum performances
when configured as shown on Figure 2.
Figure 2 : External reference setting
1kΩ
node. Our evaluation board is mounted with a 1:1
ADT1-1WT transformer from Minicircuits. You
might also use a higher impedance ratio (1:2 or
1:4) to reduce the driving requirement on the
analog signal source.
Each analog input can drive a 1.4Vpp amplitude
input signal, so the resultant differential amplitude
is 2.8Vpp.
Figure 3 : Differential input configuration with
transformer
Analog source
ADT1-1
1:1
VIN
50Ω
33pF
TSA1203
I or Q ch.
VINB
INCM
330pF
10nF
470nF
Figure 4 represents the biasing of a differential
input signal in AC-coupled differential input
configuration. Both inputs VIN and VINB are
centered around the common mode voltage, that
can be let internal or fixed externally.
330pF 10nF 4.7uF
VCCA VREFP
VIN
TSA1203
VINB
VREFM
TS821
TS4041
external
reference
Figure 4 : AC-coupled differential input
50Ω
VIN
10nF
100kΩ
33pF
common
mode
50Ω
INCM
100kΩ
TSA1203
VINB
10nF
DRIVING THE DIFFERENTIAL ANALOG
INPUTS
The TSA1203 has been designed to obtain
optimum performances when being differentially
driven. An RF transformer is a good way to
achieve such performances.
Figure 3 describes the schematics. The input
signal is fed to the primary of the transformer,
while the secondary drives both ADC inputs. The
common mode voltage of the ADC (INCM) is
connected to the center-tap of the secondary of
the transformer in order to bias the input signal
around this common voltage, internally set to
0.46V. It determines the DC component of the
analog signal. As being an high impedance input,
it acts as an I/O and can be externally driven to
adjust this DC component. The INCM is
decoupled to maintain a low noise level on this
Figure 5 shows a DC-coupled configuration with
forced VREFP and INCM to the 1V DC
analog input while VREFM is connected to
ground; we achieve a 2Vpp differential amplitude.
13/20
TSA1203
Figure 5 : DC-coupled 2Vpp differential analog
input
analog
AC+DC
VREFP
VIN
DC
TSA1203
VINB
analog
VREFM
INCM
DC
330pF
VREFP-VREFM = 1 V
10nF
4.7uF
Clock input
The TSA1203 performance is very dependant on
your clock input accuracy, in terms of aperture
jitter; the use of low jitter crystal controlled
oscillator is recommended.
The duty cycle must be between 45% and 55%.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise
modulation at the output.
It is recommended to keep the circuit clocked, to
avoid random states, before applying the supply
voltages.
Power consumption
So as to optimize both performance and power
consumption of the TSA1203 according the
sampling frequency, a resistor is placed between
IPOL and the analog Ground pins. Therefore, the
total dissipation is adjustable from 30Msps up to
40Msps.
The TSA1203 will combine highest performances
and lowest consumption at 40Msps when Rpol is
equal to 18kΩ. This value is nevertheless dependant on application and environment.
At lower sampling frequency range, this value of
resistor may be adjusted in order to decrease the
analog current without any degradation of
dynamic performances.
The table below sums up the relevant data.
Figure 6 : Total power consumption optimization
depending on Rpol value
Fs (Msps)
Rpol (kΩ)
Optimized
power (mW)
14/20
30
38
35
28
40
18
145
180
230
APPLICATION
Layout precautions
To use the ADC circuits in the best manner at high
frequencies, some precautions have to be taken
for power supplies:
- First of all, the implementation of 4 separate
proper supplies and ground planes (analog,
digital, internal and external buffer ones) on the
PCB is advised for high speed circuit applications
to provide low inductance and low resistance
common return.
The separation of the analog signal from the
digital part is mandatory to prevent noise from
coupling onto the input signal. The best
compromise is to connect from one part AGND,
DGND, GNDBI in a common point whereas
GNDBE must be isolated. Similarly, The power
supplies AVCC, DVCC and VCCBI must be
separated from the VCCBE one.
- Power supply bypass capacitors must be placed
as close as possible to the IC pins in order to
improve high frequency bypassing and reduce
harmonic distortion.
- Proper termination of all inputs and outputs must
be incorporated with output termination resistors;
then the amplifier load will be only resistive and
the stability of the amplifier will be improved. All
leads must be wide and as short as possible
especially for the analog input in order to decrease
parasitic capacitance and inductance.
- To keep the capacitive loading as low as
possible at digital outputs, short lead lengths of
routing are essential to minimize currents when
the output changes. To minimize this output
capacitance, buffers or latches close to the output
pins will relax this constraint.
- Choose component sizes as small as possible
(SMD).
Digital Interface application
Thanks to its wide external buffer power supply
range, the TSA1203 is perfectly suitable to plug in
to 2.5V low voltage DSPs or digital interfaces as
well as to 3.3V ones.
Medical Imaging application
Driven by the demand of the applications requiring
nowadays either portability or high degree of parallelism (or both), this product has been developed to satisfy medical imaging, and telecom infrastructures needs.
As a typical system diagram shows figure 7, a narrow input beam of acoustic energy is sent into a
living body via the transducer and the energy reflected back is analyzed.
TSA1203
Figure 7 : Medical imaging application
HV TX amps
TX
beam
former
Mux and
T/R
switches
ADC
RX
beam
former
TGC amplifier
Processing
and display
noise and very high linearity are mandatory factors.
These applications need high speed, low power
and high performance ADCs. 10-12 bit
resolution is necessary to lower the quantification
noise. As multiple channels are used, a dual converter is a must for room saving issues.
The input signal is in the range of 2 to 20MHz
(mainly 2 to 7MHz) and the application uses mostly a 4 over-sampling ratio for Spurious Free Dynamic Range (SFDR) optimization.
The next RX beam former and processing blocks
enable the analysis of the outputs channels versus the input beam.
EVAL1203/BA evaluation board
The transducer is a piezoelectric ceramic such as
zirconium titanate. The whole array can reach up
to 512 channels.
The TX beam former, amplified by the HV TX
amps, delivers up to 100V amplitude excitation
pulses with phase and amplitude shifts.
The mux and T/R switch is a two way input signal
transmitter/ output receiver.
To compensate for skin and tissues attenuation
effects, The Time Gain Compensation (TGC) amplifier is an exponential amplifier that enables the
amplification of low voltage signals to the ADC input range. Differential output structure with low
The EVAL1203/BA is a 4-layer board with high
decoupling and grounding level. The schematic of
the evaluation board is reported figure 11 and its
top overlay view figure 10. The characterization of
the board has been made with a fully ADC
devoted test bench as shown on Figure 8. The
analog input signal must be filtered to be very
pure.
The dataready signal is the acquisition clock of the
logic analyzer.
The ADC digital outputs are latched by the octal
buffers 74LCX573.
All characterization measurements have been
made with:
- SFSR=1dB for static parameters.
- SFSR=-1dB for dynamic parameters.
Figure 8 : Analog to Digital Converter characterization bench
HP8644
Sine Wave
Generator
Data
Vin
ADC
evaluation
board
Logic
Analyzer
PC
Clk
Clk
HP8133
Pulse
Generator
HP8644
Sine Wave
Generator
15/20
TSA1203
Operating conditions of the evaluation board:
Find below the connections to the board for the
power supplies and other pins:
board
notation
connection
internal
external
voltage (V)
voltage (V)
AV
AVCC
2.5
AG
AGND
0
RPI
REFPI
RMI
REFMI
CMI
INCMI
0.46
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