TSA1204_06

TSA1204 Dual channel 12-bit 20Msps 120mW A/D converter Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 0.5 Msps to 20 Msps sampling frequency Adaptive power consumption: 120 mW @ 20 Msps, 95 mW@10 Msps Single supply voltage: 2.5 V Independent supply for CMOS output stage with 2.5 V/3.3 V capability ENOB=11.2 @ Nyquist SFDR= -81.5 dBc @ Nyquist 1GHz analog bandwidth track-and-hold Common clocking between channels Dual simultaneous sample and hold inputs Multiplexed outputs Built-in reference voltage with external bias capability. AGND 1 INI 2 AGND 3 INIB 4 AGND 5 IPOL 6 AVCCB 7 AGND 8 INQ 9 AGND 10 INBQ 11 AGND 12 GNDBE D0(LSB) VCCBE REFPI VCCBI REFMI CLKD VCCBI 7x7mm TQFP48 INCMI AVCC AVCC OEB D1 index corner 48 47 46 45 44 43 42 41 40 39 38 37 36 D2 35 D3 34 D4 33 D5 32 D6 31 D7 TSA1204 30 D8 29 D9 28 D10 27 D11(MSB) 26 VCCBE 25 GNDBE Description The TSA1204 is a new generation of high speed, dual-channel analog-to-digital converters implemented in a mainstream 0.25 µm CMOS technology yielding high performance and very low power consumption. The TSA1204 is specifically designed for applications requiring very low noise floor, high SFDR and good insulation between channels. It is based on a pipeline structure and digital error correction to provide excellent static linearity and over 11.2 effective bits at FS=20 Msps, and Fin=10 MHz. For each channel, an integrated voltage reference simplifies the design and minimizes external components. It is nevertheless possible to use the circuit with external references. The ADC outputs are multiplexed in a common bus with a small number of pins. A tri-state capability is available for the outputs, allowing chip selection. 13 REFPQ 14 15 16 REFMQ INCMQ AGND 17 18 19 20 21 22 AVCC DVCC DGND CLK SELECT DGND 23 24 DVCC GNDBI The inputs of the ADC must be differentially driven. The TSA1204 is available in extended (-40° C to +85° C) temperature range, in a small 48-pin TQFP package. Applications ■ ■ ■ ■ ■ Medical imaging and ultrasound 3G base station I/Q signal processing applications High speed data acquisition system Portable instrumentation December 2006 Rev 4 1/31 www.st.com 31 Contents TSA1204 Contents 1 2 3 4 5 6 7 8 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1 Additional functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.1 8.1.2 Output enable mode (OEB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Select mode (SELECT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.2 References and common mode connection . . . . . . . . . . . . . . . . . . . . . . . 16 8.2.1 8.2.2 Internal reference and common mode . . . . . . . . . . . . . . . . . . . . . . . . . . 16 External reference and common mode . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.3 8.4 8.5 8.6 8.7 Driving the differential analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 EVAL1204/BA evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.7.1 8.7.2 8.7.3 8.7.4 Evaluation board operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Consumption adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Single and differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 Practical application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1 9.2 Digital interface applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Medical imaging application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/31 TSA1204 Contents 10 Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11 12 13 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3/31 Schematic diagram TSA1204 1 Schematic diagram Figure 1. TSA1204 block diagram +2.5V/3.3V CLK SELECT OEB VCCBE Timing VINI VINBI VINCMI VREFPI VREFMI IPOL VREFPQ VREFMQ VINCMQ VINQ VINBQ Polar. REF Q AD 12 I channel 12 common mode REF I M U X 12 12 Buffers D0 TO D11 common mode AD 12 Q channel 12 GND GNDBE Figure 2. Timing diagram Simultaneous sampling on I/Q channels N+3 N+4 N+5 N+6 N+12 N+13 I N-1 N Q N+1 N+2 N+7 N+8 N+9 N+10 N+11 CLK Tpd I + Tod Tod SELECT CLOCK AND SELECT CONNECTED TOGETHER OEB sample N-8 I channel sample N-6 Q channel sample N Q channel sample N+1 Q channel sample N+2 Q channel DATA OUTPUT sample N-9 I channel sample N-7 Q channel sample N+1 sample N+2 I channel I channel sample N+3 I channel 4/31 TSA1204 Pin descriptions 2 Pin descriptions Table 1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin descriptions (TQFP48 package) Description Analog ground I channel analog input Analog ground I channel inverted analog input Analog ground Analog bias current input Analog power supply Analog ground Q channel analog input Analog ground Q channel inverted analog input Analog ground Q channel top reference voltage Q channel bottom reference voltage Q channel input common mode Analog ground Analog power supply Digital power supply Digital ground Clock input Channel selection Digital ground Digital power supply Digital buffer ground 0V 2.5 V 2.5 V 0V 2.5 V CMOS input 2.5 V CMOS input 0V 2.5 V 0V 0V 0V 0V 2.5 V 0V 0V 0V Name AGND INI AGND INBI AGND IPOL AVCC AGND INQ AGND INBQ AGND REFPQ REFMQ INCMQ AGND AVCC DVCC DGND CLK SELECT DGND DVCC GNDBI Observation 0V Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name GNDBE VCCBE D11(MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0(LSB) VCCBE GNDBE VCCBI CLKD OEB AVCC AVCC INCMI REFMI REFPI Description Digital buffer ground Digital Buffer power supply Most Significant Bit output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output Least Significant Bit output Digital Buffer power supply Digital buffer ground Digital Buffer power supply Data clock input Output Enable input Analog power supply Analog power supply I channel input common mode I channel bottom reference voltage I channel top reference voltage Observation 0V 2.5 V/3.3 V CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) CMOS output (2.5 V/3.3 V) 2.5 V/3.3 V - See Application Note 0V 2.5 V Idle at high level 2.5 V or 3.3 V 2.5 V/3.3 V CMOS input 2.5 V 2.5 V 0V 5/31 Dynamic characteristics TSA1204 3 Dynamic characteristics Dynamic characteristics are measured at AVCC = DVCC = VCCB = 2.5 V, FS= 20 Msps, Fin=10.5 MHz, Vin@ -1 dBFS, VREFP=1.0 V, VREFM=0 V and Tamb = 25° C (unless otherwise specified). Table 2. Symbol SFDR SNR THD SINAD ENOB Dynamic characteristics Parameter Spurious free dynamic range Signal to noise ratio Total harmonics distortion Signal to noise and distortion ratio Effective number of bits 64.8 10.6 66.9 Test conditions Min Typ -81.5 68.5 -80 68 11.2 -70 Max -71.0 Unit dBc dB dBc dB bits 4 Timing characteristics Timing characteristics are measured at AVCC = DVCC = VCCB = 2.5 V, FS= 20 Msps, Fin=10.5 MHz, Vin@ -1 dBFS, VREFP=1.0 V, VREFM=0 V and Tamb = 25° C (unless otherwise specified). Table 3. Symbol FS DC TC1 TC2 Tod Tpd I Tpd Q Ton Toff Timing characteristics Parameter Sampling frequency Clock duty cycle Clock pulse width (high) Clock pulse width (low) Data output delay (clock edge to data valid) Data pipeline delay for channel I Data pipeline delay for channel Q Falling edge of OEB to digital output valid data Rising edge of OEB to digital output tri-state 10 pF load capacitance Test conditions Min 0.5 45 22.5 22.5 50 25 25 9 7 7.5 1 1 Typ Max 20 55 Unit MHz % ns ns ns cycle s cycle s ns ns 6/31 TSA1204 Absolute maximum ratings 5 Absolute maximum ratings Table 4. Symbol AVCC DVCC VCCBE VCCBI IDout Tstg ESD Latch-up Absolute maximum ratings Parameter Analog supply voltage (1) Digital supply voltage (1) (1) Values 0 to 3.3 0 to 3.3 0 to 3.6 0 to 3.3 -100 to 100 +150 2 1.5 A Unit V V V V mA °C kV Digital buffer supply voltage Digital buffer supply voltage (1) Digital output current Storage temperature HBM: human body CDM: charged device model(3) Class(4) model(2) 1. All voltage values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3 V or VCC. 2. Electrostatic discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5 kΩ. 3. Discharge to ground of a device that has been previously charged. 4. ST Microelectronics corporate procedure number 0018695. 6 Operating conditions Table 5. Symbol AVCC DVCC VCCBE VCCBI VREFP I VREFP Q VREFM I VREFM Q VINCM I VINCM Q Operating conditions Parameter Analog supply voltage Digital supply voltage External digital buffer supply voltage Internal digital buffer supply voltage Forced top voltage reference (1) Forced bottom reference voltage (1) Forced input common mode voltage Min 2.25 2.25 1.8 2.25 0.96 0 0.2 Typ 2.5 2.5 2.5 2.5 Max 2.7 2.7 3.5 2.7 1.4 0.4 1 Unit V V V V V V V 1. Condition VREFP-VREFM > 0.3 V 7/31 Electrical characteristics TSA1204 7 Electrical characteristics Electrical characteristics are measured at AVCC = DVCC = VCCB = 2.5 V, FS= 20 Msps, Fin=2 MHz, Vin@ -1 dBFS, VREFP=1.0 V, VREFM=0 V, and Tamb = 25° C (unless otherwise specified). Table 6. Symbol VIN-VINB Cin Req BW ERB Analog inputs Parameter Full scale reference voltage Input capacitance Equivalent input resistor Analog input bandwidth Effective resolution bandwidth Vin@full scale, FS=20 Msps Test conditions Differential inputs mandatory Min 1.1 Typ 2.0 7.0 3 1000 70 Max 2.8 Unit Vpp pF KΩ MHz MHz Table 7. Symbol Digital inputs and outputs Parameter Test conditions Min Typ Max Unit Clock and select inputs VIL VIH OEB input VIL VIH Logic "0" voltage Logic "1" voltage 0.75 x VCCBE 0 VCCBE 0.25 x VCCBE V V Logic "0" voltage Logic "1" voltage 2.0 0 2.5 0.8 V V Digital outputs VOL VOH IOZ CL Logic "0" voltage Logic "1" voltage High impedance leakage current Output load capacitance IOL=10 µA IOH=10 µA OEB set to VIH 0 0.9 x VCCBE VCCBE -1.7 1.7 15 0.1 x VCCBE V V µA pF Table 8. Symbol VREFPI VREFPQ VINCMI VINCMQ Reference voltage Parameter Top internal reference voltage Input common mode voltage Test conditions Min 0.807 0.40 Typ 0.89 0.46 Max 0.963 0.52 Unit V V 8/31 TSA1204 Table 9. Symbol ICCA ICCD ICCBE ICCBI Pd Rthja Electrical characteristics Power consumption Parameter Analog supply current Digital supply current Digital buffer supply current (10 pF load) Digital buffer supply current Power consumption in normal operation mode Thermal resistance (TQFP48) Min Typ 40 2 6.2 73 120 80 Max 49.5 3 9 221 155 Unit mA mA mA µA mW °C/W Table 10. Symbol OE GE DNL INL Accuracy Parameter Offset error Gain error Differential non linearity Integral non linearity Monotonicity and no missing codes Min -1.8 -0.1 -0.93 -1.8 Typ -0.5 0 ±0.4 ±0.8 Max 1.8 0.1 +0.93 +1.8 Unit LSB % LSB LSB Guaranteed Table 11. Symbol GM OM PHM XTLK Matching between channels Parameter Gain match Offset match Phase match Crosstalk rejection Min Typ 0.033 0.4 1 87 Max 0.1 2.5 Unit % LSB dg dB 9/31 Electrical characteristics Figure 3. Static parameter: integral non linearity(a) TSA1204 FS=20 MSPS; ICCA=40 mA; Fin=2 MH 0.8 0.6 INL (LSBs) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0 500 1000 1500 2000 2500 3000 3500 4000 Output Code Figure 4. Static parameter: differential non linearity(a) FS=20 MSPS; ICCA=40 mA; Fin=2 MHz 0.4 0.3 DNL (LSBs) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 500 1000 1500 2000 2500 3000 3500 4000 Output Code a. For parameter definitions, see Section 10: Definitions of specified parameters on page 25. 10/31 TSA1204 Electrical characteristics Figure 5. Linearity vs. FS Fin=5MHz; Rpol adjustment 12 Figure 6. Distortion vs. FS Fin=5MHz; Rpol adjustment 100 Dynamic parameters (dBc) Dynamic parameters (dB) ENOB Q -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 10 15 20 25 SFDR_Q THD_Q SFDR_I THD_I 90 ENOB I 80 SNR Q 70 SINAD Q 11 10 9 8 ENOB (bits) 60 SNR_I 50 40 10 15 20 25 SINAD_I 7 6 5 Fs (MHz) Fs (MHz) Figure 7. Linearity vs. Fin FS=20Msps; ICCA=40mA 12 11 SINAD_Q Figure 8. Distortion vs. Fin FS=20Msps; ICCA=40mA Dynamic parameters (dB) ENOB_Q ENOB_I Dynamic parameters (dBc) 100 90 80 SNR_Q -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 20 30 40 50 THD_I SFDR_Q THD_Q SFDR_I 70 60 SNR_I 9 8 SINAD_I 50 40 30 0 7 6 5 10 20 30 40 50 Fin (MHz) ENOB (bits) 10 Fin (MHz) Figure 9. Linearity vs. Temperature Figure 10. Distortion vs. Temperature FS=20Msps; ICCA=40mA; Fin=2MHz FS=20Msps; ICCA=40mA; Fin=2MHz 12 11.5 11 100 Dynamic parameters (dBc) Dynamic parameters (dB) ENOB_I 120 110 100 90 80 70 60 50 40 -40 10 60 SFDR_I THD_I SFDR_Q THD_Q 90 80 70 60 50 40 -40 10 60 ENOB_Q SNR_I SINAD_I 10 9.5 9 SNR_Q SINAD_Q 8.5 8 7.5 7 ENOB (bits) 10.5 Temperature (°C) Temperature (°C) 11/31 Electrical characteristics TSA1204 Figure 11. Linearity vs. AVCC Figure 12. Distortion vs. AVCC FS=20Msps; ICCA=40mA; Fin=5MHz FS=20Msps; ICCA=40mA; Fin=5MHz 100 12 ENOB_Q Dynamic parameters (dB) Dynamic Parameters (dBc) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 2.25 2.35 2.45 2.55 2.65 THD_Q SFDR_Q THD_I SFDR_I 95 90 85 80 75 70 65 60 55 50 2.25 11 10 SNR_Q SINAD_Q 9 8 SINAD_I SNR_I 7 6 2.35 2.45 2.55 2.65 ENOB (bits) ENOB_I AVCC (V) AVCC (V) Figure 13. Linearity vs. DVCC Figure 14. Distortion vs. DVCC FS=20Msps; ICCA=40mA; Fin=5MHz FS=20Msps; ICCA=40mA; Fin=5MHz 100 12 ENOB_Q Dynamic parameters (dB) Dynamic Parameters (dBc) -40 -50 -60 THD_I SFDR_I 90 ENOB_I 11 10 SNR_Q SNR_I 80 70 60 50 40 2.25 SINAD_I SINAD_Q ENOB (bits) -70 -80 -90 -100 -110 -120 2.25 THD_Q SFDR_Q 9 8 7 6 2.35 2.45 2.55 2.65 2.35 2.45 2.55 2.65 DVCC (V) DVCC (V) Figure 15. Linearity vs. VCCBI Figure 16. Distortion vs. VCCBI FS=20Msps; ICCA=40mA; Fin=5MHz FS=20Msps; ICCA=40mA; Fin=5MHz 90 12 ENOB_I Dynamic parameters (dB) Dynamic Parameters (dBc) -40 -50 -60 -70 -80 -90 -100 -110 -120 2.25 THD_Q SFDR_Q THD_I SFDR_I 85 80 11.5 11 ENOB_Q 75 70 65 60 55 50 2.25 SINAD_I SNR_I SNR_Q 10.5 10 9.5 SINAD_Q 9 8.5 8 ENOB (bits) 2.35 2.45 2.55 2.65 2.35 2.45 2.55 2.65 VCCBI (V) VCCBI (V) 12/31 TSA1204 Electrical characteristics Figure 17. Linearity vs. VCCBE Figure 18. Distortion vs. VCCBE FS=20Msps; ICCA=40mA; Fin=5MHz FS=20Msps; ICCA=40mA; Fin=5MHz 90 12 ENOB_I Dynamic parameters (dB) Dynamic Parameters (dBc) -40 -50 -60 SFDR_Q THD_I 85 80 75 SNR_I ENOB_Q SINAD_I 11.5 11 10.5 10 9.5 9 8.5 8 7.5 7 ENOB (bits) -70 -80 -90 -100 -110 -120 2.25 THD_Q SFDR_I 70 65 60 55 50 2.25 SNR_Q SINAD_Q 2.75 3.25 2.75 3.25 VCCBE (V) VCCBE (V) Figure 19. Linearity vs. duty cycle Figure 20. Distortion vs. duty cycle FS=20Msps; ICCA=40mA; Fin=5MHz FS=20Msps; ICCA=40mA; Fin=5MHz 100 12 ENOB_I -40 11.5 11 Dynamic parameters (dBc) Dynamic parameters (dB) 90 80 70 60 SNR_Q ENOB_Q SNR_I SINAD_I -50 -60 SFDR_Q ENOB (bits) 10.5 10 9.5 9 SINAD_Q -70 -80 -90 -100 -110 -120 45 47 THD_Q 8.5 8 7.5 SFDR_I THD_I 50 40 45 47 49 51 53 55 7 49 51 53 55 Positive Duty Cycle (%) Positive Duty Cycle (%) 13/31 Electrical characteristics Figure 21. Single-tone 8K FFT at 20Msps - Channel I Fin=5MHz; ICCA=40mA, Vin@-1dBFS 0 TSA1204 Power spectrum (dB) -20 -40 -60 -80 -100 -120 -140 1 2 3 4 5 6 7 8 9 10 Frequency (MHz) Figure 22. Dual-tone 8K FFT at 20Msps - Channel I Fin1=9.7MHz; Fin2=10.7MHz; ICCA=40mA, Vin1@-7dBFS; Vin2@-7dBFS; IMD=-76dBc 0 Power spectrum (dB) -20 -40 -60 -80 -100 -120 -140 1 2 3 4 5 6 7 8 9 10 Frequency (MHz) 14/31 TSA1204 Application information 8 Application information The TSA1204 is a dual-channel, 12-bit resolution analog-to-digital converter based on a pipeline structure and the latest deep submicron CMOS process to achieve the best performance in terms of linearity and power consumption. Each channel achieves 12-bit resolution through the pipeline structure which consists of 12 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. A latency time of 7 clock periods is necessary to obtain the digitized data on the output bus. The input signals are simultaneously sampled, for both channels, on the rising edge of the clock. The output data is delivered on the rising edge of the clock for channel I and on the falling edge of the clock for channel Q, as shown in Figure 2: Timing diagram on page 4. The digital data produced at the different stages must be time delayed accordidng to the order of conversion. Fianlly, a digital data correction completes the processing and ensures the validity of the ending codes on the output bus. The structure is specifically designed to accept differential signals only. 8.1 Additional functions To simplify the application board as much as possible, the following operating modes are provided: ● ● Output enable mode (OEB) Select mode (SELECT) 8.1.1 Output enable mode (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital output buffers are in high impedance state while the converter goes on sampling. When OEB is set to a low level again, the data arrives on the output with a very short Ton delay. This mechanism allows the chip select of the device. Figure 2: Timing diagram on page 4 summarizes this functionality. If you do not want to use OEB mode, the OEB pin should be grounded through a low value resistor. 8.1.2 Select mode (SELECT) The digital data output from each of the ADC cores is multiplexed to share the same output bus. This prevents an increase in the number of pins and allows to use the same package as for a single-channel ADC like the TSA1201. The information channel is selected with the "SELECT" pin. When set to high level (VIH), channel I data is present on the D0-D11 output bus. When set to low level (VIL), channel Q data is delivered on D0-D11. By connecting SELECT to CLK, channel I and channel Q are simultaneously present on D0D11, channel I on the rising edge of the clock and channel Q on the falling edge of the clock. (Refer to Figure 2: Timing diagram on page 4). 15/31 Application information TSA1204 8.2 References and common mode connection VREFM must always be connected externally. 8.2.1 Internal reference and common mode In the default configuration, the ADC operates with its own reference and common mode voltages generated by its internal bandgap. It is recommended to decouple the VREFP and INCM pins in order to minimize low and high frequency noise (see Figure 23). Figure 23. Internal reference and common mode setting 1.03V VIN VREFP 0.57V 330pF 10nF 4.7μF 330pF 10nF 4.7μF TSA1204 INCM VINB VREFM 8.2.2 External reference and common mode Each of the voltages VREFM, VREFP and INCM can be fixed externally to better fit to the application needs (refer to Table 5: Operating conditions on page 7 for min/max values). It is possible to use an external reference voltage device for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. The VREFP and VREFM voltages set the analog dynamic range at the input of the converter that has a full scale amplitude of 2*(VREFP-VREFM). The INCM voltage is half the value of VREFP-VREFM. The best linearity and distortion performance is achieved with a dynamic range above 2 Vpp and by increasing the VREFM voltage instead of lowering the VREFP one. To obtain the highest performance from the TSA1204 device, we recommend implementing the configuration shown in Figure 24 with the STMicroelectronics TS821or TS4041-1.2 Vref. Figure 24. External reference setting 1kΩ 330pF 10nF 4.7μF VCCA VREFP VIN TSA1204 VINB VREFM TS821 TS4041 external reference 16/31 TSA1204 Application information 8.3 Driving the differential analog inputs The TSA1204 is designed to deliver optimum performance when driven on differential inputs. An RF transformer is an efficient way of achieving this high performance. Figure 25 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.46 V. It determines the DC component of the analog signal. Being a high impedance input, it acts as an I/O and can be externally driven to adjust this DC component. The INCM is decoupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1WT transformer from Minicircuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. Each analog input can drive a 1.4 Vpp amplitude input signal, so the resulting differential amplitude is 2.8 Vpp. Figure 25. Differential input configuration with transformer Analog source 50Ω ADT1-1 1:1 33pF TSA1204 channels VINB I or Q INCM VIN 330pF 10nF 470nF Figure 26. AC-coupled differential input 50Ω common mode 10nF 100kΩ 33pF 100kΩ 10nF VIN INCM TSA1204 VINB 50Ω Figure 26 represents the biasing of a differential input signal in AC-coupled differential input configuration. Both inputs VIN and VINB are centered around the common mode voltage, that can be let internal or fixed externally. 17/31 Application information Figure 27. DC-coupled 2 Vpp differential analog input analog DC analog DC 330pF 10nF VREFP-VREFM = 1 V 4.7μF TSA1204 AC+DC VIN VREFP TSA1204 VINB VREFM INCM Figure 27 shows a DC-coupled configuration with forced VREFP and INCM to the 1 V DC analog input while VREFM is connected to ground; the differential amplitude obtained is 2 Vpp. 8.4 Clock input The quality of your TSA1204 converter is very dependent on your clock input accuracy, in terms of aperture jitter; the use of a low jitter crystal controlled oscillator is recommended. Further points to consider in your implementation are: ● ● ● The duty cycle must be between 45% and 55%. The clock power supplies must be independent from the ADC output supplies to avoid digital noise modulation on the output. When powered-on, the circuit needs several clock periods to reach its normal operating conditions. Therefore, it is recommended to keep the circuit clocked to avoid random states before applying the supply voltages. 8.5 Power consumption optimization The internal architecture of the TSA1204 makes it possible to optimize power consumption according to the sampling frequency of the application. For this purpose, an external resistor is placed between IPOL and the analog ground pins. Therefore, the total dissipation can be optimized over the full sampling range (0.5 Msps up to 20 Msps). The TSA1204 combines the highest performance and the lowest consumption at 20 Msps when Rpol is equal to 54 kΩ. This value is nevertheless dependent on the application and the environment. In the lower sampling frequency range, this value of resistor may be adjusted in order to decrease the analog current without any degradation of the dynamic performance. Table 12 gives some values to illustrate this. 18/31 TSA1204 Table 12. FS (Msps) Rpol (kΩ) Optimized power (mW) Application information Total power consumption optimization depending on Rpol value 10 120 95 20 54 120 8.6 Layout precautions To use the ADC circuits most efficiently at high frequencies, some precautions have to be taken for power supplies: ● First of all, the implementation of 4 proper separate supplies and ground planes (analog, digital, internal and external buffer ones) on the PCB is recommended for high speed circuit applications to provide low inductance and low resistance common return. The separation of the analog signal from the digital output part is mandatory to prevent noise from coupling onto the input signal. The best compromise is to connect AGND, DGND, GNDBI in a common point whereas GNDBE must be isolated. Similarly, the AVCC, DVCC and VCCBI power supplies must be separate from the VCCBE power supply. ● ● Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. All inputs and outputs must be properly terminated with output termination resistors; then the amplifier load is resistive only and the stability of the amplifier is improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. To keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. To minimize this output capacitance, use buffers or latches close to the output pins. Choose component sizes as small as possible (SMD). ● ● 8.7 EVAL1204/BA evaluation board The EVAL1204/BA is a 4-layer board with high decoupling and grounding level. The schematic of the evaluation board is shown in Figure 30 and its top overlay view in Figure 29. The board has been characterized with a fully devoted ADC test bench as shown in Figure 28. Figure 28. Analog-to-digital converter characterization bench HP8644 Sine Wave Generator Vin ADC evaluation board Clk HP8133 Pulse Generator Data Logic Analyzer Clk PC HP8644 Sine Wave Generator 19/31 Application information Note: TSA1204 The analog signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. The ADC digital outputs are latched by the octal buffers 74LCX573. All characterization measurements are made with SFSR=1 dB for static parameters. Figure 29. Evaluation board printed circuit Table 13. Name Part Type RSQ6 0 RSQ7 0 RSQ8 0 RSI6 0 RSI7 0 RSI8 0 47 R3 47 R5 RQ19 47 47 RI1 RQ1 47 RI19 47 RSI9 0NC RSQ5 0NC RSQ9 0NC RSI5 0NC 0NC R24 0NC R23 0NC R21 0NC R22 1K R2 47K R12 47K R11 Raj1 200K C23 C41 C29 Printed circuit board - list of components Footprint 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 Name Part Type C26 330pF C20 330pF C33 330pF C25 330pF CI1 33pF CQ1 33pF C34 47µF C42 47µF C35 47µF C44 47µF C36 47µF C32 47µF C37 470nF CQ10 470nF C28 470nF CI10 470nF CQ32 470nF CQ13 470nF CI32 470nF C13 470nF C53 470nF C16 470nF C3 470nF C22 470nF CI13 470nF C38 470nF CD1 470nF C19 470nF Footprint Name Part Footprint Type 603 CQ6 NC 805 603 CI6 NC 805 603 U2 74LCX573 TSSOP20 603 U3 74LCX573 TSSOP20 603 U1 STG719 SOT23-6 603 JA ANALOGIC connector RB.1 J17 BUFPOW connector RB.1 J25 CKDATA SMA RB.1 J4 CLK SMA RB.1 J27 CON2 SIP2 RB.1 J26 CON2 SIP2 RB.1 JD DIGITAL connector 805 JI1 InI SMA 805 JI1B InIB SMA 805 JQ1 InQ SMA 805 JQ1B InQB SMA 805 SW1 SWITCH connector 805 S5 SW-SPST connector 805 S4 SW-SPST connector 805 TI2 T2-AT1-1WT ADT 805 TQ2 T2-AT1-1WT ADT 805 JI2 VREFI connector 805 JQ2 VREFQ connector 805 J6 32Pin IDC-32 805 connector 805 805 NC: non soldered 805 Footprint Name Part Type 805 CD2 10nF 805 C40 10nF 805 C39 10nF 805 CQ12 10nF 805 CQ9 10nF 805 C52 10nF 603 C18 10nF 603 C21 10nF 603 C4 10nF 603 C15 10nF 603 C27 10nF 603 C11 10nF 805 CI9 10nF 805 CI12 10nF 805 CI31 10nF 805 CQ31 10nF 805 CQ30 330pF 805 CI11 330pF 805 C51 330pF 805 C2 330pF 603 C17 330pF 603 CD3 330pF 603 C10 330pF CQ8 330pF VR5 trimmer CQ11 330pF 10µF 1210 CI8 330pF 10µF 1210 C14 330pF 10µF 1210 CI30 330pF 20/31 TSA1204 REFP REFM INCM JI2 VREFI VCCB1 VCCB2 VCCB3 VCCB1 VCCB2 Switch S4 Open Short OEB Mode Normal mode High Impedance output mode R12 S4 SW-SPST R11 R23 47K STG719 VCCB1 C44 47µF + GndB1 VccB1 GndB2 VccB2 GndB3 VccB3 NM: non soudé J17 BUFPOW analog input with transformer (default) single input differential input RS5 RS6 RS7 RS8 RS9 CCC C C C C 47K S5 SW-SPST U1 CON2 VCCB2 Switch S5 Open Short Normal mode Test mode 2 1 R5 50 J26 J25 CKDATA R21 0NM 0NM R22 R24 0NM 0NM IN S2 Vcc D GNDS1 C28 VCCB2 C16 470nF AVCC C53 470nF C34 47µF VCCB3 + C43 10µF J6 470nF C27 C37 C39 C51 330pF 10nF 330pF 470nF DO D1 D2 D3 D4 D5 D6 D7 74LCX573 D8 D9 D10 D11 CLK 74LCX573 C38 C18 10nF C40 CD3 330pF C19 470nF C33 C35 + RSI5 C15 10nF C14 330pF C52 10nF RSI6 1 10nF C25 330pF C26 CI13 470nF 10nF 470nF 10nF 48 47 46 45 44 43 42 41 40 39 38 37 330pF 330pF 470nF 10nF 330pF CI12 CI11 0 NC TI2 6 RSI7 0 2 CI10 CI9 CI8 CI32 CI31 CI30 0 RI1 50 D0 GND D1 GND D2 GND D3 GND D4 GND D5 GND D6 GND D7 GND D8 GND D9 GND D10 GND D11 GND CLK GND 3 4 RSI8 T2-AT1-1WT0 JI1B InIB J9 CI1 33pF R2 C41 Raj1 47K ADC DUAL12B REFPQ REFMQ INCMQ AGND AVCC DVCC DGND CLK SELECT DGND DVCC GNDBI 470nF 10nF 330pF C3 C4 C2 1K 8-14bits ADC NM REFPI REFMI INCMI AVCC AVCC OEB CLKD VCCBI VCCBI GNDBE VCCBE D0(LSB) D1 CI6 OEB VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 U2 D5 Q5 D6 Q6 D7 Q7 GND LE RSI9 RI19 50 0 NC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AVCC JA VCC GND + C42 47µF10µF Figure 30. TSA1204 evaluation board schematic ANALOGIC 1 2 3 4 5 6 7 8 9 10 11 12 AGND INI AGND INBI AGND IPOL AVCC AGND INQ AGND INBQ AGND D2 D3 D4 D5 D6 D7 D8 D9 D10 D11(MSB) VCCBE GNDBE 36 35 34 33 32 31 30 29 28 27 26 25 RSQ5 CQ1 13 14 15 16 17 18 19 20 21 22 23 24 C29 10µF + 1 Q 33pF DVcc C17 330pF CQ13 CQ12 CQ11 CD1 470nF CD2 10nF CQ10 CQ9 470nF 10nF 470nF 10nF 330pF 470nF 10nF 330pF 330pF CQ8 CQ32 CQ31 CQ30 NM RQ1 50 RSQ61 0 0 NC RSQ7 TQ2 6 0 2 CQ6 1 2 3 4 5 6 7 8 9 10 OEB VCC D0 Q0 D1 Q1 U3 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND LE 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3 4 RSQ8 T2-AT1-1WT 0 470nF 10nF 330pF JQ1B InQB RSQ9 RQ19 50 C20 330pF SW1 C10 330pF C21 10nF DVCC C11 10nF C22 470nF C23 10µF REFP REFM INCM JQ2 VREFQ C31 10µF C36 47µF C32 47µF + + 0 NC 47µF VCCB2 J27 2 1 CON2 C5 100nF J4 50 CLK R3 DVCC AVCC C13 470nF VCC GND DIGITAL JD Application information 21/31 Application information TSA1204 8.7.1 Evaluation board operating conditions Table 14 below shows the connections to the board for the power supplies and other pins. Table 14. Board connections for power supplies and other pins Connection AVCC AGND REFPI REFMI INCMI REFPQ REFMQ INCMQ DVCC DGND GNDBI VCCBI GNDBE VCCBE GNDB3 VCCB3 0.46 0.46 0.89 0.89 Internal voltage (V) External voltage (V) 2.5 0