TSA1401IF

TSA1401 14-BIT, 20MSPS, 85mW A/D CONVERTER FEATURES ■ OPTIMWATTTM features 1 l Ultra low power consumption: 85mW at 20Msps (using external references). APPLICATIONS ■ ■ ■ ■ ■ ■ High-end infra-red imaging X-Ray medical imaging High-end CCD cameras Scanners and digital copiers Test instrumentation Wireless communication ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs ■ ■ ■ 1) OPTIMWATT(TM) is a ST deposited trademark for products features allowing optimization of power efficiency at chip/application level. ORDER CODES Temperature Range Part Number Package Conditioning TSA1401IF -40°C to +85°C TQFP48 Tray SA1401 TSA1401IFT -40°C to +85°C TQFP48 Tape & Reel SA1401 EVAL1401/AB Evaluation board PIN CONNECTIONS (top view) O DR VCCBE GNDBE VCCBI NC SRC OEB DFSB AVCC AVCC 48 47 46 45 44 43 42 41 40 39 38 37 36 D1 IPOL 1 VREFP 2 35 D2 VREFM 3 34 D3 AGND 4 33 D4 VIN 5 32 D5 TSA1401 AGND 6 31 D6 VINB 7 30 D7 AGND 8 29 D8 INCM 9 28 D9 AGND 10 27 D10 AVCC 11 26 D11 25 D12 AVCC 12 OR VCCBE GNDBE GNDBI DGND NC DGND CLK DGND DVCC 13 14 15 16 17 18 19 20 21 22 23 24 DVCC Typically designed for multi-channel applications and high-end imaging equipment, where low consumption is a must, the TSA1401 only dissipates 85mW at 20Msps when using external references, 110mW using internal references. Its power consumption adapts relative to sampling frequency. Differential signals are applied on the inputs for optimum performance. The TSA1401 reaches an SFDR of -90.5dBc and an SNR of 73.1dBc at Fin=10MHz when increasing the input dynamic range to 2.5V by using the voltage reference, TS431 (1.24V). index corner AGND DESCRIPTION The TSA1401 is a 14-bit, 20MHz sampling frequency Analog to Digital Converter using deep submicron CMOS technology combining high performances with very low power consumption.The TSA1401 is based on a pipeline structure with digital error correction to provide excellent static linearity and dynamic performances. Marking D0 (LSB) ■ Single supply voltage: 2.5V Digital I/O supply voltage: 2.5V/3.3V compatible -90.5dBc SFDR and 73.1dBc SNR at Fin=10MHz when using external references (VINpp=2.5V) Differential analog input-driving Built-in reference voltage with external bias capabilities Digital output high impedance mode D13(MSB) l Adjustable consumption versus speed. ■ ■ PACKAGE 7 x 7 mm TQFP48 A tri-state capability is available on the output buffers, enabling a Chip Select.The TSA1401 is available in the industrial temperature range of 40°C to +85°C and in a small 48-lead TQFP package. December 2003 1/19 1/19 TSA1401 1 ABSOLUTE MAXIMUM RATINGS ABSOLUTE MAXIMUM RATINGS Symbol Parameter AVCC, DVCC, VCCBI VCCBE Analog, digital, digital buffer Supply voltage Digital buffer Supply voltage Analog inputs VIN, VINB, VREFP, VREFM, VINCM IDout Tstg ESD Values Unit -0.3V to 3.3V V 0V to 3.6V V -0.3V to AVCC+0.3V V -100mA to 100mA +150 mA °C 2000 700 V 1 1 Digital output current Storage temperature Electrical Static Discharge - HBM: Human Body Model2 - CDM-JEDEC Standard ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs Latch-up Class3 A 1) All voltage values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3V or VCC 2) ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5kΩ 3) ST Microelectronics Corporate procedure number 0018695 OPERATING CONDITIONS Symbol Parameter Test conditions Min Typ Max Unit AVCC Analog Supply voltage 2.25 2.5 2.7 V DVCC Digital Supply voltage 2.25 2.5 2.7 V VCCBI Digital buffer Supply voltage 2.25 2.5 2.7 V VCCBE Digital buffer Supply voltage 2.25 2.5 3.3 V BLOCK DIAGRAM VREFP REFMODE +2.5V GNDA VIN stage 1 INCM VINB stage 2 stage n Reference circuit IPOL VREFM DFSB Sequencer-phase shifting OEB CLK Timing Digital data correction DR DO Buffers O TO D13 OR GND 2/19 ABSOLUTE MAXIMUM RATINGS TSA1401 PIN DESCRIPTIONS Pin Name I/O IPOL VREFP VREFM AGND VIN VINB INCM I No Pin Description 1 Analog bias current input - adjusts polarization current versus Fs. Top Reference Voltage - may be used as a voltage generator output or used as an I/O 2 input to adjust the input dynamic range (VIN-VINB=2x(VREFP-VREFM)). I 3 Bottom Reference Voltage. Usually connected to GND (see AN p12 for details) I 4, 6, 8, 10, 48 Analog ground. I 5 Positive Analog input. I 7 Negative Analog Input. Internal Common Mode - may be used as a voltage generator output for input sigI/O 9 nal common mode or used as an input to force the internal common mode (see AN p12 for more details). I 11, 12, 46, 47 Analog Power Supply (2.5V). I 13, 14 Digital Power Supply (2.5V) (Clock). I 15, 17,19 Digital Ground (Clock). I 16 CMOS Clock Input. NA 18, 42 Non Connected Pin. I 20 Digital Ground (Internal Buffer). I 21,40 Digital Ground (External Buffer). I 22, 39 Digital Power Supply (External Buffer, 2.5V/3.3V). O 23 Over Range Indicator, if D0-D13=’1’ or ‘0’, OR=’1’. Data CMOS Outputs (2.5V/3.3V). O 24-37 ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs AVCC DVCC DGND CLK NC GNDBI GNDBE VCCBE OR D13(MSB)D0(LSB) DR VCCBI O I 38 41 REFMODE I 43 OEB I 44 DFSB I 45 Data Ready Signal (2.5V/3.3V). Digital Power Supply (Internal Buffers 2.5V). REFMODE=’VIL’, internal references active. REFMODE=‘VIH’, external references must be applied. Output Enable Input. If OEB=’VIH’ then D0-D13 in ‘High Z’ state. Data Format Select Input - If DFSB=’VIH’ then D13 is standard binary output coding; if DFSB=’VIL’ then D13 is two’s complemented. O 3/19 TSA1401 2 ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCBI =VCCBE = 2.5V, Fs= 20MHz, Fin= 10MHz, VIN-VINB@ -1.0dBFS, VREFM= 0V, VREFP=1V, INCM=0.5V (external references), Tamb = 25°C (unless otherwise specified) Timing Characteristics Symbol Parameter Test conditions Min Typ 0.5 Max Unit 20 MHz FS Sampling Frequency DC Clock Duty Cycle 50 % TC1 Clock pulse width (high) 25 ns TC2 Clock pulse width (low) 25 ns Tod Data Output Delay (Fall of Clock 10pF load capacitance to Data Valid) Tpd Data Pipeline delay Ton Toff ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs 6 7.5 cycles Falling edge of OEB to digital output valid data 1 ns Rising edge of OEB to digital output tri-state 1 ns N+4 N+5 N+3 N+6 N+7 N+2 N-1 N+1 N N+8 CLK 8.5 clk cycles OEB Tod Ton Toff N-8 N-7 N-6 N-5 N-4 N-1 N-3 DR HZ state O 4/19 ns 8.5 Timing Diagram DATA OUT 11 N ELECTRICAL CHARACTERISTICS TSA1401 Dynamic Characteristics Symbol SFDR1 Parameter Test conditions Min Spurious Free Dynamic Range Fin=10MHz, VREFP=1V Fin=10MHz, VREFP=1.24V (TS431) Signal to Noise Ratio Fin=10MHz, VREFP=1V Total Harmonic Distortion -89 -74 Unit dBFS -91 68 Fin=10MHz, VREFP=1.24V (TS431) THD1 Max -91.5 Fin=10MHz, internal references SNR1 Typ 71.5 73.1 Fin=10MHz, internal references 70 Fin=10MHz, VREFP=1V -85 dBc -71 ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs Fin=10MHz, VREFP=1.24V (TS431) -85.9 Fin=10MHz, internal references SINAD1 ENOB1 Signal to Noise and Distortion Ratio Effective Number of Bits Fin=10MHz, VREFP=1V 71 66 Fin=10MHz, VREFP=1.24V (TS431) 72.85 Fin=10MHz, internal references 69.9 Fin=10MHz, VREFP=1V dBc -86 10.9 dBc 11.7 Fin=10MHz, VREFP=1.24V (TS431) 12 Fin=10MHz, internal references bits 11.5 1) Typical values have been measured using the evaluation board on a dedicated test bench. Accuracy Symbol Parameter Min Typ Max Unit OE Offset Error -3 LSB GE Gain Error 0.04 % DNL Differential Non Linearity ±0.8 LSB INL Integral Non Linearity ±2 LSB - Monotonicity and no missing codes Guaranteed Analog Inputs Symbol Parameter Test conditions VIN-VINB Analog Input Voltage, Differential Cin Analog Input capacitance Zin Analog Input impedance Fs=20MHz Analog Input Bandwidth (-3dB) Full power, VIN-VINB=2.0Vpp, Fs=20MHz O BW Min Typ Max Unit 2 Vpp 4.0 pF 3.3 kΩ 1000 MHz Internal Reference Voltage Symbol Parameter REFP Top internal reference voltage REFM Bottom internal reference voltage INCM Internal common mode voltage Test conditions Min Typ Max Unit 0.75 0.84 0.9 V 0 0.4 0.44 V 0.5 V 5/19 TSA1401 Symbol RrefO ELECTRICAL CHARACTERISTICS Parameter Reference output impedance Test conditions Min REFMODE=’0’: int references Typ Max Unit Ω 18.7 External Reference Voltage Symbol Parameter VREFP Forced Top reference voltage VREFM Bottom reference voltage VINCM Forced common mode voltage Test conditions REFMODE=’1’ Min Typ Max Unit 0.8 1.3 V 0 0.2 V 0.4 1 V ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs RrefI Reference input impedance Vpol Analog bias voltage 7.5 REFMODE=’1’ kΩ 1.22 1.27 1.34 V Min Typ Max Unit 40 30 37 595 700 µA Power Consumption Symbol ICCA Parameter Analog Supply current Test conditions REFMODE=’0’ REFMODE=’1’ mA ICCD Digital Supply Current ICCBI Digital Buffer Supply Current 1 1.5 mA ICCBE Digital Buffer Supply Current 2.3 6 mA ICCBEZ Digital Buffer Supply Current in High Impedance Mode 10 150 µA Pd Power consumption in normal opera- REFMODE=’0’ tion mode REFMODE=’1’ 110 REFMODE=’0’ REFMODE=’1’ 104 PdZ Rthja Power consumption in High Impedance mode Thermal resistance (TQFP48) 1) Typical values have been measured using the evaluation board on a dedicated test bench. O 6/19 851 791 80 110 96 mW mW °C/W ELECTRICAL CHARACTERISTICS TSA1401 Digital Inputs and Outputs Symbol Parameter Test conditions Min Typ Max Unit 0.8 V Clock inputs VIL Logic "0" voltage DVCC=2.5V VIH Logic "1" voltage IIL Low input current TBD µA IIH High input current TBD µA 2.0 V Digital inputs ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs VIL Logic "0" voltage VCCBE=2.5V 0.25 VCCBE VIH Logic "1" voltage IIL Low input current TBD µA IIH High input current TBD µA 0.75 VCCBE V V Digital Outputs VOL Logic "0" voltage VCCBE=2.5V, Iol=10µA VOH Logic "1" voltage VCCBE=2.5V, Ioh=10µA 0.1 2.45 V V O 7/19 TSA1401 3 DEFINITIONS OF SPECIFIED PARAMETERS DEFINITIONS OF SPECIFIED PARAMETERS 3.1 Static Parameters Signal to Noise and Distortion Ratio (SINAD) Static measurements are performed through the method of histograms on a 2MHz input signal, sampled at 20Msps, which is high enough to fully characterize the test frequency response. An input level of +1dBFS is used to saturate the signal. Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. Differential Non Linearity (DNL) When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: SINAD= 6.02 × ENOB + 1.76 dB. ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs The average deviation of any output code width from the ideal code width of 1LSB. Integral Non linearity (INL) An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve. 3.2 Dynamic Parameters Dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies and sampled at 20Msps. Spurious Free Dynamic Range (SFDR) The ratio between the amplitude of fundamental tone (signal power) and the power of the worst spurious signal (not always an harmonic) over the full Nyquist band. It is expressed in dBc. Total Harmonic Distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. Signal to Noise Ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (Fs/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. O 8/19 SINAD= 6.02 × ENOB + 1.76 dB + 20 log (2A0/FS) The ENOB is expressed in bits. Analog Input Bandwidth The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3dB. Higher values can be achieved with smaller input levels. Effective Resolution Bandwidth (ERB) The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output, on the output bus. Also called data latency. It is expressed as a number of clock cycles. TYPICAL PERFORMANCE CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS Fs=20MHz; Icca=40mA 12 11.9 77 11.8 11.7 74 11.6 ENOB 11.5 71 11.4 SNR ENOB (Bits) Dynamic parameters (dB) 80 Fig. 4: Linearity vs. Fin, External References (REFP=1V) Fs=20MHz; Icca=28mA 80 12 77 11.8 ENOB 74 11.6 SINAD 71 11.4 SNR ENOB (Bits) Fig. 1: Linearity vs. Fin, Internal References Dynamic parameters (dB) 4 TSA1401 ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs 11.3 SINAD 68 11.2 11.1 65 11.2 65 11 5 11 0 5 10 15 20 Fin (Mhz) 25 10 15 30 20 25 30 Fin (Mhz) Fig. 2: Distortion vs. Fin, Internal References Fs=20MHz; Icca=40mA; Internal references Fig. 5: Distortion vs. Fin, External References (RefP=1V) Fs=20MHz; Icca=28mA -70 -70 -75 -75 Distortion (dBc) Distortion (dBc) 68 -80 THD -85 SFDR -90 -80 THD -85 -90 SFDR -95 -95 -100 -100 5 0 5 10 15 Fin (Mhz) 20 25 10 30 Fig. 3: 2nd. and 3rd. harmonic vs. Fin, Internal References, Fs=20MHz; Icca=40mA 15 20 Fin (Mhz) 25 30 Fig. 6: 2nd. and 3rd. harmonic vs. Fin, External References (REFP=1V) Fs=20MHz; Icca=28mA -65 -60 -70 -65 -75 -70 Distortion (dB) O Distortion (dB) -60 -80 -85 H2 -90 -95 -80 H3 -85 -90 H2 -95 -100 H3 -100 -75 -105 -105 -110 0 5 10 15 Fin (Mhz) 20 25 30 -110 5 10 15 20 Fin (Mhz) 25 30 9/19 TSA1401 TYPICAL PERFORMANCE CHARACTERISTICS Fig. 7: SFDR vs. input amplitude (FS=2x0.86V) Fs=20Msps; Fin=5Mhz;Icca=40mA, -20 SFDR(dBc and dBFS) -30 -40 -50 -60 SFDR(dBc) -70 -80 -90 ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs SFDR(dBFS) -100 -110 -30 -25 -20 -15 SFSR(dB) -10 -5 0 Fig. 8: Single-tone 16K FFT at Fs=20 Msps, Internal references Fin=5MHz, Icca=40mA,Vin@-1dBFS, SFDR=-89.3dBc, THD=-84.5dBc, SNR=70.5dB, SINAD=70.3dB, ENOB=11.5 bits 0 -2 0 -4 0 -6 0 -8 0 -1 0 0 -1 2 0 -1 4 0 -1 6 0 -1 8 0 0 5 F (M h z) Fig. 9: Single-tone 16K FFT at Fs=20Msps, External References TS4041 Fin=5MHz, Icca=40mA, Vin@-1dBFS, VREFP=1.225V SFDR=-87.5dBc, THD=-85.4dBc, SNR=73.3dB, SINAD=73dB, ENOB=11.84 bits 20 0 O Power spectrum -2 0 -4 0 -6 0 -8 0 -1 0 0 -1 2 0 -1 4 0 -1 6 0 0 5 F (M h z) 10/19 10 TYPICAL PERFORMANCE CHARACTERISTICS TSA1401 Static parameter: Differential Non Linearity Fs=20MSPS; Fin=1MHz; Icc=40mA;N=524288pts 1 .2 1 0 .8 0 .6 0 .4 0 .2 0 -0 . 2 -0 . 4 -0 . 6 ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs -0 . 8 Static parameter: Integral Non Linearity Fs=20MSPS; Fin=1MHz; Icc=40mA; N=524288pts 2 .5 2 1 .5 1 0 .5 0 -0 . 5 -1 -1 . 5 -2 -2 . 5 O 11/19 TSA1401 5 APPLICATION INFORMATION APPLICATION INFORMATION The TSA1401 is a High Speed Analog to Digital converter based on a pipeline architecture and the latest deep sub micron CMOS process to achieve the best performances in terms of linearity and power consumption. The pipeline structure consists of 14 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. Each of the 14 stages consists of an Analog to Digital converter, a Digital to Analog converter, a Sample and Hold and an amplifier (gain=2). A 1.5bit conversion resolution is achieved in each stage. Each resulting LSB-MSB couple is then time-shifted to recover from the delay caused by conversion. Digital data correction completes the processing by recovering from the redundancy of the (LSB-MSB) couple for each stage. The corrected data are outputted through the digital buffers. Internal references, common mode: When REFMODE is set to VIL level, TSA1401 operates with its own reference voltage generated by its internal bandgap. VREFM pin is connected externally to the Analog Ground while VREFP is set to its internal voltage (0.86V). The full scale of the ADC when using internal references is 1.8Vpp (to reduce the full scale if desired, VREFM may be forced externally). ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs Signal input is sampled on the rising edge of the clock while digital outputs are delivered on the falling edge of the clock. The advantages of such a converter reside in the combination of pipeline architecture and the most advanced technologies. The highest dynamic performances are achieved while consumption remains at the lowest level. 5.1 Analog Input Configuration In this case VREFP and INCM are low impedance outputs. INCM pin (voltage generator 0.46V) may be used to supply the common mode, CM of the analog input signal. External references, common mode: In applications requiring a different full scale magnitude, it is possible to force externally VREFP and INCM (REFM must be connected to analog ground or forced externally). REFMODE set to VIH level will put in standby mode the internal references. In this case, VREFP, INCM are high impedance inputs and have to be forced by external references. TSA1401 shows better performances when the full scale is increased by the use of external references (see Figure 10 and 11). Fig. 10: Linearity vs. VREFP Fin=5MHz;Fs=20Mhz;Icca=26mA;INCM=0.45V 80 12.4 To maximize the TSA1401’s high-resolution and speed, it is advisable to drive the analog input differentially. The full scale of TSA1401 is adjusted through the voltage value of VREFP and VREFM: VIN-VINB=2(VREFP-VREFM) O The differential analog input signal always presents a common mode voltage, CM: CM=(VIN+VINB)/2 In order for the user to select the right full scale according to the application, a control pin, REFMODE, allows to switch from internal to external references. 12/19 Dynamic parameters (dB) 5.1.1 Analog input level and references 12.2 77 12 ENOB 74 SINAD 11.8 SNR 71 11.6 11.4 68 11.2 65 11 0.8 0.9 1 1.1 1.2 REFP (V) 1.3 1.4 APPLICATION INFORMATION TSA1401 Fig. 11: Distortion vs. VREFP Fin=5MHz;Fs=20Mhz;Icca=26mA;INCM=0.46V Fig. 13: Linearity vs. Fs at Fin=5MHz, using TS4041 Icca optimised; VREFP=1.225V; VREFM=GND; INCM=0.65V, -70 80 -80 THD -85 -90 SFDR 12.1 12 ENOB 77 11.9 11.8 74 11.7 SNR 11.6 SINAD 71 11.5 11.4 ENOB (Bits) Dynamic parameters (dB) Distortion (dBc) -75 ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs -100 0.8 0.9 1 1.1 REFP (V) 1.2 1.3 1.4 An external reference voltage device may be used for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. Using the STMicroelectronics TS821, TS4041-1.2 or TS431 Voltage Reference devices leads to optimum performances when configured as shown in Figure 12. The full scale is increased to 2.5Vpp differential and SNR and SINAD are enhanced as shown in Figure 13 . Fig. 12: External reference setting 330pF 10nF 4.7µF VREFP 100Ω VIN TSA1401 VINB VREFM TS4041 TS821 external reference In multi-channel applications, the high impedance input of the references permits to drive several ADCs with only one Voltage Reference device. O 11.3 11.2 65 11.1 3 5 7 9 11 13 Fs (Mhz) 15 17 19 21 Fig. 14: Distortion vs. Fs at Fin=5MHz, using TS4041 Icca optimised; VREFP=1.225V; VREFM=GND; INCM=0.65V -70 -75 -80 -85 THD -90 SFDR -95 1kΩ REFMODE AVCC 68 Distortion (dBc) -95 -100 3 5 7 9 11 13 Fs (Mhz) 15 17 19 21 The magnitude of the analog input common mode, CM should stay close to VREFP/2. Higher level will introduce more distortion. 5.1.2 - Driving the analog input The TSA1401 has been designed to be differentially driven for better noise immunity. Some measurements have been done with single-ended signals. It degrades a little bit the performances, with an SFDR of -75dBc and an ENOB of 11.2 bits at 20Msps, Fin at 10MHz. The switch-capacitor input structure of TSA1401, presents a high input impedance (3.3kΩ at Fs=20MHz) but not constant in time (see equivalent input circuit Figure 15). Indeed at the end of each conversion, the charge update of the 13/19 TSA1401 APPLICATION INFORMATION sampling capacitor will draw/inject a small current transient on the input signal. One method to mask this transient current is a low-pass RC filter as shown on Figures 16 and Figure 17. A larger capacitor value compared to the sampling capacitor (appoximately 2pF) mounted in parallel of the two analog inputs signals will absorb the transient glitches. configuration. Both inputs VIN and VINB are centered around the common mode voltage CM, that can be forced through INCM or supplied externally (in this case the internal common mode of the TSA1401 may be left internal at 0.45V, different from the input common mode value). Fig. 17: AC-coupled differential input Fig. 15: ADC input equivalent circuit VIN ) s ( t c u d o s) r ( P t c e u t e l rod o s P b O ete l ) o s ( s t b c u -O d o s) r ( P t e uc t e l od o s Pr b O ete l o bs 50Ω AVcc 10nF 100kΩ 33pF common mode 100kΩ Zin =1/(2ΠCs.Fs)=3.3kΩ (Fs=20MHz) VIN 50Ω Cin=4pF VINB 10nF 5.2 - Clock management Single-ended signal with transformer: Using an RF transformer is a good means to achieve high performance. Figures 16 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. Fig. 16: Differential input configuration with transformer The converter performances are very dependant on clock input accuracy, in terms of aperture delay and jitter. The voltage error induced by the jitter of the clock is: Verror=SR.Tj, where Tj is the jitter of the clock (system clock and ADC) and, SR is the slew rate of the input signal: SR max=2Π.Fin.FS (FS full scale, Fin input signal frequency) ADT1-1 1:1 VIN 50Ω TSA1401 INCM AGND Analog source INCM TSA1401 100pF VINB 330pF 10nF INCM 4.7µF Verror should be less than an LSB to guarantee no missing codes. At the end we have: Verror=2Π.Fin.FS.Tj and Verror< FS/2n Tj