TSC2010, TSC2011, TSC2012
Datasheet
High voltage, precision, bidirectional current sense amplifiers
Features
SO8
MiniSO8
•
•
•
•
•
•
•
•
Wide common mode voltage: - 20 to 70 V
Offset voltage: ± 200 µV max
2.7 to 5.5 V supply voltage
Different gain available
–
TSC2010: 20 V/V
–
TSC2011: 60 V/V
–
TSC2012: 100 V/V
Gain error: 0.3% max
Offset drift: 5 µV/°C max
Quiescent current: 20 µA in shutdown mode
SO8 and MiniSO8 package
Applications
Maturity status link
TSC2010, TSC2011, TSC2012
•
•
•
•
•
•
•
High-side current sensing
Low-side current sensing
Data acquisition and instrumentation
Test and measurement equipment
Industrial process control
Motor control
Solenoid control
Description
The TSC2010, TSC2011 and TSC2012 are precision bidirectional current sense
amplifiers. They can sense the current thanks to a shunt resistor over a wide range
of common mode voltages, from - 20 to + 70 V, whatever the supply voltage is. They
are available with an amplifier gain of 20V/V for TSC2010, 60 V/V for TSC2011 and
100 V/V for TSC2012.
They are able to sense very low drop voltages as low as 10 mV full scale minimizing
the measurement error.
The TSC2010, TSC2011 and TSC2012 can also be used in other functions such
as: precision current measurement, overcurrent protection, current monitoring, and
feedback loops.
This device fully operates over the broad supply voltage range from 2.7 to 5.5 V and
over the industrial temperature range from -40 to 125 °C.
DS13057 - Rev 6 - September 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
TSC2010, TSC2011, TSC2012
Diagram
1
Diagram
Figure 1. Block diagram
DS13057 - Rev 6
page 2/53
TSC2010, TSC2011, TSC2012
Pin configuration
2
Pin configuration
Figure 2. Pin connection (top view)
Table 1. Pin description
DS13057 - Rev 6
Pin
Pin name
Description
1
IN -
2
GND
3
VREF2
Reference voltage 2
4
SHDN
Shutdown
5
OUT
Output
6
VCC
Supply voltage
7
VREF1
8
IN +
Negative input
Ground
Reference voltage 1
Positive input
page 3/53
TSC2010, TSC2011, TSC2012
Maximum ratings
3
Maximum ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
Supply voltage (1)
-0.3 to 7
V
VICM
Common mode voltage on input pins
-25 to 76
V
VDIF
Differential voltage between input pins (In+, In-)
7
V
Gnd - 0.3 to Vcc + 0.3
V
5
mA
VREF1 VREF2 VOUT
IIN
Voltage present on pins Ref1, Ref2, Out
Input current to any pins (2)
TSTG
Storage temperature
-65 to 150
°C
TJ
Junction temperature
150
°C
125
°C/W
Thermal resistance junction to ambient (3)(4)
RTHJA
SO8
MiniSO8
ESD
190
Human body model (HBM)
(5)
Charged device model (CDM)
2000
(6)
Latch-up immunity
1000
200
V
mA
1. All voltage values, except the differential voltage are with respect to the network ground terminal.
2. Input voltage can go beyond supply voltage but input current must be limited. Using a serial resistor with the input is highly
recommended in that case.
3. Short-circuits can cause excessive heating and destructive dissipation.
4. Rth are typical values.
5. According to JEDEC standard JESD22-A114F.
6. According to ANSI/ESD STM5.3.1.According to ANSI/ESD STM5.3.1.
Table 3. Operating conditions
Symbol
Value
Unit
Vcc
Supply voltage
2.7 to 5.5
V
Vicm
Common mode voltage on input pins
-20 to +70
V
Vref
Output offset adjustment range
0 to Vcc
V
-40 to 125
°C
T
DS13057 - Rev 6
Parameter
Operating free-air temperature range
page 4/53
TSC2010, TSC2011, TSC2012
Electrical characteristics
4
Electrical characteristics
Table 4. Electrical characteristics Vcc = 2.7 V, Vicm = 12 V, T = 25 °C (unless otherwise specified).
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Power supply
Current consumption
Icc
Current consumption with
shutdown active
Vicm = -20 to 70 V
1.5
2.3
2.3
Tmin < T < Tmax
Vicm = - 20 to 70 V
20
50
Tmin < T < Tmax
150
Vicm = 1 V
200
Tmin < T < Tmax
700
Vicm = 12 V
500
Tmin < T < Tmax
1100
mA
µA
Input
|Vos|
|ΔVos/ΔT|
CMR
Iib+
Iib-
|Vsense|
Offset voltage (RTI) (1)
Offset drift vs. temperature
Common mode rejection
Input bias current
Input bias current
Vsense operating range with
Eg ≤ 0.3% (2)
µV
Vicm = 1 V, Tmin < T < Tmax
5
Vicm = 12 V, Tmin < T < Tmax
8
Vicm = -20 to 70 V, DC mode
90
Tmin < T < Tmax
85
Vicm = 12 V
Tmin < T < Tmax, Vicm = -20 to 70 V
dB
350
-400
Vicm = 12 V
Tmin < T < Tmax, Vicm= - 20 to 70 V
115
µV/°C
600
100
-150
µA
350
TSC2010
123.6
Tmin < T < Tmax
122.4
TSC2011
40.5
Tmin < T < Tmax
39.3
TSC2012
23.9
Tmin < T < Tmax
22.7
mV
Output
G
Eg
Gain error vs. temperature
20
TSC2011
60
TSC2012
100
0.3
Tmin < T < Tmax
0.3
25
Gain error drift
Tmin < T < Tmax
NLE
Linearity error
Vicm = 12 V
Drop voltage output high
V/V
ΔVout = 100 mV to (Vcc - 100 mV)
ΔEg/ΔT
Vcc - Voh
DS13057 - Rev 6
Gain
TSC2010
Isource = 0.2 mA
Tmin < T < Tmax
0.03
8
%
ppm/°C
%
15
20
mV
page 5/53
TSC2010, TSC2011, TSC2012
Electrical characteristics
Symbol
Vol
Iout
Reg Load
Parameter
Output voltage low
Output current
Load regulation
Conditions
Min.
Isink = 0.2 mA
Typ.
Max.
12
20
30
Tmin < T < Tmax
Sink mode
12
Tmin < T < Tmax
8
Source mode
6
Tmin < T < Tmax
4
Iout = - 10 to +4 mA
20
Unit
mV
25
30
10
14
mA
17
0.3
1.5
mV/mA
OFFSET adjustment
Rt
Acc
Ratiometric accuracy
Accuracy, RTO
Voltage applied to Vref1 and Vref2 in
parallel
0.5
V/V
0.1
%
Dynamic performances
Rl = 10 kΩ, Cl = 100 pF
BW
Small signal -3 dB bandwidth
TSC2010
600
TSC2010, Tmin < T < Tmax
300
TSC2011
500
TSC2011, Tmin < T < Tmax
250
TSC2012
330
TSC2012, Tmin < T < Tmax
170
750
620
kHz
415
Rl = 10 kΩ, Cl = 100 pF, Vicm = 1 V
SR
En
Slew rate
TSC2010, Vsense = 120 mV
3.0
TSC2010, Tmin < T < Tmax
2.7
TSC2011, Vsense = 40 mV
2.7
TSC2011, Tmin < T < Tmax
2.5
TSC2012, Vsense = 24 mV
2.0
TSC2012, Tmin < T < Tmax
1.8
3.9
3.5
V/µs
2.8
Noise, RTI
0.1 Hz to 10 Hz
37
µVpp
Spectral density, RTI
f = 1 kHz
100
nV/√Hz
Shutdown function (active high)
Vil
Logical low level
0
0.3xVcc
Vih
Logical high level
0.7xVcc
Vcc
Iih
Leakage current
Vshdn = Vcc (Shutdown mode)
V
0.9
µA
TSC2011
6
µs
TSC2010, TSC2012
8
Vshdn= 2.7 V to 0 V, Rl = 10 kΩ
Ton
Turn-on time
Vshdn = 0 V to 2.7 V, Rl= 10 kΩ
Toff
DS13057 - Rev 6
Turn-off time
TSC2011
4
TSC2010, TSC2012
5
µs
page 6/53
TSC2010, TSC2011, TSC2012
Electrical characteristics
Symbol
Iout
Parameter
Output leakage current
Conditions
Shdn active
Min.
Typ.
50
Max.
Unit
nA
1. RTI stands for “Related to input”.
2. Vsense=(Vin+) – (Vin-).
DS13057 - Rev 6
page 7/53
TSC2010, TSC2011, TSC2012
Electrical characteristics
Table 5. Electrical characteristics (Vcc = 5 V, Vicm = 12 V, T = 25 °C unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
1.6
2.4
Unit
Power supply
Current consumption
Icc
Current consumption with
shutdown active
SVR
Supply voltage rejection
Vicm = -20 to 70 V
2.4
Tmin < T < Tmax
Vicm = - 20 to 70 V
20
Tmin < T < Tmax
Vcc = 2.7 to 5.5 V
Tmin < T < Tmax
50
150
80
100
mA
µA
dB
75
Input
|Vos|
|ΔVos/ΔT|
CMR
Iib+
Iib-
|Vsense|
Offset voltage (RTI) (1)
Offset drift vs. temperature
Common mode rejection
Input bias current
Input bias current
Vsense operating range with
Eg ≤ 0.3% (2)
Vicm = 1 V
200
Tmin < T < Tmax
700
Vicm = 12 V
500
Tmin < T < Tmax
1100
µV
Vicm = 1 V, Tmin < T < Tmax
5
Vicm = 12 V, Tmin < T < Tmax
8
Vicm = -20 to 70 V, DC mode
90
Tmin < T < Tmax
85
Vicm = 12 V
Tmin < T < Tmax, Vicm = -20 to 70 V
dB
350
-400
Vicm = 12 V
Tmin < T < Tmax, Vicm= - 20 to 70 V
120
µV/°C
600
100
-150
µA
350
TSC2010
238.3
Tmin < T < Tmax
237.1
TSC2011
78
Tmin < T < Tmax
77.6
TSC2012
46.9
Tmin < T < Tmax
45.7
mV
Output
G
Eg
Gain error vs. temperature
20
TSC2011
60
TSC2012
100
0.3
Tmin < T < Tmax
0.3
25
Gain error drift
Tmin < T < Tmax
NLE
Linearity error
Vicm = 12 V
Drop voltage output high
V/V
ΔVout = 100 mV to (Vcc - 100 mV)
ΔEg/ΔT
Vcc - Voh
DS13057 - Rev 6
Gain
TSC2010
Isource = 0.2 mA
Tmin < T < Tmax
0.03
15
%
ppm/°C
%
30
35
mV
page 8/53
TSC2010, TSC2011, TSC2012
Electrical characteristics
Symbol
Vol
Iout
Reg Load
Parameter
Output voltage low
Output current
Load regulation
Conditions
Min.
Isink = 0.2 mA
Typ.
Max.
26
40
50
Tmin < T < Tmax
Sink mode
25
Tmin < T < Tmax
15
Source mode
12
Tmin < T < Tmax
8
Iout = -10 to +10 mA
36
Unit
mV
50
60
25
45
mA
55
0.3
1.5
mV/mA
OFFSET adjustment
Rt
Acc
Ratiometric accuracy
Accuracy, RTO
Voltage applied to Vref1 and Vref2 in
parallel
0.5
V/V
0.1
%
Dynamic performance
Rl = 10 kΩ, Cl = 100 pF
BW
Small signal -3 dB bandwidth
TSC2010
650
TSC2010, Tmin < T < Tmax
330
TSC2011
600
TSC2011, Tmin < T < Tmax
300
TSC2012
390
TSC2012, Tmin < T < Tmax
200
820
750
kHz
490
Rl = 10 kΩ, Cl = 100 pF, Vicm = 1 V
SR
En
Slew rate
TSC2010, Vsense = 230 mV
5.7
TSC2010, Tmin < T < Tmax
4.4
TSC2011, Vsense = 78 mV
5.4
TSC2011, Tmin < T < Tmax
4.1
TSC2012, Vsense = 47 mV
4.4
TSC2012, Tmin < T < Tmax
3.2
7.5
7
V/µs
5.2
Noise, RTI
0.1 Hz to 10 Hz
37
µVpp
Spectral density, RTI
f = 1 kHz
100
nV/√Hz
Shutdown function (active high)
Vil
Logical low level
0
0.3xVcc
Vih
Logical high level
0.7xVcc
Vcc
Iih
Leakage current
Vshdn = Vcc (Shutdown mode)
V
1.2
µA
TSC2011
6
µs
TSC2010, TSC2012
8
Vshdn= 5 V to 0 V, Rl = 10 kΩ
Ton
Turn-on time
Vshdn = 0 V to 5 V, Rl= 10 kΩ
Toff
DS13057 - Rev 6
Turn-off time
TSC2011
4
TSC2010, TSC2012
5
µs
page 9/53
TSC2010, TSC2011, TSC2012
Electrical characteristics
Symbol
Iout
Parameter
Output leakage current
Conditions
Shdn active
Min.
Typ.
50
Max.
Unit
nA
1. RTI stands for “Related to input”.
2. Vsense = (Vin+) – (Vin-).
DS13057 - Rev 6
page 10/53
TSC2010, TSC2011, TSC2012
Typical characteristics
4.1
Typical characteristics
TSC2011 is used for typical characteristics, unless otherwise noted.
Figure 3. Supply current vs. supply voltage
Figure 4. Supply current vs. input common mode
1.9
1.9
Vicm=2.5V
1.7
Vicm=0V
Vicm=12V
1.6
1.5
Vicm=70V
1.4
1.3
2.8
3.1
3.5
3.9
4.2
Vref=Vcc/2
Vsense=0V
T=25°C
1.8
Supply current (mA)
Supply Current (mA)
1.8
4.5
1.7
Vcc=5V
1.6
Vcc=3.3V
1.5
Vcc=2.7V
Vref=Vcc/2
Vsense=0V
T=25°C
1.4
4.9
1.3
-20
5.3
-10
0
10
Supply voltage (V)
20
30
40
50
60
70
Vicm (V)
Figure 5. Supply current vs. temperature
Figure 6. Supply current vs. input common mode with
active shutdown mode
1.9
Vicm= -20V
24
22
20
Vicm=0V
1.7
Supply Current (µA)
Supply Current (mA)
1.8
Vicm=12V
1.6
Vicm=48V
1.5
Vicm=70V
18
16
12
8
4
Vsense=0V
Vcc=5V
1.3
-40
-20
2
0
20
40
60
Temperature (°C)
DS13057 - Rev 6
80
100
120
Vcc=3.3V
10
6
1.4 Vref=Vcc/2
Vcc=5V
14
0
-20
Vref=Vcc/2
SHDN=Vcc
Vsense=0V
T=25°C
-10
0
Vcc=2.7V
10
20
30
40
50
60
70
Vicm (V)
page 11/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 7. Input bias current vs. input common mode with
shutdown active
Figure 8. Input bias current vs. temperature VCC = 2.7 V
600
400
500
300
400
Iibp
300
200
Iibp 25°C
Iibp -40 °C
Iib (µA)
100
Iib (µA)
200
Iibn
0
-100
100
Iibn [-40° : 125°]
0
-100
-200
-200
-300
-400
-20
-10
0
Iibp 125°C
-300
Vref=Vcc/2
SHDN=Vcc
Vsense=0V
T=25 °C
Vcc=2.7 to 5.5V
Vref=VCC /2
Vsense=0V
Vcc=2.7V
-400
-500
10
20
30
40
50
60
-600
-20
70
-10
0
10
20
Figure 9. Input bias current vs. temperature with VCC = 5 V
500
400
300
Iibp -40 °C
Vio (µV)
Iib (µA)
200
Iibp 25°C
Iibn [ -40 °:125 °]
-100
-200
Iibp 125 °C
-300
Vref=Vcc/2
Vsense=0V
Vcc=5V
-400
-500
-600
-20
-10
0
10
20
30
Vicm (V)
DS13057 - Rev 6
50
60
70
Figure 10. Input offset voltage vs. temperature
600
0
40
Vicm (V)
Vicm (V)
100
30
40
50
60
70
700
600
500
400
300
200
100
0
-100
-200
-300
-400 Vref=Vcc/2
Vsense=0V
-500 Vcc=5V
-600
-700
-40 -20
0
Vicm=48V
Vicm=12V
Vicm= -20V
Vicm=70V
Vicm=0V
20
40
60
80
100
120
Temperature (°C)
page 12/53
TSC2010, TSC2011, TSC2012
Typical characteristics
700
600
500
400
300
200
100
Figure 12. Input offset voltage vs. input common mode
with VCC = 5 V
T=125°C
T=25°C
T=85°C
0
T=-20°C
-100
-200
-300
-400
-500
-600
Vio (µV)
Vio (µV)
Figure 11. Input offset voltage vs. input common mode
with VCC = 2.7 V
T=-40°C
T=0°C
Vref=Vcc/2
Vsense=0V
Vcc=2.7V
-700
-20
-10
0
10
20
30
40
50
60
70
700
600
500
400
300
200
100
0
T=-40°C
-100
-200
-300
-400
Vref=Vcc/2
-500 Vsense=0V
-600 Vcc=5V
-700
-20 -10
0
Vicm (V)
300
Vicm=12V
100
-100
-200
Vicm=1V
Vicm= -20V
Vicm=48V
Vicm= -10V
Vicm=70V
-300
Vref=Vcc/2
Vsense=0V
T=25°C
-400
-500
3.0
3.5
4.0
Vcc (V)
DS13057 - Rev 6
Iout (mA)
Vio (µV)
200
0
T=-20°C
10
20
30
T=85 °C
T=0°C
40
50
60
70
Figure 14. Output current vs. output voltage
500
Vicm=5V
T=25 °C
Vicm (V)
Figure 13. Input offset voltage vs. supply voltage
400
T=125 °C
4.5
5.0
5.5
40
35
30
Isink
25
20
15
10
Vcc=2.7V
Vcc=3.3V
Vcc=5.5V
5
0
-5
-10
-15
-20
Vref=Vcc/2
-25
Vsense=100mV
-30
Isource
Vicm=12V
T=25°C
-35
-40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Vout (V)
page 13/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 15. Output current vs. temperature with VCC = 5 V
50
50
45
45
40
35
35
30
30
25
Isource
20
10
Isink
20
10
Vcc=5V
Vicm=12V
Vref=Vcc/2
Vsense=100mV
5
-40
25
15
15
0
Vcc=2.7V
Vicm=12V
Vref=Vcc/2
Vsense=100mV
40
Isink
Iout (mA)
Iout (mA)
Figure 16. Output current vs. temperature with VCC = 2.7 V
-20
0
20
40
60
80
100
5
0
-40
120
Isource
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Figure 17. Voh and Vol vs. input common mode voltage
with VCC = 5 V
Figure 18. (Output voltage + Vref) vs. Vsense
unidirectionnal with VCC = 5 V
6.0
5.4
Vcc=5V; Vref=Vcc/2
Vsense= 100mV
Rl=10kΩ connected to Vcc/2
T=25 °C
4.8
4.2
34
Vref=0V
Vcc=5V
T=25 °C
Unidirectionnal
3.6
26
VOL
17
VOH
Vout (V)
VOH and VOL drop (mV)
43
3.0
2.4
1.8
1.2
0.6
9
0.0
-0.6
0
-20
-10
0
10
20
30
Vicm (V)
DS13057 - Rev 6
40
50
60
70
-10
0
10
20
30
40
50
60
70
80
90
Vsense (mV)
page 14/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 19. (Output voltage + Vref) vs. Vsense bidirectionnal
with VCC = 5 V
Figure 20. Output rail linearity vs. load with VCC = 5 V
5.5
6.0
5.4
4.8
4.2
Vref=Vcc/2
Vcc=5V
T=25 °C
Bidirectionnal
5.0
Vout (V)
3.0
2.4
4.5
Rl=1kΩ
1.8
1.2
0.0
Rl=2kΩ
0.6
Rl=4.7k Ω
0.0
-0.6
50
Vsense (mV)
Vsense (mV)
Figure 21. Linearity vs. Vsense with VCC = 5 V
Figure 22. Linearity vs. Vsense and temperature
0.15
0.15
0.12
0.12
0.09
0.09
0.06
Vicm=1V
Vicm=-10V
0.03
Linearity error (%)
0.06
0.00
-0.03
-0.06
Vicm=12V
-0.09
Vref=Vcc/2
Vcc=5V
T=25°C
-0.12
-0.15
-50
-40
-30
-20
-10
0
10
Vsense (mV)
DS13057 - Rev 6
50
40
45
30
40
20
-40
10
-45
0
-50
-0.5
-50 -40 -30 -20 -10
Linearity error (%)
No load
Rl=10k Ω
35
Vout (V)
3.6
Vcc=5V
Vicm=12V
Vref=Vcc/2
T=25°C
20
30
40
0.03
T=25°C
0.00
-0.03
T=-40°C
-0.06
T=125°C
-0.09
Vref=Vcc/2
Vcc=5V
Vicm=12V
-0.12
50
-0.15
-50
-40
-30
-20
-10
0
10
20
30
40
50
Vsense (mV)
page 15/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 24. Gain error vs. input common mode and
temperature
Figure 23. Gain error vs. input common mode
0.30
0.30
0.25
0.25
0.20
0.20
0.15
0.15
0.05
Vcc=2.7V
Vcc=3.3V
0.00
-0.05
-0.10
Vcc=5V
-0.15
-0.20
-0.25
-20
0.05
T=25°C
0.00
-0.05
T=-40°C
-0.10
-0.15
Vref=Vcc/2
T=25°C
-0.30
T=125°C
0.10
Gain error(%)
Gain error(%)
0.10
Vref=Vcc/2
Vcc=5V
-0.20
-0.25
-10
0
10
20
30
40
50
60
70
-0.30
-20
-10
0
Vicm (V)
10
20
30
40
50
60
70
Vicm (V)
Figure 25. Load regulation with VCC = 5 V
Figure 26. Gain vs. frequency
1.30
Vcc = 3.3 V
40
Isink
Isource
Vcc = 5 V
1.25
Vcc = 2.7 V
20
1.20
Gain (dB)
Vout (V)
Vicm=70V
Vicm=12V
Vicm=-20V
1.15
1.10
-15.0
Vref=Vcc/2
Vsense=19.8mV
Vcc=5V
T=25°C
Vicm=0V
-10.0
-5.0
0.0
Iout (mA)
DS13057 - Rev 6
5.0
10.0
15.0
0
-20
Vicm = 12 V, Vref = Vcc / 2
Rl = 10kΩ ,Cl = 100 pF connected to Vcc / 2
-40
1
10
100
1000
10000
Frequency (kHz)
page 16/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 27. Gain vs. frequency VCC = 5 V
Figure 28. Gain vs. frequency different capacitive load
TSC2012
40
40
CI = 100 pF
TSC2011
20
20
Gain (dB)
Gain (dB)
TSC2010
0
CI = 470 pF
-20
-20
-40
CI = 330 pF
0
Vcc = 5 V, Vicm = 12 V, Vref = Vcc/2
Rl = 10kΩ , Cl = 10 pF connected to Vcc/2
1
10
100
Vcc=5V, Vicm=12V, Vref=Vcc/2
RI=10kΩ connected to Vcc/2
-40
1000
1
10000
10
100
1000
10000
Frequency (kHz)
Frequency (kHz)
Figure 29. Gain vs. frequency different capacitive load
(TSC2010)
Figure 30. Gain vs. frequency different capacitive load
(TSC2012)
40
40
Cl = 100 pF
Cl = 100 pF
20
Gain (dB)
Gain (dB)
20
Cl = 330 pF
0
Cl = 470 pF
Cl = 680 pF
-20
Cl = 330 pF
Cl = 470 pF
0
Cl = 680 pF
-20
Vcc = 5 V, Vicm = 12 V, Vref = Vcc/2
Rl = 10 kΩ connected to Vcc/2
-40
1
10
100
Frequency (kHz)
DS13057 - Rev 6
Vcc = 5 V, Vicm = 12 V, Vref = Vcc / 2
RI = 10kΩ connected to Vcc / 2
1000
10000
-40
1
10
100
1000
10000
Frequency (kHz)
page 17/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 31. Bandwidth vs. input common mode
Figure 32. Bandwidth vs. input common mode (TSC2010)
1.2M
1.1M
1.0M
900.0k
T = 25°C
800.0k
700.0k
T =125°C
600.0k
500.0k
400.0k
300.0k
100.0k
0.0
-20
-10
0
10
20
30
T = 25 °C
40
800.0k
700.0k
600.0k
T = 125 °C
500.0k
400.0k
300.0k
Vref = Vcc/2
Vcc = 5 V
Rl = 10 kΩ ,Cl = 100 pF connected to Vcc/2
200.0k
Vref=Vcc/2
Vcc=5V
Rl=10kΩ , Cl=100pF connected to Vcc/2
200.0k
T = -40 °C
900.0k
Bandwidth -3 dB (Hz)
Bandwidth -3dB (Hz)
1.1M
T = -40°C
1.0M
100.0k
50
60
0.0
-20
70
-10
0
10
20
30
40
50
60
70
Vicm (V)
Vicm (V)
Figure 34. Overshoot vs. capacitive load
Figure 33. Bandwidth vs. input common mode (TSC2012)
40
900.0k
30
T=-40°C
600.0k
Overshoot (%)
Bandwidth -3dB (Hz)
700.0k
T=25°C
500.0k
T=125°C
400.0k
300.0k
200.0k
100.0k
0.0
DS13057 - Rev 6
TSC2011
Vsensestep=10mVpp
35
800.0k
TSC2010
Vsensestep=30mVpp
25
20
15
TSC2012
Vsensestep=6mVpp
10
Vref=Vcc/2
Vcc=5V
Rl=10kΩ ,Cl=100pF connected to Vcc/2
0
-20 -10
0
10
20 30
Vicm (V)
40
Vcc = 5 V,
Vref=Vcc/2, Vicm[-20V:70V],
Rl = 10 k Ω, Cl connect to Gnd
5
50
60
70
100
200
300
400
500
600
700
Capacitive load (pF)
page 18/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 35. Small signal response with VCC = 5 V
50
1.0
25
Vout
Vsense
0.0
0
Vsense (mV)
Vout (V)
0.5
Figure 36. Small signal response with VCC = 5 V
(TSC2010)
-25
-0.5
Vcc=5V, Vicm=12V, Vsense=10mVpp
T=25°C, Cl=100pF
-1.0
-60µ
-40µ
-20µ
0
-50
20µ
Time (s)
Figure 37. Small signal response with VCC = 5 V
(TSC2012)
Figure 38. Small signal response with VCC= 2.7 V
50
1.0
0.5
25
0.5
0.0
0
1.0
50
-0.5
-25
Vout (V)
-0.5
-20µ
Time (s)
DS13057 - Rev 6
0
0
-25
Vcc=2.7V, Vicm=12V, Vsense=10mVpp
T=25°C, Cl=100pF
T = 25 °C, Cl = 100 pF
-40µ
Vsense
0.0
Vcc = 5 V, Vicm = 12 V, Vsense = 6 mVpp
-1.0
-60µ
25
Vout
Vsense (mV)
Vsense
Vsense (mV)
Vout (V)
Vout
-50
20µ
-1.0
-60µ
-40µ
-20µ
0
-50
20µ
Time (s)
page 19/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 40. Large signal response with VCC = 5 V
(TSC2010)
Figure 39. Large signal response with VCC = 5 V
3
50
150
3
125
100
2
2
75
25
Vcc=5V,
Vicm=12V,
Vsense=80mVpp
Cl=100pF,
T=25°C
-1
-2
0
5µ
Vout
-2
-3
-50
15µ
10µ
25
0
-25
Vcc = 5 V,
Vicm = 12 V,
Vsense = 230 mVpp
Cl = 100 pF,
T = 25 °C
-1
-25
-3
-5µ
Vsense
0
-5µ
0
5µ
-50
Vsense (mV)
0
Vout (V)
Vout
Vsense (mV)
Vout (V)
Vsense
0
50
1
1
-75
-100
-125
-150
15µ
10µ
Time (s)
Time (s)
Figure 41. Large signal response with VCC = 5 V
(TSC2012)
Figure 42. Large signal response with VCC = 2.7 V
3
3
150
50
125
2
100
25
50
25
Vsense
0
Vout
-25
Vcc = 5 V,
Vicm = 12 V,
Vsense = 45 mVpp
Cl = 100 pF,
T = 25°C
-1
-2
0
-50
-100
5µ
Vout
Vcc=2.7V,
Vicm=12V,
Vsense=40mVpp
Cl=100pF,
T=25°C
-1
-2
-125
-150
0
Vsense
0
-75
-3
-5µ
1
Vout (V)
Vout (V)
1
Vsense (mV)
75
10µ
15µ
-25
-3
-5µ
0
5µ
0
Vsense (mV)
2
10µ
-50
15µ
Time (s)
Time (s)
DS13057 - Rev 6
page 20/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 43. 12 V common mode step response recovery
5
Figure 44. 50 V common mode step response recovery
20
5
15
4
70
60
Vicm
Vout
3
10
-5
Vcc=5V,
Vicm edge 10ns,
Vsense=0V, Vref=2.5V
Rl=10kΩ , Cl=100pF,
T=25°C
0
-1
Vout (V)
1
0
10µ
20µ
0
-10
1
-1
-15
20µ
-50
-60
30µ
Figure 45. PSRR vs. frequency
Figure 46. CMRR vs. frequency
-120
Vcc=3.3V
Vcc=2.7V
-100
Vcc=2.7V
CMRR (dB)
PSRR (dB)
10µ
Time (s)
Vcc=5V
-60
-40
-80
-60
Vcc=5V
-40
Vicm=12V
Vripple=100mVpp
T=25°C
1k
-20
10k
100k
Frequency (Hz)
DS13057 - Rev 6
0
Time (s)
-100
0
100
-40
-70
-10µ
Vcc=3.3V
-20
-30
-2
30µ
-120
-80
-20
Vcc=5V,
Vicm edge 10ns,
Vsense=0V, Vref=2.5V
Rl=10kΩ, Cl=100pF,
T=25°C
-10
-20
-10µ
10
2
0
-2
30
20
Vicm (V)
Vout (V)
0
40
Vout
3
5
2
50
Vicm
Vicm (V)
4
1M
10M
0
100
Vicm=12V
Vripple=100mVpp
T=25°C
1k
10k
100k
1M
10M
Frequency (Hz)
page 21/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 47. Positive overvoltage recovery VCC = 2.7 V
100
200
3
Vcc=2.7V,
Vicm=12V,
CI=100pF
T=25°C
0
50
0
-1
-50
Vout
Vcc=2.7V,
Vicm=12V,
CI=100pF,
T=25°C
-2
-50
0
-100
-3µ
-2µ
-1µ
0
1µ
2µ
3µ
4µ
5µ
-2µ
-1µ
0
1µ
2µ
3µ
4µ
Time (s)
Figure 49. Overvoltage recovery vs. Vicm VCC = 5 V
Figure 50. Noise vs. frequency
Equivalent Input Voltage Noise (nV/√
√ Hz)
Over Voltage Recovery (µs)
1.5
Negative recovery time
1.3
1.0
0.8
0.5
Positive recovery time
0.3
0.0
-20
-10
0
10
Vicm (V)
DS13057 - Rev 6
20
30
5µ
6µ
10000
Vref = Vcc / 2
Vcc = 5 V,
T = 25 °C
Vout = 100 mV drop after Vsense edge
1.8
-150
-200
-3µ
Time (s)
2.0
-100
-3
6µ
Vsense (mV)
Vsense
100
Vout
Vsense
50
Vout (V)
1
0
150
Vsense (mV)
2
Vout (V)
Figure 48. Negative overvoltage recovery VCC = 2.7 V
40
5V
1000
3.3V
Lorem ipsum
2.7V
100
10
Vicm=Vcc/2
Tamb=25°C
1
100m
1
10
100
1k
10k
100k
1M
Frequency (Hz)
page 22/53
TSC2010, TSC2011, TSC2012
Typical characteristics
Figure 52. Output voltage vs. Vsense beyond the sense
operating
Figure 51. ON/OFF delay for shutdown mode
3
4.0
3.2
2
2.4
VSHDN
1
1.6
Vout
Vout (V)
1V/div
Vout phase reversal for Vsense
Vcc to power it.
Figure 54. Power supply when Vicm > Vcc
DS13057 - Rev 6
page 24/53
TSC2010, TSC2011, TSC2012
Theory of operation
In Figure 55. Input bias current vs. common mode voltage Vcc = 5 V, the current used to power the TSC2011
increases together with the Vicm voltage. The slope represents the internal common mode resistances. The most
part of the current is drawn by the pin In+ as we can see on the iibp curve of Figure 9. Input bias current vs.
temperature with VCC = 5 V the current is around 450 µA. Some of it being Vicm / (R4+R1) and some supplies the
input stage of the circuit, roughly 250 µA. On the In- pin 250 µA is drawn only.
So due to the architecture of the TSC2011, the current to be measured must be much larger than the input bias
current. In case of small current to measure the Iib current must be taken into account.
Figure 55. Input bias current vs. common mode voltage Vcc = 5 V
600
500
400
300
Iibp
Iib (µA)
200
100
Iibn
0
-100
-200
-300
-400
Vref=Vcc/2
Vsense=0V
Vcc=5V
-500
-600
-20
-10
0
10
20
30
40
50
60
70
Vicm (V)
•
Gnd < Vicm < Vcc
In this manner, the TSC2011 is only powered by the power supply Vcc, and the iib currents are very close to 0 µA
and do not have any impact on the current measurement.
•
- 20 V < Vicm < Gnd
The TSC2011 is fully functional in this range of common mode voltage and has also been characterized.
As the high positive common mode voltage, in this specific range, the TSC2011 is also powered by the input, see
Figure 56. Power supply when Vicm < Gnd.
DS13057 - Rev 6
page 25/53
TSC2010, TSC2011, TSC2012
Theory of operation
Figure 56. Power supply when Vicm < Gnd
Most part of the current is still due to the pin In+ as we can see on the iibp curve of Figure 9. Input bias current
vs. temperature with VCC = 5 V. The current is about - 300 µA, some of it being Vicm / (R4 + R1) and some other
supplies the circuit, roughly 250 µA. A small part of the current, coming from the common mode rail, is also due to
the input In– in order to power the TSC2011, in a range of - 100 µV.
•
Output common mode range
The TSC2011 output common mode voltage level can be set thanks to voltages applied on the Vref1 and Vref2
pins. These two pins allow the device to be set either in bidirectional or in unidirectional operation. The voltage
applied to those pins must not exceed the Vcc range. The different configurations are detailed in the section
Unidirectionnal/Bidirectionnal operation.
As depicted by the Figure 57. Vref powered by an external voltage source, Vref1 and Vref2 pins can be driven by
an external voltage source capable of sourcing/sinking a current following the equation below:
Iref =
Vicm − Vref
5kΩ + 275kΩ + 25kΩ
(1)
Figure 57. Vref powered by an external voltage source
DS13057 - Rev 6
page 26/53
TSC2010, TSC2011, TSC2012
Theory of operation
When the output common mode voltage is supplied by an external power supply, in order to improve the output
voltage measurement, it is recommended to measure the Vout differentially with respect to Vref voltage. It provides
a better CMRR measurement, better noise immunity and also a more accurate Vout voltage. A decoupling
capacitance of 1 nF minimum can be also added to better filter the power supply, and can also be used as a tank
capacitance in case an ADC is connected to this reference voltage.
DS13057 - Rev 6
page 27/53
TSC2010, TSC2011, TSC2012
Unidirectionnal / bidirectionnal operation
5.3
Unidirectionnal / bidirectionnal operation
•
Unidirectional operation
Unidirectional mode of operation allows the device to measure the current through a shunt resistor in one
direction only. The output reference can be ground or Vcc and can be set by using Vref1 and Vref2 pins for
adjustment.
•
Ground referenced
Figure 58. Output reference to ground
In this configuration Vref1 pin and Vref2 pin are connected together to the ground. The output common
mode voltage is then automatically set to GND when no current flows through the Rshunt resistance. This
configuration allows the full scale output in unidirectional mode. It allows a current to be measured as described in
Figure 58. Output reference to ground.
•
Vcc referenced
Figure 59. Output reference to Vcc
DS13057 - Rev 6
page 28/53
TSC2010, TSC2011, TSC2012
Unidirectionnal / bidirectionnal operation
In this configuration Vref1 pin and Vref2 pin are connected together to the Vcc power supply. The output common
mode voltage is then automatically set to Vcc voltage when no current flows through the Rshunt resistance.
This configuration allows the full scale output in unidirectional mode. It measures the current as described in
Figure 59. Output reference to Vcc.
•
Bidirectional operation
Bidirectional mode of operation allows the device to measure currents through a shunt resistor in two directions.
The output reference can be set anywhere within the power supply range. If the output common mode voltage
is set at mid-range, the full scale current measurement range is equal in both directions. This is achieved by
connecting one Vref pin to Vcc and the other Vref pin to Gnd as described by Figure 60. Split supply. It can be
done as well connecting both Vref pins to Vcc / 2 voltage as described by Figure 61. External supply. In case the
current measurement is not equal in both directions, user can set the output in a non-symmetrical configuration,
adjusting Vref according to the user's needs.
•
Split supply
Figure 60. Split supply
The great advantage of this configuration, is that the TSC2011 can be used in bidirectional mode with an
output common mode voltage set at the middle of scale, with an accuracy of 0.1%, without any added external
component or power supply. This configuration creates a midscale offset ratiometric to the power supply.
•
External
Figure 61. External supply
DS13057 - Rev 6
page 29/53
TSC2010, TSC2011, TSC2012
RSENSE selection
In this configuration, Vref1 pin and Vref2 pin are connected together to a reference voltage. The output common
mode voltage is then automatically set to this reference voltage value when no current flows through the Rshunt
resistance. This configuration adjusts the output offset as needed by the application. A DAC for calibration of the
analog chain could also be used.
5.4
RSENSE selection
The selection of the shunt resistor is a tradeoff between the dynamic range and power dissipation.
Generally, in high current sensing application, the main focus is to reduce as much as possible the power
dissipation (I²R) by choosing the smallest value of shunt. It could be quite easy if a full scale current to measure is
small.
In low current applications the Rsense value could be higher, to minimize the impact of the offset voltage on the
circuit. Due to input bias current of several µA, the TSC2011 cannot measure the current in the same range, when
the common mode voltage overpasses the power supply voltage (refer to section about theory of operation).
The tradeoff is mainly when a dynamic range of current to measure is large, meaning ability to measure with the
same shunt value from low current to high current. Generally, the current full scale (Imax-Imin) defines the shunt
value thanks to the full output voltage range, the gain of the TSC2011. The TSC2011 can work with a full scale
∆Vout = 100 mV to Vcc - 100 mV with maximum gain accuracy of 0.3%.
At first order, the full current range to measure through Rsense can be defined by equation 2, just by taking the
gain error and input offset voltage as inaccuracy parameters:
Isense_full_scale*Rsense =
Vcc − 200mV − 2 Vio
TSC_Gain 1 + Eg
(2)
The Vsense parameter is defined in the electrical characteristics following the equation 2.
Its purpose is to highlight that the product Rsense*TSC_gain is determined by the application, and that once one of
these two parameters is selected, the maximum value of the second one can be calculated.
•
If power dissipation in the shunt is the key point, RSense should be chosen as follows:
Rsense ≤
Pmax
Imax²
and then choosing the right gain. For example, for high current to sense, the TSC2012 can offer a gain of
100, in this manner a smaller shunt can be used and so limited power losses. However accuracy can be
lower.
•
5.5
Or choosing the product available on the shelf, and then size the shunt resistor value accordingly.
Input offset voltage drift overtemperature
The maximum input offset voltage drift overtemperature is defined as the offset variation related to the offset value
measured at 25 °C. The signal chain accuracy at 25 °C can be compensated during production at application
level. The maximum input voltage drift overtemperature enables the system designer to anticipate the effect of
temperature variations.
The maximum input voltage drift over temperature is computed using equation 3:
ΔVio
Vio T − Vio 25°C
ΔT = max
T − 25°C
(3)
Where T = -40 °C and 125 °C.
The TSC2011 datasheet maximum value is guaranteed by measurements on a representative sample size
ensuring a Cpk (process capability index) greater than 1.3.
DS13057 - Rev 6
page 30/53
TSC2010, TSC2011, TSC2012
Error calculation
5.6
Error calculation
The principal source of error, such as: input offset voltage, gain error, common mode rejection ration, are
described separately in the electrical characteristics. This chapter summarizes the most important error to take
into account during a design phase.
•
Input offset voltage error
The equation 2 depicts a first order error calculation just by taking into account the input offset voltage. In a
temperature environment, the deviation of the Vio and the error linked to the input offset on the output voltage can
be written as equation 4:
•
Vio Error = ± Vio ± Dvio/Dt *Gain
(4)
Gain error = Gain 1 + εgain
(5)
Gain error and shunt resistance accuracy
Rsense error = Gain 1 + εRsense
(6)
Where εgain is the gain error 0.3% max for the TSC2011.
Where εRsense is the shunt resistance error. Shunt resistors from 5 mΩ to 100 mΩ are available with 1%
accuracy or better.
•
CMR error
In the electrical characteristics, CMR is specified at one input common mode voltage. So in order to take into
consideration the variation of the input voltage offset depending the Vicm, the calculus must be done till this known
point. Let us get the Vicm = 12 V as reference point.
So the error on Vout due to a common mode voltage variation can be written as the equation 7:
•
Vicm − 12V *Gain
CMR error = ±
CMR
(7)
Output common mode error (Vocm)
This error can be taken into account when the output common mode voltage is set like suggested in the
Figure 62. Schematic for Vocm error, and so by using the internal divider bridge. Otherwise it is important to take
into consideration the error linked to the voltage source applied on the VRef1 pin and Vref2 pin.
Figure 62. Schematic for Vocm error
The divider bridge is made by two resistances of 50 kΩ given an output common mode voltage of:
Vref1 + Vref2
2
Due to a small mismatch of the internal resistance the error, on the output common mode voltage, can be
described as equation 8:
DS13057 - Rev 6
page 31/53
TSC2010, TSC2011, TSC2012
Error calculation
Vocm =
Vref1 + Vref2
. 1 + εAcc
2
(8)
Where εAcc is the accuracy referred to the output with a typical value of 0.1%.
•
Noise
The Section 4.1 expresses the noise referred to the input of the TSC2011. This device shows a 1/f noise until 10
kHz frequency. Above this limit the white noise density is 29 nV/ Hz , until the bandwidth of the TSC2011.
The noise can be then expressed as two terms, the former related to the 1/f noise and the latter due to the white
noise. If we consider that there is no additional filter on the TSC2011 and it is only bandwidth limited, it can be
considered that over the 750 kHz, there is an attenuation of the noise with a first order filtering. So the equivalent
noise bandwidth is 750kHz . π
2 .
The RMS value of the output noise is the integration of the spectral noise over the bandwidth of interest and can
be expressed as equation 9:
enRMS =
•
Total error
10000 29 . 10−9
∫0.1
f
10 . 103
2
750000 . π
2 29 . 10−9 2df *Gain
df + ∫
0.1
(9)
The maximum total error expected on the output of the device can be described as the sum of the different source
described just above. The total output accuracy can be written as equation 10.
Vouterr = Gain*Rsense* Iload εgain + εRsense + Gain . Vio + Gain .
Vocm εAcc + noise
Vicm − 12V
+
CMR
(10)
Iload is described in Figure 63. Input current and the output noise is described by the equation 9.
Note that the input bias currents are not taken into account in this section, as they are already integrated in the
Vsense. The Figure 63. Input current below depicts the current flowing from the source to the load when the input
common mode voltage is higher than the supply voltage.
Figure 63. Input current
From a calculation approach, when Vicm voltage is beyond Vcc, Iload must be considered as the sum of Isource and
Input bias current (Iib). Note that the input bias current on the pin – is largely lower and can be neglected.
The Figure 63. Input current also expresses that the TSC2011 cannot measure the current in the same order as
input bias current (several hundreds of µA).
The linearity is not taken into account in the error calculus as it represents 0.03% of error only and it is negligible.
Nevertheless, as the gain error has been calculated thanks to the best fit line approach, it gives the information
that the gain error can be relatively constant throughout the linear input range of the TSC2011.
The equation 10 has been described for a temperature of 25 °C. For sure with a temperature variation, Dvio/DT
error term must be added. And if the power supply is susceptible to change, the SVR parameter must also be
taken into account.
DS13057 - Rev 6
page 32/53
TSC2010, TSC2011, TSC2012
Shutdown mode
•
Example
Let us consider that the maximum total error can happen on the output of the TSC2011.
•
Use case:
–
Vcc = 5 V
–
Vicm = 24 V
–
Vocm = 2.5 V
–
–
Temperature = 25 °C
Iload = 5 A
–
Shunt 5 mΩ with 1% accuracy
Theoretically the expected output voltage should be Vout = Rshunt * Iload *60 + Vocm = 4 V.
From the equations above, all the error terms are detailed by using the maximum value of the electrical
characteristics (when available), in order to express as much as possible, the worst case condition. The % error
on output of the following table is expressed in reference of Vout – Vref, so in this typical example: 1.5 V.
Table 6. Gain error
Error source
Calculus
Output voltage error
% error on
output
Gain error
60*5 . 10−3*5*0.3%
4.5 mV
0.3%
30 mV
2%
22.7 mV
1.5%
2.5 mV
0.2%
1.98 mVRMS
0.4% (1)
Vio error
60*500µV
60*
CMRR error
Vocm error
Noise
Total
24V − 12V
90
10 20
2.5*0.1%
60* 29nV 10kHz* ln 10k − ln 0.1
Hz
+ 750kHz* π
2 − 0.1Hz
60 mV
+1.98 mVRMS
4.4%
1. The percentage is based on voltage peak value, which is 3 times RMS value.
So the maximum output voltage in the worst case condition at ambient temperature is 4.060 V + 1.98 mVRMS
instead of 4 V expected. This represents an error on the current reading about 4.4%. 1% more must be added
due to the shunt accuracy.
This calculus comes from all the maximum values and all the error terms which have been added to each
other, meaning that the chance to get 4.4% precision in the use case above is extremely low and on the whole
population, the error is largely smaller.
5.7
Shutdown mode
If the SHDN pin is driven between 0.7 x Vcc and Vcc the TSC2011 enters low power shutdown mode, drawing less
than 20 µA, over the Vcc and Vicm range. In SHDN mode the output is in HiZ state.
Although there is an internal current source of 500 nA on the SHDN pin, keeping a low state allowing the
TSC2011 to work without any voltage applied on the SHDN pin, it is strongly recommended to apply the dedicated
voltage on the SHDN pin to ensure the full functionality of the TSC2011, especially when fast common mode
variation appears.
The figure below depicts the architecture of the SHDN pin.
DS13057 - Rev 6
page 33/53
TSC2010, TSC2011, TSC2012
Stability
Figure 64. SHDN pin
•
•
5.8
With GND applied to SHDN pin the TSC2011 is in active mode
With Vcc applied to SHDN pin the TSC2011 is in shutdown mode
Stability
•
Driving switched capacitive loads
Some ADCs get their signal thanks to a sample and hold capacitor. If before a sampling this capacitance is fully
discharged, a fast current load can appear on the output of the TSC2011 during the sampling phase.
The scope probe in the figure below shows the output voltage of the TSC2011 excited by a 40 pF capacitor with a
3.3 Vpp signal at 50 kHz to simulate the sample and hold circuit of the ADC120.
8
7
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
Sample and hold
Vout
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
50kHz square signal of 3.3V amplitude
injected in the output through 40pF
-4µ
0
4µ
8µ
1000
900
800
700
600
500
400
300
200
100
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
Vout (mV)
Simulated Sample and Hold (V)
Figure 65. Capacitive load response at Vcc = 3.3 V
12µ
Time (s)
The ADC120 has a conversion rate of 50 ksps, which is perfect to sample and hold the output of the TSC2011
without any error.
The graph shows the behavior of the output of the TSC2011 under the worst case condition, as for example,
when there is an ADC120 channel change between two measurements.
If a single channel is used, for sure the change on the sample and hold capacitance are very small, and so the
recovery time is extremely low as described by the figure below.
DS13057 - Rev 6
page 34/53
TSC2010, TSC2011, TSC2012
Stability
Figure 66. Capacitive load response at Vcc = 3.3 V with a step of 100 mV
Simulated Sample and Hold (mV)
80
60
Sample and hold
40
20
Vout
0
-20
-40
-60
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
50kHz square signal of 100mV amplitude
injected in the output through 40pF
-80
-100
-4µ
0
4µ
8µ
1000
900
800
700
600
500
400
300
200
100
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
Vout (mV)
100
12µ
Time (s)
The effect of the ADC sampling and hold can be easily smoothed thanks to an RC filter. As suggested on the
schematic below. The capacitor of the external filter must be chosen much higher than the internal ADC capacitor,
in order to easily absorb the sudden voltage variation on the output due to the sampling and hold of the ADC. The
resistance must be chosen accordingly to the application speed of the system in order not to impact the whole
application. The main advantage of using an RC filter is to have an antialiasing system. For sure the used ADC
must have sample and hold conversion in accordance with the RC filter value, in order to let the output recover
before sampling.
Figure 67. RC filter when driving ADC
In the figure Figure 68. Capacitive load response at Vcc = 3.3 V with 720 kHz RC filter an Rs = 470 Ω resistance
and a Ct = 470 pF capacitance have been set. Given a low-pass filter of 720 kHz and a response time of roughly
660 ns.
In the figure Figure 69. Capacitive load response at Vcc = 3.3 V with 194 kHz RC filter an Rs = 820 Ω resistance
and a Ct = 1 nF capacitance have been set. Given a low-pass filter of 194 kHz and a response time of roughly 2.5
µs.
DS13057 - Rev 6
page 35/53
TSC2010, TSC2011, TSC2012
Stability
Vout
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
Rs=470Ω,Ct=470pF
50kHz square signal of 3.3V amplitude
injected in the output through 40pF
-4µ
0
4µ
8µ
8
7
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
Sample and hold
Vout
Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp
T=25°C,
Rs=820Ω,Ct=1nF
50kHz square signal of 3.3V amplitude
injected in the output through 40pF
-4µ
12µ
0
4µ
8µ
1000
900
800
700
600
500
400
300
200
100
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
Vout (mV)
Sample and hold
1000
900
800
700
600
500
400
300
200
100
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
Simulated Sample and Hold (V)
8
7
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
Figure 69. Capacitive load response at Vcc = 3.3 V with
194 kHz RC filter
Vout (mV)
Simulated Sample and Hold (V)
Figure 68. Capacitive load response at Vcc = 3.3 V with
720 kHz RC filter
12µ
Time (s)
Time (s)
The value of the added external capacitor must be taken into account. Indeed, if this one is chosen with an
excessive value and the serial resistance with a too small value, the risk of instability on the output of the
TSC2011 is high.
•
Driving large capacitive Cload
Increasing the load capacitance produces gain peaking in the frequency response, with an overshoot and ringing
in the step response.
The figure below, shows the serial resistors that must be added to the output, to make a system stable. The
chosen criteria ensures the stability of the system and it is an overshoot lower than 24%.
Figure 70. Stability criteria with a serial resistor at VCC = 5 V
500
Vcc=5V, Vicm=0V,
Vref=Vcc/2,
T=25°C,
Serial Resistor (Ohm)
400
300
Stable
200
100
Unstable
0
0.1
1
10
100
Capacitive Load (nF)
DS13057 - Rev 6
page 36/53
TSC2010, TSC2011, TSC2012
Power supply recommendation
5.9
Power supply recommendation
In order to decouple correctly the TSC2011, a 100 nF bypass capacitor can be placed between Vcc and Gnd. This
capacitor must be placed as closer as possible to the supply pins. The figure below shows a start-up time with a
decoupling capacitance of 100 nF.
Figure 71. Start-up time with a decoupling capacitance of 100 nF
6
5
Vcc
4
Voltage (V)
3
2
Vout
1
0
Vref=0V
Vsense=20mV,
Vcc=5V, Vicm=12V,
RI=10k Ω, Cl=10pF connected to Vcc-,
T=25°C
-1
-2
-3
-200µ
0
200µ
400µ
600µ
800µ
Time (s)
Vref pin is used to fix the output common mode voltage and it is driven by a low impedance voltage source and
can be decoupled thanks to a 10 nF bypass capacitor.
A greater bypass capacitor added on Vcc pin and Vref pin helps to enhance CMRR and PSRR performance.
5.10
PCB layout recommendations
The layout of the PCB tracks connected to the current sensing, load and power supply is very important. It is a
good practice to use short and wide PCB traces to minimize voltage drops and parasitic inductance.
When a shunt resistance, lower than 1 Ω, is used, a 4-wire connection technique should be used to sense
the current as described in the schematic below. This technique separates pairs of current carrying and voltagesensing electrodes to make more accurate measurements by eliminating the lead and contact resistance from the
measurement.
The track connected to the input pin of the TSC2011 has to be considered as a differential pair, it must have
the same length and width, and ideally placed on the same PCB plane, and above all must be routed as far as
possible from noisy source. As this track carries the input bias current, in a range of hundreds of µA, it can be
designed small but always by taking care of its resistivity. Any via in these input tracks are non-recommended to
avoid any parasitic resistance in this path.
To minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top
layer ground planes together in many locations is often used.
A ground plane generally helps to reduce EMI, that is why a multilayer PCB use is suggested as well as the
ground planes as a shield to protect the internal track. In this case, the digital from the analog ground must be
separated and any ground loop must be avoided. Loop area or antenna must be reduced to minimize EMI impact.
The Figure 72. Recommended layout suggests a possible routing for the TSC2011, in order to minimum parasitic
effect.
DS13057 - Rev 6
page 37/53
TSC2010, TSC2011, TSC2012
EMI rejection ration (EMIRR)
Figure 72. Recommended layout
5.11
EMI rejection ration (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of current sensing
device. An adverse effect that is common to many current sensing is a change in the offset voltage as a result
of RF signal rectification. A first order internal low pass filter is included on the input of the TSC2011 to minimize
susceptibility to EMIRR. Figure 73 shows the EMIRR on pin IN+, Figure 74 shows the EMIRR on pin IN- of the
TSC2011 measured from 400 MHz up to 2.4 GHz.
Figure 73. EMIRR on pin+
Figure 74. EMIRR on pin-
100
100
EMIRR In-(dB)
120
EMIRR In+(dB)
120
80
60
60
40
40
20
20
Vcc=5V, T=25°C
Prf=-10dBm
Vcc=5V, T=25°C
Prf=-10dBm
0
400
80
600
800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
0
400
600
800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
Figure 75 shows the EMIRR on pin IN+, Figure 76 shows the EMIRR on pin IN- of the TSC2010 measured from
10 MHz up to 2.4 GHz.
DS13057 - Rev 6
page 38/53
TSC2010, TSC2011, TSC2012
EMI rejection ration (EMIRR)
Figure 75. EMIRR on pin+ (TSC2010)
Figure 76. EMIRR on pin- (TSC2010)
100
100
80
80
EMIRR In- (dB)
120
EMIRR In+ (dB)
120
60
40
40
20
20
Vcc = 5 V, T = 25°C
Prf = 10 dBm
0
60
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
DS13057 - Rev 6
Vcc = 5 V, T = 25°C
Prf = 10 dBm
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
Frequency (MHz)
page 39/53
TSC2010, TSC2011, TSC2012
Overload recovery
5.12
Overload recovery
Overload recovery is defined as the time required for the current sensing output to recover from a saturated state
to a linear state.
The saturation state occurs when the output voltage gets very close to rails in the application. It results from an
excessive input voltage.
When the output of the TSC2011 enters saturation state, less than 1 µs is needed to get back to a linear state as
shown by Figure 77 and Figure 78.
Figure 47 and Figure 48 show the overvoltage recovery for a VCC = 2.7 V.
Figure 77. Negative overvoltage recovery VCC = ± 2.5 V
DS13057 - Rev 6
Figure 78. Positive overvoltage recovery VCC = ± 2.5 V
page 40/53
TSC2010, TSC2011, TSC2012
Application examples
5.13
Application examples
5.13.1
H-Bridge motor control
The H-Bridge topology is very popular in motor control, DC-DC converters, LED lighting control and other
bidirectional loads from a single supply potential.
The TSC2011 provides a feedback control system about current but also detects overload conditions.
The Figure 79. H-Bridge application describes a typical schematic using the TSC2011 in a motor control
application. A 20 mΩ shunt resistance in series with the motor monitors a measurable voltage drop representing
the load current, and the TSC2011 amplifies the Vsense in order to give some information about the current flowing
into the motor in real time. These information are then digitalizing by the 12-bit ADC (ADC120).
Figure 79. H-Bridge application
General overview:
To make the motor rotation occur, the NMOS H1, H2, L1, L2 are driven by a H-Bridge quad power MOSFET
driver. We have to consider that the current flows from the 12 V to the GND, through H1 NMOS and L2 NMOS. A
PWM is applied on the NMOS L2 in order to control the current and thus the speed of the motor.
By PWM, the average voltage applied on the motor is controlled. H1 remains always ON and the PWM is applied
on L2. When L2 is turned off, H2 must be turned ON, for freewheeling, allowing the discharge of the motor
inductance current. This phenomenon generates a fast input common mode voltage transition on the TSC2011,
from 0 V to 12 V.
Thanks to a good recovery time due to fast input common mode change, the TSC2011 follows the current flowing
into the motor as depicted by the scope probe in Figure 80. TSC2011 H-Bridge application.
The black curve represents the fast Vicm variation step of 12 V in 500 ns when the freewheeling is activated. The
blue curve represents the current flowing into the motor measured with a current probe.
The red curve represents the output voltage - 1.35 V (Vref voltage) of the TSC2011 probe after the RC filter.
The RC filter, used to drive the ADC120, smooths a bit the output signal and adds a small constant time, in the
range of 1 µs.
DS13057 - Rev 6
page 41/53
TSC2010, TSC2011, TSC2012
Application examples
Figure 80. TSC2011 H-Bridge application
1.0
1.20
0.96
Vicm variation from 0V to 12V
0.6
0.72
0.4
0.48
0.2
0.24
Vout
0.0
0.00
-0.2
-0.24
Current flowing into the motor
-0.48
-0.4
-50µ
Vout - Vref (V)
input current (A)
0.8
-40µ
-30µ
-20µ
-10µ
0
10µ
20µ
30µ
40µ
50µ
Time (s)
After a fast variation of the input common mode, the TSC2011 needs less than 5 µs to recover its normal
behavior.
5.13.2
Solenoid valve
In automotive applications, the automatic transmission relies on bands and clutches to change gears, and the
only way they can be applied is by fluid pressure. The transmission solenoid is responsible for opening or closing
valves in the valve body to allow transmission fluid to enter, at which point the fluid can pressurize the clutches
and bands. Solenoids consist of a spring loaded plunger wrapped with a coil of wire, and it is generally driven
thanks to a MOS transistor.
In the schematic below the TSC2011 is used in mono directional mode. When the MOS is ON, the current can
flow through the solenoid and actuate this one. The input common mode is high in this case.
When the MOS is turned OFF, as the current stored into the solenoid cannot stop instantaneously, the diode turns
ON allowing a freewheeling to discharge the solenoid resulting in a common mode one diode voltage drop below
ground.
Thanks to its large input common mode range, the TSC2011 can be used for such applications depicted in figure
below.
In order not to saturate the output when no current is flowing into Rsense, a small voltage on Vref has to be applied.
DS13057 - Rev 6
page 42/53
TSC2010, TSC2011, TSC2012
Application examples
Figure 81. Solenoid valve application
DS13057 - Rev 6
page 43/53
TSC2010, TSC2011, TSC2012
Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
DS13057 - Rev 6
page 44/53
TSC2010, TSC2011, TSC2012
SO8 package information
6.1
SO8 package information
Figure 82. SO8 package outline
Table 7. SO-8 mechanical data
Dim.
mm
Min.
Inches
Typ.
A
Min.
Typ.
1.75
0.25
Max.
0.069
A1
0.1
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.01
D
4.8
4.9
5
0.189
0.193
0.197
E
5.8
6
6.2
0.228
0.236
0.244
E1
3.8
3.9
4
0.15
0.154
0.157
e
0.004
0.01
0.049
1.27
0.05
h
0.25
0.5
0.01
0.02
L
0.4
1.27
0.016
0.05
L1
k
ccc
DS13057 - Rev 6
Max.
1.04
0
0.04
8°
0.1
1°
8°
0.004
page 45/53
TSC2010, TSC2011, TSC2012
MiniSO8 package information
6.2
MiniSO8 package information
Figure 83. MiniSO8 package outline
Table 8. MiniSO8 mechanical data
Dim.
Millimeters
Min.
Inches
Typ.
A
Min.
Typ.
1.1
A1
0
A2
0.75
b
Max.
0.043
0.15
0
0.95
0.03
0.22
0.4
0.009
0.016
c
0.08
0.23
0.003
0.009
D
2.8
3
3.2
0.11
0.118
0.126
E
4.65
4.9
5.15
0.183
0.193
0.203
E1
2.8
3
3.1
0.11
0.118
0.122
e
L
0.85
0.65
0.4
0.6
0.006
0.033
0.8
0.016
0.024
L1
0.95
0.037
0.25
0.01
ccc
0°
0.037
0.026
L2
k
DS13057 - Rev 6
Max.
8°
0.1
0°
0.031
8°
0.004
page 46/53
TSC2010, TSC2011, TSC2012
Ordering information
7
Ordering information
Table 9. Order codes
Order code
Gain (V/V)
TSC2010IDT
TSC2010IYDT (1)
TSC2011IDT
TSC2011IYDT (1)
TSC2012IDT
TSC2012IYDT (1)
TSC2010IST
TSC2010IYST (1)
TSC2011IST
TSC2011IYST
(1)
TSC2012IST
TSC2012IYST
(1)
Package
Packaging
TSC2010
20
60
TSC2010Y
TSC2011
SO8
TSC2011Y
TSC2012
100
Tape and reel
20
60
100
Marking
TSC2012Y
O117
O120
MiniSO8
O118
O121
O119
O122
1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 &
Q002 or equivalent.
DS13057 - Rev 6
page 47/53
TSC2010, TSC2011, TSC2012
Revision history
Table 10. Document revision history
Date
Revision
11-Sep-2019
1
Changes
Initial release.
Added new part number TSC2012, Figure 25. Gain vs. frequency (VCC = 5 V),
Figure 27. Gain vs. different capacitive load (TSC2012), Figure 29. Bandwidth vs.
30-Jan-2020
2
input common mode (TSC2012) and Figure 32. Small signal response with VCC = 5 V
(TSC2012).
Updated description on the cover page, Figure 30. Overshoot vs. capacitive load,
Figure 42. Overvoltage recovery vs. Vicm, VCC = 5 V, Table 4. Electrical characteristics
VCC = 2.7 V, Vicm = 12 V, T = 25 °C (unless otherwise specified)., Table 5. Electrical
characteristics (VCC = 5 V, Vicm = 12 V, T = 25 °C unless otherwise specified) and
Table 9. Order codes.
Added new part number TSC2010, Figure 75 and Figure 76.
Updated:
10-Apr-2020
3
- Features and description on the cover page
- |Vsense|, G, BW and SR conditions in Table 4 and Table 5.
- Section 4.1 Typical characteristics.
- Table 9. Order codes.
DS13057 - Rev 6
05-Aug-2020
4
Updated Figure 77 and Figure 78.
06-May-2021
5
Updated Section 5.13.1 H-Bridge motor control.
15-Sep-2021
6
Updated Figure 33. Bandwidth vs. input common mode (TSC2012).
page 48/53
TSC2010, TSC2011, TSC2012
Contents
Contents
1
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
4
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.1
5
6
7
Typical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2
Theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3
Unidirectionnal / bidirectionnal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4
RSENSE selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.5
Input offset voltage drift overtemperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.6
Error calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.7
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.8
Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.9
Power supply recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.10
PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.11
EMI rejection ration (EMIRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.12
Overload recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.13
Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.13.1
H-Bridge motor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.13.2
Solenoid valve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
6.1
SOT23-3L package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2
MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
DS13057 - Rev 6
page 49/53
TSC2010, TSC2011, TSC2012
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics Vcc = 2.7 V, Vicm = 12 V, T = 25 °C (unless otherwise specified). .
Electrical characteristics (Vcc = 5 V, Vicm = 12 V, T = 25 °C unless otherwise specified). . .
Gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MiniSO8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS13057 - Rev 6
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. 3
. 4
. 4
. 5
. 8
33
45
46
47
48
page 50/53
TSC2010, TSC2011, TSC2012
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
DS13057 - Rev 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . .
Supply current vs. input common mode . . . . . . . . . . . . . . . . . . . .
Supply current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply current vs. input common mode with active shutdown mode
Input bias current vs. input common mode with shutdown active . . .
Input bias current vs. temperature VCC = 2.7 V . . . . . . . . . . . . . . .
Input bias current vs. temperature with VCC = 5 V . . . . . . . . . . . . .
Input offset voltage vs. temperature. . . . . . . . . . . . . . . . . . . . . . .
Input offset voltage vs. input common mode with VCC = 2.7 V . . . . .
Input offset voltage vs. input common mode with VCC = 5 V . . . . . .
Input offset voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . .
Output current vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . .
Output current vs. temperature with VCC = 5 V . . . . . . . . . . . . . . .
Output current vs. temperature with VCC = 2.7 V . . . . . . . . . . . . . .
Voh and Vol vs. input common mode voltage with VCC = 5 V . . . . . .
(Output voltage + Vref) vs. Vsense unidirectionnal with VCC = 5 V . .
(Output voltage + Vref) vs. Vsense bidirectionnal with VCC = 5 V . . . .
Output rail linearity vs. load with VCC = 5 V. . . . . . . . . . . . . . . . . .
Linearity vs. Vsense with VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . .
Linearity vs. Vsense and temperature . . . . . . . . . . . . . . . . . . . . . .
Gain error vs. input common mode . . . . . . . . . . . . . . . . . . . . . . .
Gain error vs. input common mode and temperature . . . . . . . . . . .
Load regulation with VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain vs. frequency VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain vs. frequency different capacitive load . . . . . . . . . . . . . . . . .
Gain vs. frequency different capacitive load (TSC2010) . . . . . . . . .
Gain vs. frequency different capacitive load (TSC2012) . . . . . . . . .
Bandwidth vs. input common mode . . . . . . . . . . . . . . . . . . . . . . .
Bandwidth vs. input common mode (TSC2010). . . . . . . . . . . . . . .
Bandwidth vs. input common mode (TSC2012). . . . . . . . . . . . . . .
Overshoot vs. capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . .
Small signal response with VCC = 5 V . . . . . . . . . . . . . . . . . . . . .
Small signal response with VCC = 5 V (TSC2010) . . . . . . . . . . . . .
Small signal response with VCC = 5 V (TSC2012) . . . . . . . . . . . . .
Small signal response with VCC= 2.7 V . . . . . . . . . . . . . . . . . . . .
Large signal response with VCC = 5 V . . . . . . . . . . . . . . . . . . . . .
Large signal response with VCC = 5 V (TSC2010) . . . . . . . . . . . . .
Large signal response with VCC = 5 V (TSC2012) . . . . . . . . . . . . .
Large signal response with VCC = 2.7 V . . . . . . . . . . . . . . . . . . . .
12 V common mode step response recovery . . . . . . . . . . . . . . . .
50 V common mode step response recovery . . . . . . . . . . . . . . . .
PSRR vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMRR vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive overvoltage recovery VCC = 2.7 V . . . . . . . . . . . . . . . . . .
Negative overvoltage recovery VCC = 2.7 V . . . . . . . . . . . . . . . . .
Overvoltage recovery vs. Vicm VCC = 5 V . . . . . . . . . . . . . . . . . . .
Noise vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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page 51/53
TSC2010, TSC2011, TSC2012
List of figures
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
DS13057 - Rev 6
ON/OFF delay for shutdown mode . . . . . . . . . . . . . . . . . . . .
Output voltage vs. Vsense beyond the sense operating . . . . . .
Power up time delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power supply when Vicm > Vcc . . . . . . . . . . . . . . . . . . . . . . .
Input bias current vs. common mode voltage Vcc = 5 V . . . . . .
Power supply when Vicm < Gnd . . . . . . . . . . . . . . . . . . . . . .
Vref powered by an external voltage source . . . . . . . . . . . . . .
Output reference to ground . . . . . . . . . . . . . . . . . . . . . . . . .
Output reference to Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Split supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic for Vocm error . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SHDN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitive load response at Vcc = 3.3 V. . . . . . . . . . . . . . . . .
Capacitive load response at Vcc = 3.3 V with a step of 100 mV .
RC filter when driving ADC. . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitive load response at Vcc = 3.3 V with 720 kHz RC filter .
Capacitive load response at Vcc = 3.3 V with 194 kHz RC filter .
Stability criteria with a serial resistor at VCC = 5 V . . . . . . . . . .
Start-up time with a decoupling capacitance of 100 nF. . . . . . .
Recommended layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIRR on pin+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIRR on pin- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIRR on pin+ (TSC2010) . . . . . . . . . . . . . . . . . . . . . . . . .
EMIRR on pin- (TSC2010) . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative overvoltage recovery VCC = ± 2.5 V . . . . . . . . . . . . .
Positive overvoltage recovery VCC = ± 2.5 V. . . . . . . . . . . . . .
H-Bridge application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSC2011 H-Bridge application . . . . . . . . . . . . . . . . . . . . . . .
Solenoid valve application . . . . . . . . . . . . . . . . . . . . . . . . . .
SO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MiniSO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . .
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page 52/53
TSC2010, TSC2011, TSC2012
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service
names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13057 - Rev 6
page 53/53
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