TSX631, TSX632, TSX634,
TSX631A, TSX632A, TSX634A
Micropower (45 μA, 200 kHz) rail-to-rail 16 V CMOS
operational amplifiers
Datasheet - production data
Related products
Single
• See TSX56x or TSX92x series for higher gain
bandwidth products (900 kHz or 10 MHz)
Applications
SOT23-5
• Industrial signal conditioning
• Automotive signal conditioning
Dual
• Active filtering
• Medical instrumentation
DFN8 2x2
• High impedance sensors
MiniSO-8
Description
Quad
QFN16 3x3
The TSX63x and TSX63xA series of operational
amplifiers offer low voltage operation and rail-torail input and output. TSX631 is the single
version, TSX632 the dual version and TSX634
the quad version, with pinouts compatible with
industry standards.
TSSOP14
The TSX63x and TSX63xA series offer a 200 kHz
gain bandwidth product while consuming 60 µA
maximum at 16 V.
Features
• Low power consumption: 60 µA max at 16 V
• Supply voltage: 3.3 V to 16 V
The devices are housed in the tiniest industrial
packages.
These features make the TSX63x and TSX63xA
family ideal for sensor interfaces and industrial
signal conditioning. The wide temperature range
and high ESD tolerance ease the use in harsh
automotive applications.
• Rail-to-rail input and output
• Gain bandwidth product: 200 kHz typ
• Low offset voltage:
– 500 µV max for “A” version
– 1 mV max for standard version
Table 1. Device summary
• Low input bias current: 1 pA typ
• Automotive qualification
Benefits
• Power savings in power-conscious
applications
Op-amp
version
Standard Vio
Enhanced Vio
Single
TSX631
TSX631A
Dual
TSX632
TSX632A
Quad
TSX634
TSX634A
• Easy interfacing with high impedance sensors
March 2013
This is information on a product in full production.
DocID024293 Rev 1
1/31
www.st.com
31
Contents
TSX63x, TSX63xA
Contents
1
Package pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 4
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
4.1
Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2
Rail-to-rail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3
Input offset voltage drift over temperature . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4
Long term input offset voltage drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5
High values of input differential voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6
PCB layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7
Macromodel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1
SOT23-5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2
DFN8 2x2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3
MiniSO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4
QFN16 3x3 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.5
TSSOP14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
DocID024293 Rev 1
TSX63x, TSX63xA
Package pin connections
Figure 1. Pin connections for each package (top view)
Single
SOT23-5 (TSX631)
Dual
287
9&&
287
9&&
,1
287
,1
287
,1
,1
,1
,1
9&&
,1
9&&
,1
DFN8 2x2 (TSX632)
Mini-SO8 (TSX632)
,1
287
287
,1
Quad
,1
9&&
9&&
1&
1&
,1
,1
,1
287
287
,1
,1
1
Package pin connections
QFN16 3x3 (TSX634)
DocID024293 Rev 1
TSSOP14 (TSX634)
3/31
Absolute maximum ratings and operating conditions
2
TSX63x, TSX63xA
Absolute maximum ratings and operating conditions
Table 2. Absolute maximum ratings (AMR)
Symbol
VCC
Vid
Vin
Iin
Tstg
Rthja
Rthjc
Tj
Parameter
Supply voltage
(2)
±VCC
V
(3)
VCC- - 0.2 to VCC++ 0.2
(4)
10
mA
-65 to +150
°C
Input voltage
Storage temperature
Thermal resistance junction to ambient
SOT23-5
DFN8 2x2
MiniSO-8
QFN16 3x3
TSSOP14
(5)(6)
250
120
190
80
100
°C/W
Thermal resistance junction to case
DFN8 2x2
QFN16 3x3
33
30
Maximum junction temperature
160
°C
4
kV
200
V
1.3
kV
200
mA
HBM: human body
ESD
Unit
18
Differential input voltage
Input current
Value
(1)
MM: machine
model(7)
model(8)
CDM: charged device
model(9)
Latch-up immunity
1. All voltage values, except the differential voltage are with respect to network ground terminal.
2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal. See
Section 4.5 for precautions of using the TSX631 with high differential input voltage.
3. VCC-Vin must not exceed 18 V, Vin must not exceed 18 V.
4. Input current must be limited by a resistor in series with the inputs.
5. Short-circuits can cause excessive heating and destructive dissipation.
6. Rth are typical values.
7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for
all couples of pin combinations with other pins floating.
8. Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two
pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin
combinations with other pins floating.
9. Charged device model: all pins plus package are charged together to the specified voltage and then
discharged directly to the ground.
Table 3. Operating conditions
Symbol
4/31
Parameter
VCC
Supply voltage
Vicm
Common mode input voltage range
Toper
Operating free air temperature range
Value
3.3 to 16
DocID024293 Rev 1
VCC- - 0.1 to VCC+ + 0.1
-40 to +125
Unit
V
°C
TSX63x, TSX63xA
3
Electrical characteristics
Electrical characteristics
Table 4. Electrical characteristics at VCC+ = +3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and
RL= 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
Vio
Vio
Offset voltage
Offset voltage, high common
mode (Vicm=VCC, RL > 1 MΩ)
ΔVio/ΔT Input offset voltage drift
Iio
Iib
Input offset current (Vout = VCC/2)
Input bias current (Vout = VCC/2)
TSX63xA, T = 25 °C
700
TSX63xA, -40°C < T < 125 °C
1500
TSX63x, T = 25 °C
1.6
TSX63x, -40°C < T < 125 °C
2.4
T = 25 °C
4
-40°C < T < 125 °C
5
-40°C < T < 125 °C(1)
1
T = 25 °C
1
(2)
200(2)
-40°C < T < 125 °C
T = 25 °C
1
mV
μV/°C
8
100
μV
100(2)
pA
200(2)
-40°C < T < 125 °C
RIN
Input resistance
1
TΩ
CIN
Input capacitance
5
pF
T = 25 °C
65
CMR1
Common mode rejection ratio
CMR = 20 log (ΔVicm/ΔVio)
(Vicm = -0.1 V to VCC-1.65 V,
Vout = VCC/2, RL > 1 MΩs)
-40°C < T < 125 °C
62
T = 25 °C
59
CMR2
Common mode rejection ratio
CMR = 20 log (ΔVicm/ΔVio)
(Vicm = -0.1 V to VCC+0.1 V,
Vout = VCC/2, RL > 1 MΩ)
-40°C < T < 125 °C
55
Large signal voltage gain
(Vout = 0.5 V to (VCC - 0.5 V),
RL > 1 MΩ)
T = 25 °C
100
Avd
-40°C < T < 125°C
90
VOH
High level output voltage
Vid = +1 V, VOH = VCC-Vout
RL = 10 kΩ, T = 25 °C
70
RL = 10 kΩ, -40 °C < T < 125 °C
100
VOL
Low level output voltage
Vid = -1 V,
RL = 10 kΩ, T = 25 °C
70
RL = 10 kΩ, -40°C < T < 125 °C
100
Isink (Vout = VCC)
Iout
Isource (Vout = 0 V)
ICC
Supply current
(per operator, Vout = VCC/2,
RL > 1 MΩ)
79
74
dB
T = 25 °C
4.3
-40°C < T < 125 °C
2.5
T = 25 °C
3.3
-40°C < T < 125 °C
2.5
T = 25 °C
-40°C < T < 125 °C
DocID024293 Rev 1
110
mV
5.3
mA
4.3
45
60
60
µA
5/31
Electrical characteristics
TSX63x, TSX63xA
Table 4. Electrical characteristics at VCC+ = +3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and
RL= 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
160
200
Max.
Unit
AC performance
GBP
Gain bandwidth product
Fu
Unity gain frequency
Φm
Phase margin
Gm
Gain margin
SR
Slew rate
∫ en
Low-frequency peak-to-peak
input noise
en
Equivalent input noise voltage
RL = 100 kΩ, CL = 100 pF
160
kHz
55
degrees
9
dB
RL = 100 kΩ, CL = 100 pF,
Vout = 0.5 V to VCC - 0.5V
0.12
V/μs
Bandwidth: f = 0.1 to 10 Hz
5
µVpp
60
nV
-----------Hz
0.005
%
f = 1 kHz
f = 10 kHz
THD+N Total harmonic distortion + noise
Follower configuration,
fin = 1 kHz, RL = 100 kΩ,
Vicm = 0.9V, BW = 22 kHz,
Vout = 1 Vpp
1. See Chapter 4.3: Input offset voltage drift over temperature on page 18
2. Guaranteed by design
6/31
DocID024293 Rev 1
TSX63x, TSX63xA
Electrical characteristics
Table 5. Electrical characteristics at VCC+ = +5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and
RL= 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
Vio
Vio
Offset voltage
Offset voltage, high common
mode (Vicm=VCC, RL > 1 MΩ)
ΔVio/ΔT Input offset voltage drift
ΔVio
Iio
Iib
TSX63xA, T = 25 °C
700
TSX63xA, -40°C < T < 125 °C
1500
TSX63x, T = 25 °C
1.6
TSX63x, -40°C < T < 125 °C
2.4
T = 25 °C
4
-40°C < T < 125 °C
-40°C < T < 125
mV
5
°C(1)
1
Long term input offset voltage
drift
T = 25 °C(2)
17
Input offset current
(Vout = VCC/2)
T = 25 °C
1
Input bias current (Vout = VCC/2)
μV
8
nV
month
---------------------------
100(3)
200(3)
-40°C < T < 125 °C
T = 25 °C
1
μV/°C
100(3)
pA
200(3)
-40°C < T < 125 °C
RIN
Input resistance
1
TΩ
CIN
Input capacitance
5
pF
T = 25 °C
65
CMR1
Common mode rejection ratio
CMR = 20 log (ΔVicm/ΔVio)
(Vicm = -0.1 V to VCC-1.65 V,
Vout = VCC/2, RL > 1 MΩ)
-40°C < T < 125 °C
62
T = 25 °C
62
CMR2
Common mode rejection ratio
CMR = 20 log (ΔVicm/ΔVio)
(Vicm = -0.1 V to VCC+0.1 V,
Vout = VCC/2, RL > 1 MΩ)
-40°C < T < 125 °C
58
Large signal voltage gain
(Vout = 0.5 V to (VCC - 0.5 V),
RL > 1 MΩ)
T = 25 °C
100
Avd
-40°C < T < 125 °C
90
VOH
High level output voltage
Vid = +1 V, VOH = VCC-Vout
RL = 10 kΩ, T=25 °C
70
RL = 10 kΩ, -40°C < T < 125 °C
100
VOL
Low level output voltage
Vid = -1 V,
RL = 10 kΩ, T = 25 °C
70
RL = 10 kΩ, -40°C < T < 125 °C
100
Isink (Vout = VCC)
Iout
Isource (Vout = 0 V)
ICC
Supply current
(per operator, Vout = VCC/2,
RL > 1 MΩ)
79
77
dB
T = 25 °C
11
-40°C < T < 125 °C
8
T = 25 °C
9
-40°C < T < 125 °C
7
T = 25 °C
-40°C < T < 125 °C
DocID024293 Rev 1
110
mV
14
mA
12
45
60
60
µA
7/31
Electrical characteristics
TSX63x, TSX63xA
Table 5. Electrical characteristics at VCC+ = +5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and
RL= 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
160
200
Max.
Unit
AC performance
GBP
Gain bandwidth product
Fu
Unity gain frequency
Φm
Phase margin
Gm
Gain margin
SR
Slew rate
∫ en
Low-frequency peak-to-peak
input noise
en
Equivalent input noise voltage
RL = 100 kΩ, CL = 100 pF
160
kHz
55
degrees
9
dB
RL = 100 kΩ, CL = 100 pF,
Vout = 0.5 V to VCC - 0.5V
0.12
V/μs
Bandwidth: f = 0.1 to 10 Hz
5
µVpp
60
nV
-----------Hz
0.005
%
f = 1 kHz
f = 10 kHz
Follower configuration,
f = 1 kHz, RL = 100 kΩ,
THD+N Total harmonic distortion + noise in
Vicm = 2.5V, BW = 22 kHz,
Vout = 1 Vpp
1. See Chapter 4.3: Input offset voltage drift over temperature on page 18
2. Typical value is based on the Vio drift observed after 1000h at 125°C extrapolated to 25°C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. See
Chapter 4.4: Long term input offset voltage drift on page 19.
3. Guaranteed by design
8/31
DocID024293 Rev 1
TSX63x, TSX63xA
Electrical characteristics
Table 6. Electrical characteristics at VCC+ = +10 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and
RL=10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
Vio
Offset voltage
TSX63xA, T = 25 °C
500
TSX63xA, -40°C < T < 125 °C
1300
TSX63x, T = 25 °C
1
TSX63x, -40°C < T < 125 °C
Vio
Offset voltage, high common
mode (Vicm=VCC, RL > 1 MΩ)
ΔVio/ΔT Input offset voltage drift
ΔVio
Iio
Iib
Long term input offset voltage
drift
Input offset current (Vout = VCC/2)
Input bias current (Vout = VCC/2)
1.8
T = 25 °C
4
-40°C < T < 125 °C
-40°C < T < 125
μV
mV
5
°C(1)
1
T = 25 °C(2)
8
nV
month
---------------------------
180
T = 25 °C
1
100(3)
200(3)
-40°C < T < 125 °C
T = 25 °C
1
μV/°C
100(3)
pA
200(3)
-40°C < T < 125 °C
RIN
Input resistance
1
TΩ
CIN
Input capacitance
5
pF
T = 25 °C
71
-40°C < T < 125 °C
68
84
CMR1
Common mode rejection ratio
CMR = 20 log (ΔVicm/ΔVio)
(Vicm = -0.1 V to VCC-1.65 V,
Vout = VCC/2, RL > 1 MΩ)
T = 25 °C
69
CMR2
Common mode rejection ratio
CMR = 20 log (ΔVicm/ΔVio)
(Vicm = -0.1 V to VCC+0.1 V,
Vout = VCC/2, RL > 1 MΩ)
-40°C < T < 125 °C
66
Large signal voltage gain
(Vout = 0.5 V to (VCC - 0.5 V),
RL > 1 MΩ)
T = 25 °C
100
Avd
-40°C < T < 125 °C
90
VOH
High level output voltage
Vid = +1 V, VOH = VCC-Vout
RL = 10 kΩ, T = 25 °C
70
RL = 10 kΩ, -40°C < T < 125 °C
100
VOL
Low level output voltage
Vid = -1 V,
RL = 10 kΩ, T = 25 °C
70
RL = 10 kΩ, -40°C < T < 125 °C
100
Isink (Vout = VCC)
Iout
Isource (Vout = 0 V)
ICC
Supply current
(per operator, Vout = VCC/2,
RL > 1 MΩ)
82
dB
T = 25 °C
35
-40°C < T < 125 °C
25
T = 25 °C
30
-40°C < T < 125 °C
20
T = 25 °C
-40°C < T < 125 °C
DocID024293 Rev 1
110
mV
51
mA
42
45
60
60
µA
9/31
Electrical characteristics
TSX63x, TSX63xA
Table 6. Electrical characteristics at VCC+ = +10 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and
RL=10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
160
200
Max.
Unit
AC performance
GBP
Gain bandwidth product
Fu
Unity gain frequency
Φm
Phase margin
Gm
Gain margin
SR
Slew rate
∫ en
Low-frequency peak-to-peak
input noise
en
Equivalent input noise voltage
RL = 100 kΩ, CL = 100 pF
160
kHz
55
degrees
9
dB
RL = 100 kΩ, CL = 100 pF,
Vout = 0.5 V to VCC - 0.5V
0.12
V/μs
Bandwidth: f = 0.1 to 10 Hz
5
µVpp
60
nV
-----------Hz
0.004
%
f = 1 kHz
f = 10 kHz
THD+N Total harmonic distortion + noise
Follower configuration,
fin = 1 kHz, RL = 100 kΩ,
Vicm = 5 V, BW = 22 kHz,
Vout = 1 Vpp
1. See Chapter 4.3: Input offset voltage drift over temperature on page 18
2. Typical value is based on the Vio drift observed after 1000h at 125°C extrapolated to 25°C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. See
Chapter 4.4: Long term input offset voltage drift on page 19.
3. Guaranteed by design
10/31
DocID024293 Rev 1
TSX63x, TSX63xA
Electrical characteristics
Table 7. Electrical characteristics at VCC+ = +16 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and
RL=10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
Vio
Vio
Offset voltage
Offset voltage, high commonmode (Vicm=VCC, RL > 1 MΩ)
ΔVio/ΔT Input offset voltage drift
TSX63xA, T = 25 °C
700
TSX63xA, -40°C < T < 125 °C
1500
T = 25 °C
1.6
-40°C < T < 125 °C
2.4
T = 25°C
4
-40°C < T < 125 °C
5
-40°C < T < 125 °C(1)
Long term input offset voltage
drift
T = 25 °C(2)
Iio
Input offset current
(Vout = VCC/2)
T = 25 °C
Iib
Input bias current
(Vout = VCC/2)
ΔVio
1
8
T = 25 °C
1
μV/°C
---------------------------
100(3)
200(3)
-40°C < T < 125 °C
mV
μV
month
3.4
1
μV
100(3)
pA
200(3)
-40°C < T < 125 °C
RIN
Input resistance
1
TΩ
CIN
Input capacitance
5
pF
T = 25 °C
71
CMR1
Common mode rejection ratio
CMR = 20 log (ΔVicm/ΔVio)
(Vicm = -0.1 V to VCC-1.65 V,
Vout = VCC/2, RL > 1 MΩ)
85
-40°C < T < 125 °C
68
T = 25 °C
69
CMR2
Common mode rejection ratio
CMR = 20 log (ΔVicm/ΔVio)
(Vicm = -0.1 V to VCC+0.1 V,
Vout = VCC/2, RL > 1 MΩ)
-40°C < T < 125 °C
66
T = 25 °C
73
SVR
Common mode rejection ratio
20 log (ΔVCC/ΔVio)
(VCC =3.3 V to 16 V,
Vout = Vicm VCC/2)
-40°C < T < 125 °C
70
Large signal voltage gain
(Vout = 0.5 V to (VCC - 0.5 V),
RL > 1 MΩ)
T = 25 °C
100
Avd
-40°C < T < 125 °C
90
VOH
High level output voltage
Vid = +1 V, VOH = VCC-Vout
RL = 10 kΩ, T = 25 °C
70
RL = 10 kΩ, -40°C < T < 125 °C
100
VOL
Low level output voltage
Vid = -1 V,
RL = 10 kΩ, T = 25 °C
70
RL = 10 kΩ, -40°C < T < 125 °C
100
83
dB
DocID024293 Rev 1
87
110
mV
11/31
Electrical characteristics
TSX63x, TSX63xA
Table 7. Electrical characteristics at VCC+ = +16 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and
RL=10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Isink
Iout
Isource
ICC
Supply current
(per operator, Vout = VCC/2,
RL > 1 MΩ)
Conditions
Min.
Typ.
Vout = VCC, T = 25 °C
40
92
Vout = VCC, -40°C < T < 125 °C
35
Vout = 0 V, T = 25 °C
30
Vout = 0 V, -40°C < T < 125 °C
25
T = 25 °C
Max.
mA
90
45
-40°C < T < 125 °C
Unit
60
60
µA
AC performance
GBP
Gain bandwidth product
Fu
Unity gain frequency
Φm
Phase margin
Gm
Gain margin
SR
Slew rate
∫ en
Low-frequency peak-to-peak
input noise
en
Equivalent input noise voltage
160
RL = 100 kΩ, CL = 100 pF
200
160
kHz
55
degrees
9
dB
RL = 100 kΩ, CL = 100 pF,
Vout = 0.5 V to VCC - 0.5V
0.12
V/μs
Bandwidth: f = 0.1 to 10 Hz
5
µVpp
60
nV
-----------Hz
0.004
%
f = 1 kHz
f = 10 kHz
THD+N
Total harmonic distortion +
noise
Follower configuration, fin = 1 kHz,
RL = 100 kΩ, Vicm = 8 V,
BW = 22 kHz, Vout = 1 Vpp
1. See Chapter 4.3: Input offset voltage drift over temperature on page 18
2. Typical value is based on the Vio drift observed after 1000h at 125°C extrapolated to 25°C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. See
Chapter 4.4: Long term input offset voltage drift on page 19.
3. Guaranteed by design
12/31
DocID024293 Rev 1
TSX63x, TSX63xA
Electrical characteristics
Figure 2. Supply current vs. supply voltage at
Vicm = VCC/2
Figure 3. Input offset voltage distribution at
VCC = 16 V
20
50
Vcc=16V
Vicm=8V
T=25°C
Vicm=Vcc/2
15
Population (%)
Supply Current (µA)
40
30
20
T=-40°C
T=25°C
10
0
5
T=125°C
0
2
4
6
8
10
Supply Voltage (V)
12
14
0
-1500
16
-500
0
500
1000
1500
Figure 5. Input offset voltage vs. temperature at
VCC=16 V
3000
35
Limit for TSX63x
Vcc=3.3V
Vicm=1.65V
T=25°C
Limit for TSX63xA
2000
Input offset voltage (µV)
30
-1000
Input offset voltage (µV)
Figure 4. Input offset voltage distribution at
VCC = 10 V
25
Population (%)
10
20
15
10
1000
0
-1000
5
-2000
0
-250
-3000
-40
Vcc=16V
-200
-150
-100
-50
0
50
100
150
200
250
-20
0
Input offset voltage (µV)
Figure 6. Input offset voltage temperature
coefficient distribution
Input Offset Voltage (µV)
Population (%)
10
5
200
0
T=125°C
-200
T=25°C
T=-40°C
-400
-600
-800
-1000
0
-6
-5
120
400
15
-7
100
600
Vcc=16V
Vicm=8V
T=25°C
-8
80
Figure 7. Input offset voltage vs. input common
mode voltage
25
20
20
40
60
Temperature (°C)
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
Vcc=16V
0
Δ Vio/Δ T (µV/°C)
DocID024293 Rev 1
2
4
6
8
10
12
Input Common Mode Voltage (V)
14
16
13/31
Electrical characteristics
TSX63x, TSX63xA
Figure 8. Output current vs. output voltage at
VCC = 3.3 V
Figure 9. Output current vs. output voltage at
VCC = 16 V
125
10.0
100 Sink
Vid=-1V
75
Sink
7.5 Vid=-1V
Output Current (mA)
2.5
0.0
T=-40°C
T=25°C
T=125°C
-2.5
-5.0
25
T=-40°C
T=25°C
0
T=125°C
-25
-50
-75
-7.5
-10.0
0.0
50
0.5
1.0
1.5
2.0
Output Voltage (V)
-100
Source
Vid=1V
Vcc=3.3V
2.5
-125
0.0
3.0
Figure 10. Output low-rail linearity
performance (RL≥ 2 kΩ)
2.0
4.0
14.0
16.0
0.20
From Vcc=3.3V to Vcc=16V
From Vcc=3.3V to Vcc=16V
0.15
0.15
Vcc - Vout (V)
Vout (V)
6.0
8.0 10.0 12.0
Output Voltage (V)
Figure 11. Output high-rail linearity
performance (RL≥ 2kΩ)
0.20
0.10
0.05
0.10
0.05
Follower configuration
T=25°C
0.00
0.00
0.05
0.10
Vin (V)
0.15
Follower configuration
T=25°C
0.00
0.00
0.20
Figure 12. Bode diagram at VCC = 3.3 V,
RL= 10 kΩ
40
0.05
0.10
Vcc - Vin (V)
0.15
0.20
Figure 13. Bode diagram at VCC = 3.3 V,
RL= 100 kΩ
40
0
0
Gain
Gain
-45
30
-45
20
-90
20
-90
Phase
T=-40°C
10
0
-135
Vcc=3.3V
Vicm=1.65V
Rl=10kΩ
Cl=100pF
Gain=-100
-10
T=25°C
-180
0
-225
-10
10k
100k
-270
1M
-20
-135
Vcc=3.3V
Vicm=1.65V
Rl=100kΩ
Cl=100pF
Gain=-100
1k
Frequency (Hz)
14/31
Phase
T=-40°C
10
T=125°C
-20
1k
Gain (dB)
30
Phase (°)
Gain (dB)
Source
Vid=1V
Vcc=16V
-180
T=25°C
-225
T=125°C
10k
100k
Frequency (Hz)
DocID024293 Rev 1
-270
1M
Phase (°)
Output Current (mA)
5.0
TSX63x, TSX63xA
Electrical characteristics
Figure 14. Bode diagram at VCC = 16 V,
RL = 10 kΩ
Figure 15. Bode diagram at VCC = 16 V,
RL = 100 kΩ
0
40
40
0
-45
30
-45
20
-90
20
-90
Phase
T=-40°C
10
0
-135
Vcc=16V
Vicm=8V
Rl=10kΩ
Cl=100pF
Gain=-100
-10
0
-225
-10
-270
1M
-20
100k
-135
Vcc=16V
Vicm=8V
Rl=100kΩ
Cl=100pF
Gain=-100
T=125°C
10k
Phase
T=-40°C
10
-180
T=25°C
-20
1k
Gain (dB)
30
1k
T=125°C
-270
1M
100k
Figure 17. In-series resistor (Riso) vs.
capacitive load
15
10000
Follower configuration
10 Vcc=16V
Vicm=8V
Rl=100kΩ
5 T=25°C
Cl=470pF
Cl=200pF
0
-5
Follower configuration
Vcc=16V
Vicm=8V
Rl=100kΩ
T=25°C
Stable
1000
Riso (Ω )
Gain (dB)
-225
Frequency (Hz)
Figure 16. Closed-loop gain vs.
capacitive load
Unstable
100
Cl=20pF
Cl=100pF
-10
-15
1k
10k
100k
Frequency (Hz)
10
100p
1M
10n
100n
Figure 19. Positive slew rate
6.0
6.0
5.0
T=-40°C
3.0
2.0
1.0
5.0
Vcc=16V
Vicm=Vcc/2
Rl=100kΩ
Cl=100pF
T=25°C
0.0
-1.0
T=125°C
-2.0
4.0
3.0
Output Voltage (V)
4.0
-3.0
2.0
0.0
-2.0
-3.0
-5.0
-5.0
20
40
60
80
Time (µs)
100
120
140
T=25°C
-1.0
-4.0
0
T=125°C
1.0
-4.0
-6.0
-20
1n
Cload (F)
Figure 18. Negative slew rate
Output Voltage (V)
-180
T=25°C
10k
Frequency (Hz)
Phase (°)
Gain
Phase (°)
Gain (dB)
Gain
-6.0
-20
DocID024293 Rev 1
T=-40°C
0
20
40
60
80
Time (µs)
Vcc=16V
Vicm=Vcc/2
Rl=100kΩ
Cl=100pF
100
120
140
15/31
Electrical characteristics
TSX63x, TSX63xA
Figure 20. Slew rate vs. supply voltage
Figure 21. Small step response
0.10
0.20
Vcc = 16V
Vicm=8V
Rl=100kΩ
Cl=100pF
T=25°C
0.15
0.05
Slew rate (V/µs)
0.05
0.00
T=125°C
T=25°C
Vicm=Vcc/2
Vload=Vcc/2
Rl=100kΩ
Cl=100pF
T=-40°C
-0.05
-0.10
Output Voltage (V)
0.10
0.00
-0.05
-0.15
-0.10
-0.20
4
6
8
10
12
Supply Voltage (V)
14
0
16
Figure 22. Noise vs. frequency at VCC = 16 V
20
Time (µs)
30
40
Figure 23. 0.1 Hz to 10 Hz noise at VCC = 16 V
400
4
350
Vcc=16V
Vicm=Vcc/2
T=25°C
300
250
200
150
100
Input voltage noise (µV)
Equivalent Input Noise Voltage (nV/VHz)
10
2
Vcc=16V
Vicm=8V
T=25°C
0
-2
50
0
10
100
1000
Frequency (Hz)
-4
0
10000
8
10
1
Vcc=16V
Vicm=8V
Gain=1
Vin=1Vpp
BW=80kHz
Rl=100kΩ
T=25°C
0.1
THD + N (%)
THD + N (%)
6
Figure 25. THD+N vs. output voltage at
VCC = 16 V
1
0.01
100
16/31
4
Time (s)
Figure 24. THD+N vs. frequency at
VCC = 16 V
0.1
2
1000
Frequency (Hz)
10000
0.01
1E-3
0.01
DocID024293 Rev 1
Vcc=16V
Vicm=8V
Gain=1
f=1kHz
BW=22kHz
Rl=100kΩ
T=25°C
0.1
1
Output Voltage (Vpp)
10
TSX63x, TSX63xA
Electrical characteristics
Figure 26. Output impedance vs. frequency in
closed loop configuration
Figure 27. PSRR vs. frequency
10000
100
Vcc=16V
Vicm=8V
Gain=1
Vosc=30mVRMS
T=25°C
+
PSRR
80
PSRR (dB)
Output impedance (Ω )
1000
100
10
1
60
Vcc=16V
Vicm=8V
Gain=1
Rl=10kΩ
Cl=100pF
Vosc=100mVPP
T=25°C
40
20
-
PSRR
0.1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
0
10
DocID024293 Rev 1
100
1k
10k
Frequency (Hz)
100k
1M
17/31
Application information
TSX63x, TSX63xA
4
Application information
4.1
Operating voltages
The amplifiers of the TSX63x and TSX63xA series can operate from 3.3 to 16 V. Their
parameters are fully specified at 3.3, 5, 10 and 16 V power supplies. However, the
parameters are very stable in the full VCC range. Additionally, the main specifications are
guaranteed in extended temperature ranges from -40 ° C to +125 ° C.
4.2
Rail-to-rail input
The TSX63x and TSX63xA are built with two complementary PMOS and NMOS input
differential pairs. The devices have a rail-to-rail input, and the input common mode range is
extended from VCC-- 0.1 V to VCC+ + 0.1 V.
However, the performance of these devices is clearly optimized for the PMOS differential
pairs (which means from VCC- - 0.1V to VCC+ - 1.65V).
Beyond VCC+ - 1.65 V, the op-amp is still functional but with a degraded performance as can
be observed in the electrical characteristics section of this datasheet (mainly Vio).
These performances are suitable for a number of applications requiring rail-to-rail input and
output.
The devices are guaranteed without phase reversal.
4.3
Input offset voltage drift over temperature
The maximum input voltage drift over the temperature variation is defined as the offset
variation related to offset value measured at 25 °C. The operational amplifier is one of the
main circuits of the signal conditioning chain, and the amplifier input offset is a major
contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated
during production at application level. The maximum input voltage drift over temperature
enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
Equation 1
ΔV io
V io ( T ) – V io ( 25° C )
------------ = max -------------------------------------------------ΔT
T – 25° C
with T = -40 °C and 125 °C.
The datasheet maximum value is guaranteed by a measurement on a representative
sample size ensuring a Cpk (process capability index) greater than 2.
18/31
DocID024293 Rev 1
TSX63x, TSX63xA
4.4
Application information
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
•
Voltage acceleration, by changing the applied voltage
•
Temperature acceleration, by changing the die temperature (below the maximum
junction temperature allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2.
Equation 2
A FV = e
β ⋅ ( VS – VU )
Where:
AFV is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3.
Equation 3
A FT = e
Ea ⎛ 1
1
------ ⋅ ------ – ------⎞
⎝ T U T S⎠
k
Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate
k is the Boltzmann constant (8.6173 x 10-5 eV.K-1)
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die under temperature stress (K)
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and
the temperature acceleration factor (Equation 4).
Equation 4
A F = A FT × A FV
AF is calculated using the temperature and voltage defined in the mission profile of the
product. The AF value can then be used in Equation 5 to calculate the number of months of
use equivalent to 1000 hours of reliable stress duration.
DocID024293 Rev 1
19/31
Application information
TSX63x, TSX63xA
Equation 5
Months = A F × 1000 h × 12 months ⁄ ( 24 h × 365.25 days )
To evaluate the op-amp reliability, a follower stress condition is used where VCC is defined
as a function of the maximum operating voltage and the absolute maximum rating (as
recommended by JEDEC rules).
The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at
different measurement conditions (see Equation 6).
Equation 6
V CC = maxV op with V icm = V CC ⁄ 2
The long term drift parameter (ΔVio), estimating the reliability performance of the product, is
obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the
calculated number of months (Equation 7).
Equation 7
V io drift
ΔV io = -----------------------------( months )
where Vio drift is the measured drift value in the specified test conditions after 1000 h stress
duration.
4.5
High values of input differential voltage
In closed loop configuration, which represents the typical use of an op-amp, the input
differential voltage is low (close to Vio). However, some specific conditions can lead to
higher input differential values, such as:
•
operation in an output saturation state
•
operation at speeds higher than the device bandwidth, with output voltage dynamics
limited by slew rate.
•
use of the amplifier in a comparator configuration, hence in open loop
Use of the TSX631 in comparator configuration, especially combined with high temperature
and long duration can create a permanent drift of Vio.
All channels of the dual and quad versions of the TSX632 and TSX634 are virtually
unaffected when used in comparator configuration.
4.6
PCB layouts
For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible
to the power supply pins.
20/31
DocID024293 Rev 1
TSX63x, TSX63xA
4.7
Application information
Macromodel
Accurate macromodels of the TSX63x and TSX63xA are available on STMicroelectronics’
web site at www.st.com. These models are a trade-off between accuracy and complexity
(that is, time simulation) of the TSX63x and TSX63xA operational amplifiers. They emulate
the nominal performances of a typical device within the specified operating conditions
mentioned in the datasheet. They also help to validate a design approach and to select the
right operational amplifier, but they do not replace on-board measurements.
DocID024293 Rev 1
21/31
Package information
5
TSX63x, TSX63xA
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
22/31
DocID024293 Rev 1
TSX63x, TSX63xA
5.1
Package information
SOT23-5 package information
Figure 28. SOT23-5 package mechanical drawing
Table 8. SOT23-5 package mechanical data
Dimensions
Ref.
A
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
0.90
1.20
1.45
0.035
0.047
0.057
A1
0.15
0.006
A2
0.90
1.05
1.30
0.035
0.041
0.051
B
0.35
0.40
0.50
0.013
0.015
0.019
C
0.09
0.15
0.20
0.003
0.006
0.008
D
2.80
2.90
3.00
0.110
0.114
0.118
D1
1.90
0.075
e
0.95
0.037
E
2.60
2.80
3.00
0.102
0.110
0.118
F
1.50
1.60
1.75
0.059
0.063
0.069
L
0.10
0.35
0.60
0.004
0.013
0.023
K
0°
10 °
0°
DocID024293 Rev 1
10 °
23/31
Package information
5.2
TSX63x, TSX63xA
DFN8 2x2 package information
Figure 29. DFN8 2x2 package mechanical drawing
'
$
%
& [
(
3,1,1'(;$5($
& [
7239,(:
$
$
&
&
6($7,1*
3/$1(
6,'(9,(:
&
H
E SOFV
3,1,1'(;$5($
& $ %
/
3LQ,'
%277209,(:
*$06&%
Table 9. DFN8 2x2 package mechanical data
Dimensions
Ref.
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.70
0.75
0.80
0.028
0.030
0.031
A1
0.00
0.02
0.05
0.000
0.001
0.002
b
0.15
0.20
0.25
0.006
0.008
0.010
D
2.00
0.079
E
2.00
0.079
e
0.50
0.020
L
N
24/31
Millimeters
0.045
0.55
0.65
8
DocID024293 Rev 1
0.018
0.022
8
0.026
TSX63x, TSX63xA
5.3
Package information
MiniSO-8 package information
Figure 30. MiniSO-8 package mechanical drawing
Table 10. MiniSO-8 package mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
A
Inches
Max.
Min.
Typ.
1.1
A1
0
A2
0.75
b
Max.
0.043
0.15
0
0.95
0.030
0.22
0.40
0.009
0.016
c
0.08
0.23
0.003
0.009
D
2.80
3.00
3.20
0.11
0.118
0.126
E
4.65
4.90
5.15
0.183
0.193
0.203
E1
2.80
3.00
3.10
0.11
0.118
0.122
e
L
0.85
0.65
0.40
0.60
0.006
0.033
0.026
0.80
0.016
0.024
L1
0.95
0.037
L2
0.25
0.010
k
ccc
0°
0.037
8°
0.10
DocID024293 Rev 1
0°
0.031
8°
0.004
25/31
Package information
5.4
TSX63x, TSX63xA
QFN16 3x3 package information
Figure 31. QFN16 3x3 package mechanical drawing
'
$
%
DDD & [
(
,1'(;$5($
'[(
DDD & [
7239,(:
$
FFF &
$
&
6($7,1*
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6,'(9,(:
HHH &
H
/
E
EEE
EEE
3LQ,'
5
& $ %
&
%277209,(:
*$06&%
26/31
DocID024293 Rev 1
TSX63x, TSX63xA
Package information
Table 11. QFN16 3x3 package mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
Inches
Max.
Min.
Typ.
Max.
A
0.50
0.65
0.020
0.026
A1
0
0.05
0
0.002
b
0.18
0.30
0.007
0.25
0.010
D
3.00
0.118
E
3.00
0.118
e
0.50
0.020
L
0.30
0.50
0.012
0.012
0.020
aaa
0.15
0.006
bbb
0.10
0.004
ccc
0.10
0.004
ddd
0.05
0.002
eee
0.08
0.003
DocID024293 Rev 1
27/31
Package information
5.5
TSX63x, TSX63xA
TSSOP14 package information
Figure 32. TSSOP14 package mechanical drawing
Table 12. TSSOP14 package mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
A
Max.
Min.
Typ.
1.20
A1
0.05
A2
0.80
b
Max.
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0089
D
4.90
5.00
5.10
0.193
0.197
0.201
E
6.20
6.40
6.60
0.244
0.252
0.260
E1
4.30
4.40
4.50
0.169
0.173
0.176
e
L
k
aaa
1.00
0.65
0.45
L1
28/31
Inches
0.60
0.0256
0.75
0.018
1.00
0°
0.024
0.030
0.039
8°
0.10
DocID024293 Rev 1
0°
8°
0.004
TSX63x, TSX63xA
6
Ordering information
Ordering information
Table 13. Order codes
Order
code
No. of
channels
Package
TSX631ILT
1
SOT23-5
K27
TSX632IQ2T
2
DFN8 2x2
K27
2
MiniSO8
K27
TSX634IQ4T
4
QFN16 3x3
K27
TSX634IPT
4
TSSOP14
TSX634I
1
SOT23-5
K188
2
MiniSO8
4
TSSOP14
1
SOT23-5
K189
2
MiniSO8
K189
4
TSSOP14
TSX634AI
1
SOT23-5
K190
2
MiniSO8
K190
4
TSSOP14
TSX634AIY
TSX632IST
TSX631IYLT
TSX632IYST
TSX634IYPT
Temperature
range
-40 to 125 °C
-40 to 125 °C
Automotive
grade(1)
TSX631AILT
TSX632AIST
-40 to 125 °C
TSX634AIPT
TSX631AIYLT
TSX632AIYST
TSX634AIYPT
-40 to 125°C
Automotive
grade(1)
Packing
Tape and reel
Marking
K188
TSX634IY
1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced
screening according to AEC Q001 & Q 002 or equivalent are on-going.
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Revision history
7
TSX63x, TSX63xA
Revision history
Table 14. Document revision history
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Date
Revision
26-Mar-2013
1
Changes
Initial release
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