TSX711, TSX711A, TSX712
Datasheet
Low-power, precision, rail-to-rail, 2.7 MHz, 16 V CMOS operational amplifiers
TSX711 and TSX711A
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SOT23-5
TSX712
MiniSO8
Features
Low input offset voltage: 200 µV max.
Rail-to-rail input and output
Low current consumption: 800 µA max.
Gain bandwidth product: 2.7 MHz
Low supply voltage: 2.7 - 16 V
Unity gain stable
Low input bias current: 50 pA max.
High ESD tolerance: 4 kV HBM
Extended temp. range: -40 °C to 125 °C
Automotive qualification
SO8
Applications
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Maturity status link
TSX711, TSX711A, TSX712
Related products
TSX7191, TSX7192
For higher speeds
with similar
precision
TSX561, TSX562
For low-power
features
TSX631, TSX632
For micro-power
features
TSX921, TSX922
For higher speeds
Battery-powered instrumentation
Instrumentation amplifier
Active filtering
DAC buffer
High-impedance sensor interface
Current sensing (high and low side)
Description
The TSX711, TSX711A, and TSX712 series of operational amplifiers (op amps) offer
high precision functioning with low input offset voltage down to a maximum of 200 µV
at 25 °C. In addition, their rail-to-rail input and output functionality allow these
products to be used on full range input and output without limitation. This is
particularly useful for a low-voltage supply such as 2.7 V that the TSX71x is able to
operate with.
Thus, the TSX71x has the big advantage of offering a large span of supply voltages,
ranging from 2.7 V to 16 V. They can be used in multiple applications with a unique
reference.
Low input bias current performance makes the TSX71x perfect when used for signal
conditioning in sensor interface applications. In addition, low-side and high-side
current measurements can be easily made thanks to rail-to-rail functionality.
High ESD tolerance (4 kV HBM) and a wide temperature range are also good
reasons to use the TSX71x in the automotive market segment.
DS10192 - Rev 6 - September 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
TSX711, TSX711A, TSX712
Package pin connections
1
Package pin connections
Figure 1. Pin connections (top view)
1
OUT
VCC+
5
2
VCC-
+
IN+
3
IN-
4
SOT23-5
OUT1
1
IN1-
2
-
IN1+
3
+
VCC-
4
8
VCC+
7
OUT2
-
6
IN2-
+
5
IN2+
MiniSO8 and SO8
DS10192 - Rev 6
page 2/29
TSX711, TSX711A, TSX712
Absolute maximum ratings and operating conditions
2
Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings (AMR)
Symbol
Parameter
VCC
Supply voltage
Vid
Differential input voltage (2)(3)
Vin
Input voltage
Iin
Tstg
Rthja
Tj
ESD
Input current
(1)
(4)
Storage temperature
Thermal resistance junction to ambient (5)(6)
Value
Unit
18
V
±VCC
mV
(VCC-) - 0.2 to (VCC+) + 0.2
V
10
mA
-65 to 150
°C
SOT23-5
250
MiniSO8
190
SO8
125
Maximum junction temperature
150
HBM: human body model (7)
4000
MM: machine model
(8)
100
CDM: charged device model
(9)
Latch-up immunity
°C/W
°C
V
1500
200
mA
1. All voltage values, except the differential voltage are with respect to the network ground terminal.
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. See Section 5.7 High
values of input differential voltage for the precautions to follow when using the TSX711, TSX711A, and TSX712 with a high
differential input voltage.
3. Input stage is protected against excessive differential voltage. Each input has a 1 kΩ resistor connected on the input, in
series with the emitter of a PNP transistor with collector grounded. The base of the PNP is connected to the other input. This
structure is present on both inputs. Therefore, in comparator mode, or when Vdiff becomes higher than a diode voltage (Vd
~ 0.7 V), the input with the highest voltage has a current of (Vdiff - Vd) / 1 kΩ. The other input has a much lower input current
as it is divided by the gain of the PNP. See Section 5.7 High values of input differential voltage for more details.
4. Input current must be limited by a resistor in series with the inputs.
5. Rth are typical values.
6. Short-circuits can cause excessive heating and destructive dissipation.
7. According to JEDEC standard JESD22-A114F.
8. According to JEDEC standard JESD22-A115A.
9. According to ANSI/ESD STM5.3.1
Table 2. Operating conditions
Symbol
DS10192 - Rev 6
Parameter
VCC
Supply voltage
Vicm
Common mode input voltage range
Toper
Operating free air temperature range
Value
2.7 to 16
(VCC-) - 0.1 to (VCC+) + 0.1
-40 to 125
Unit
V
°C
page 3/29
TSX711, TSX711A, TSX712
Electrical characteristics
3
Electrical characteristics
Table 3. Electrical characteristics at VCC+ = 4 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL > 10 kΩ connected to
VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Vio (TSX711,
TSX712)
Input offset voltage
Vio (TSX711A)
ΔVio/ΔT
ΔVio
Iib
Iio
Input offset voltage drift
Input bias current(1)
current(1)
RIN
Input resistance
CIN
Input capacitance
CMRR (TSX711,
TSX711A)
Common mode rejection
ratio 20 log (ΔVic/ΔVio)
CMRR (TSX712)
Avd
Large signal voltage gain
High level output voltage
(voltage drop from VCC+)
200
Tmin < Top < 85 °C
365
Tmin < Top < 125 °C
450
Vicm = VCC/2
100
Tmin < Top < 85 °C
265
Tmin < Top < 125 °C
350
2.5
T = 25 °C
1
Vout = VCC/2
1
Tmin < Top < Tmax
Vout = VCC/2
1
Tmin < Top < Tmax
84
Tmin < Top < Tmax
83
Vicm = -0.1 to 2 V, Vout = VCC/2
100
Tmin < Top < Tmax
94
Vicm = -0.1 to 4.1 V, Vout = VCC/2
80
Tmin < Top < Tmax
78
Vicm = -0.1 to 2 V, Vout = VCC/2
91
Tmin < Top < Tmax
86
RL = 2 kΩ, Vout = 0.3 to 3.7 V
110
Tmin < Top < Tmax
96
RL = 10 kΩ, Vout = 0.2 to 3.8 V
110
Tmin < Top < Tmax
96
DS10192 - Rev 6
Tmin < Top < Tmax
µV/°C
nV
month
50
50
pA
1
TΩ
12.5
pF
102
122
98
dB
103
136
140
28
Tmin < Top < Tmax
RL = 2 kΩ tο VCC/2
Low level output voltage
μV
200
Vicm = -0.1 to 4.1 V, Vout = VCC/2
RL = 10 kΩ tο VCC/2
Unit
---------------------------
200
50
60
6
Tmin < Top < Tmax
VOL
Max.
Vicm = VCC/2
RL = 2 kΩ to VCC/2
VOH
Typ.
(1)
Long term input offset
voltage drift (2)
Input offset
Min.
15
mV
20
23
50
60
mV
page 4/29
TSX711, TSX711A, TSX712
Electrical characteristics
Symbol
VOL
Parameter
Low level output voltage
Iout (TSX711,
TSX711A)
Isource
Isink
Iout (TSX712)
Isource
RL = 10 kΩ tο VCC/2
Supply current per amplifier
35
Tmin < Top < Tmax
20
Vout = 0 V
35
Tmin < Top < Tmax
20
Vout = VCC
25
Tmin < Top < Tmax
15
Vout = 0 V
35
Tmin < Top < Tmax
20
No load, Vout = VCC/2
ɸm
Phase margin
Gm
Gain margin
SRn
Negative slew rate
en
THD+N
Max.
5
15
Positive slew rate
Unit
mV
45
45
mA
37
45
570
Tmin < Top < Tmax
RL = 10 kΩ, CL = 100 pF
SRp
Typ.
20
Vout = VCC
Gain bandwidth product
GBP
Min.
Tmin < Top < Tmax
Isink
ICC
Conditions
800
900
1.9
μA
2.7
MHz
RL = 10 kΩ, CL = 100 pF
50
Degrees
RL = 10 kΩ, CL = 100 pF
15
dB
Av = 1, Vout = 3 VPP, 10 % to 90 %
0.6
Tmin < Top < Tmax
0.5
Av = 1, Vout = 3VPP, 10 % to 90 %
1.0
Tmin < Top < Tmax
0.9
0.85
1.4
Equivalent input noise
voltage
f = 1 kHz
22
f = 10 kHz
19
Total harmonic distortion +
noise
f =1 kHz, Av = 1, RL= 10 kΩ, BW = 22 kHz,
Vin= 0.8 VPP
0.001
V/μs
nV
-----------Hz
%
1. Maximum values are guaranteed by design.
2. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the
Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower
mode configuration (see Section 5.6 Long term input offset voltage drift).
DS10192 - Rev 6
page 5/29
TSX711, TSX711A, TSX712
Electrical characteristics
Table 4. Electrical characteristics at VCC+ = 10 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL > 10 kΩ connected
to VCC/2 (unless otherwise specified)
Symbol
Parameter
Vio (TSX711,
TSX712)
Input offset voltage
Vio (TSX711A)
ΔVio/ΔT
ΔVio
Iib
Iio
Min.
Long term input offset
voltage drift (2)
Input bias current(1)
Input offset current(1)
Input resistance
CIN
Input capacitance
CMRR (TSX711,
TSX711A)
Common mode rejection
ratio 20 log (ΔVic/ΔVio)
CMRR (TSX712)
Large signal voltage gain
High level output voltage
(voltage drop from VCC+)
200
Tmin < Top < 85 °C
365
Tmin < Top < 125 °C
450
Vicm = VCC/2
100
Tmin < Top < 85 °C
265
Tmin < Top < 125 °C
350
2.5
T = 25 °C
25
Vout = VCC/2
1
Tmin < Top < Tmax
Vout = VCC/2
1
Tmin < Top < Tmax
DS10192 - Rev 6
Isink
Vicm = -0.1 to 10.1 V, Vout = VCC/2
90
Tmin < Top < Tmax
86
Vicm = -0.1 to 8 V, Vout = VCC/2
105
Tmin < Top < Tmax
95
Vicm = -0.1 to 10.1 V, Vout = VCC/2
88
Tmin < Top < Tmax
84
Vicm = -0.1 to 8 V, Vout = VCC/2
98
Tmin < Top < Tmax
92
RL = 2 kΩ, Vout = 0.3 to 9.7 V
110
Tmin < Top < Tmax
100
RL = 10 kΩ, Vout = 0.2 to 9.8 V
110
Tmin < Top < Tmax
100
nV
month
50
50
pA
TΩ
12.5
pF
102
117
100
dB
106
140
45
Tmin < Top < Tmax
70
80
RL = 10 kΩ ο VCC/2
10
30
40
42
Tmin < Top < Tmax
70
mV
80
RL = 10 kΩ ο VCC/2
Vout = VCC
μV/°C
1
9
Tmin < Top < Tmax
Iout (TSX711,
TSX711A)
μV
200
RL = 2 kΩ ο VCC/2
Low level output voltage
Unit
---------------------------
200
Tmin < Top < Tmax
VOL
Max.
Vicm = VCC/2
RL = 2 kΩ ο VCC/2
VOH
Typ.
Input offset voltage drift (1)
RIN
Avd
Conditions
30
40
50
70
mA
page 6/29
TSX711, TSX711A, TSX712
Electrical characteristics
Symbol
Parameter
Isink
Iout (TSX711,
TSX711A)
Isource
Isink
Iout (TSX712)
Isource
ICC
Supply current per amplifier
Conditions
Tmin < Top < Tmax
40
Vout = 0 V
50
Tmin < Top < Tmax
40
Vout = VCC
30
Tmin < Top < Tmax
15
Vout = 0 V
50
Tmin < Top < Tmax
40
No load, Vout = VCC/2
RL = 10 kΩ, CL = 100 pF
ɸm
Phase margin
Gm
Gain margin
SRn
Negative slew rate
SRp
en
THD+N
Positive slew rate
Typ.
Max.
mA
39
69
630
850
1000
1.9
Unit
69
Tmin < Top < Tmax
Gain bandwidth product
GBP
Min.
μA
2.7
MHz
RL = 10 kΩ, CL = 100 pF
53
Degrees
RL = 10 kΩ, CL = 100 pF
15
dB
Av = 1, Vout = 8 VPP, 10 % to 90 %
0.8
Tmin < Top < Tmax
0.7
Av = 1, Vout = 8 VPP, 10 % to 90 %
1.0
Tmin < Top < Tmax
0.9
1
1.3
Equivalent input noise
voltage
f = 1 kHz
22
f = 10 kHz
19
Total harmonic distortion +
noise
f = 1 kHz, Av = 1, RL = 10 kΩ,
BW = 22 kHz, Vin = 5 VPP
0.0003
V/μs
nV
-----------Hz
%
1. Maximum values are guaranteed by design.
2. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the
Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower
mode configuration (see Section 5.6 Long term input offset voltage drift).
DS10192 - Rev 6
page 7/29
TSX711, TSX711A, TSX712
Electrical characteristics
Table 5. Electrical characteristics at VCC+ = 16 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL > 10 kΩ connected
to VCC/2 (unless otherwise specified)
Symbol
Parameter
Vio (TSX711,
TSX712)
Input offset voltage
Vio (TSX711A)
ΔVio/ΔT
ΔVio
Iib
Iio
Long term input offset
voltage drift (2)
Input bias current(1)
Input offset current(1)
Input resistance
CIN
Input capacitance
Tmin < Top < 85 °C
365
Tmin < Top < 125 °C
450
Vicm = VCC/2
100
Tmin < Top < 85 °C
265
Tmin < Top < 125 °C
350
2.5
T = 25 °C
Vout = VCC/2
1
Tmin < Top < Tmax
1
Tmin < Top < Tmax
Vicm = -0.1 to 14 V, Vout = VCC/2
110
Tmin < Top < Tmax
96
Vicm = -0.1 to 16.1 V, Vout = VCC/2
94
Tmin < Top < Tmax
90
Vicm = -0.1 to 14 V, Vout = VCC/2
100
Tmin < Top < Tmax
90
Supply voltage rejection ratio Vcc = 4 to 16 V
20 log (ΔVcc/ΔVio)
Tmin < Top < Tmax
100
High level output voltage
(voltage drop from VCC+)
110
Tmin < Top < Tmax
100
RL = 10 kΩ, Vout = 0.2 to 15.8 V
110
Tmin < Top < Tmax
100
12.5
pF
113
116
107
107
DS10192 - Rev 6
dB
131
146
149
100
130
RL = 2 kΩ (TSX712)
70
130
Tmin < Top < Tmax
Tmin < Top < Tmax
pA
TΩ
RL = 2 kΩ (TSX711, TSX711A)
RL = 2 kΩ
Low level output voltage
50
1
150
16
Tmin < Top < Tmax
VOL
50
90
RL = 2 kΩ, Vout = 0.3 to 15.7 V
RL = 10 kΩ
μV/°C
200
90
Large signal voltage gain
μV
---------------------------
200
Vout = VCC/2
Unit
nV
month
500
Tmin < Top < Tmax
CMRR (TSX712)
Max.
200
94
Common mode rejection
ratio 20 log (ΔVic/ΔVio)
VOH
Typ.
Vicm = VCC/2
Vicm = -0.1 to 16.1 V, Vout = VCC/2
CMRR (TSX711,
TSX711A)
Avd
Min.
Input offset voltage drift (1)
RIN
SVRR
Conditions
mV
40
50
70
130
150
mV
page 8/29
TSX711, TSX711A, TSX712
Electrical characteristics
Symbol
VOL
Parameter
Low level output voltage
Iout (TSX711,
TSX711A)
Isource
Isink
Iout (TSX712)
Isource
RL = 10 kΩ
Supply current per amplifier
50
Tmin < Top < Tmax
45
Vout = 0 V
50
Tmin < Top < Tmax
45
Vout = VCC
30
Tmin < Top < Tmax
15
Vout = 0 V
50
Tmin < Top < Tmax
45
No load, Vout = VCC/2
ɸm
Phase margin
Gm
Gain margin
SRn
Negative slew rate
en
THD+N
Max.
15
40
Positive slew rate
Unit
mV
71
68
mA
40
68
660
Tmin < Top < Tmax
RL = 10 kΩ, CL = 100 pF
SRp
Typ.
50
Vout = VCC
Gain bandwidth product
GBP
Min.
Tmin < Top < Tmax
Isink
ICC
Conditions
900
1000
1.9
μA
2.7
MHz
RL = 10 kΩ, CL = 100 pF
55
Degrees
RL = 10 kΩ, CL= 100 pF
15
dB
Av = 1, Vout = 10 VPP, 10 % to 90 %
0.7
Tmin < Top < Tmax
0.6
Av = 1, Vout = 10 VPP, 10 % to 90 %
Tmin < Top < Tmax
1
0.95
1.4
V/μs
0.9
Equivalent input noise
voltage
f = 1 kHz
22
f = 10 kHz
19
Total harmonic distortion +
Noise
f = 1 kHz, Av = 1, RL = 10 kΩ,
BW = 22 kHz, Vin = 5 VPP
0.0002
nV
-----------Hz
%
1. Maximum values are guaranteed by design.
2. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the
Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower
mode configuration (see Section 5.6 Long term input offset voltage drift).
DS10192 - Rev 6
page 9/29
TSX711, TSX711A, TSX712
Electrical characteristic curves
4
Electrical characteristic curves
Figure 2. Supply current vs. supply voltage
Figure 3. Input offset voltage distribution at VCC = 16 V
20
800
Vcc = 16 V
Vicm = 8 V
T = 25 ºC
600
15
Population (%)
Supply Current (µA)
Vicm=Vcc/2
T=-40°C
400
T=25°C
T=125°C
200
0
5
0
2
4
6
8
10
Supply Voltage (V)
12
14
0
-300 -250 -200 -150 -100
16
0
50
100
150
200
250
300
Figure 5. Input offset voltage vs. temperature at
VCC = 16 V
20
600
Vcc = 4V
V icm = 2V
T = 25°C
Vio limit
400
Input offset voltage (µV)
15
Population (%)
-50
Input offset voltage (µV)
Figure 4. Input offset voltage distribution at VCC = 4 V
10
5
0
-300 -250 -200 -150 -100
-50
0
50
100
Input offset voltage (µV)
DS10192 - Rev 6
10
150
200
250
300
200
0
-200
-400
-600
-40
Vcc=16V
Vicm=8V
-20
0
20
40
60
Temperature (°C)
80
100
120
page 10/29
TSX711, TSX711A, TSX712
Electrical characteristic curves
Figure 6. Input offset voltage drift population
Figure 7. Input offset voltage vs. supply voltage at
VICM = 0 V
40
600
Vcc = 16V
Vicm = 8V
T = 25ºC
35
Input Offset Voltage (µV)
Population (%)
25
20
15
10
5
0
-4
Vicm = 0V
400
30
-3
-2
-1
0
1
2
3
200
0
-200
T = -40°C
-600
4
4
∆Vio/∆T (µV/ºC)
Figure 8. Input offset voltage vs. common mode voltage
at VCC = 2.7 V
6
8
10
12
Supply voltage (V)
14
16
600
Vcc = 2.7V
400
200
0
-200
T = 125°C
T = 25°C
T = -40°C
-400
0.0
0.5
1.0
1.5
2.0
2.5
Input Common Mode Voltage (V)
Input Offset Voltage (µV)
400
Input Offset Voltage (µV)
T = 125°C
Figure 9. Input offset voltage vs. common mode voltage
at VCC = 16 V
600
-600
T = 25°C
-400
Vcc = 16V
200
0
-200
T = 125°C
-400
-600
0
2
T = -40°C
T = 25°C
4
6
8
10
12
14
Input Common Mode Voltage (V)
16
Figure 10. Output current vs. output voltage at VCC = 2.7 V Figure 11. Output current vs. output voltage at VCC = 16 V
(TSX711, TSX711A)
(TSX711, TSX711A)
30
75
10
0
T = -40°C
T = 125°C
T = 25°C
-10
-20
-30
0.0
DS10192 - Rev 6
Vcc = 2.7V
0.5
1.0
1.5
2.0
Output Voltage (V)
Source
Vid = 1V
2.5
Output Current (mA)
Output Current (mA)
20
100
Sink
Vid = -1V
Sink
Vid=1V
50
25
0
T=25°C
T=125°C
T=-40°C
-25
-50
-75
-100
0
Vcc=16V
2
4
6
8
10
12
Output Voltage (V)
Source
Vid=1V
14
16
page 11/29
TSX711, TSX711A, TSX712
Electrical characteristic curves
Figure 12. Output current vs. output voltage at VCC = 2.7 V Figure 13. Output current vs. output voltage at VCC = 16 V
(TSX712)
(TSX712)
30.0
22.5
75
15.0
7.5
T=-40ºC
0.0
T=25ºC
T=125ºC
-7.5
-15.0
-22.5
0.5
25
0
-25
-50
-75
Source
Vid =1V
Vcc=2.7V
-30.0
0.0
50
Output Current (mA)
Output Current (mA)
100
Sink
Vid =-1V
1.0
1.5
2.0
Output Voltage (V)
2.5
Figure 14. Output low voltage vs. supply voltage
Output voltage (from Vcc+) (mV)
Output voltage (mV)
25
T=-40ºC
T=25ºC
20
T=125ºC
15
10
5
0
4
6
8
10
12
Supply voltage (V)
14
25
1.5
1.0
16.00
15.95
15.90
15.85
15.80
4
6
8
10
12
Supply voltage (V)
0.5
0.0
14
16
T=125ºC
T=25ºC
T=-40ºC
Vicm=Vcc/2
Vload=Vcc/2
RI=10kΩ
CI=100pF
-0.5
-2.0
0.15
T=125ºC
-1.5
0.00
0.10
T=-40ºC
-1.0
Vcc=16V
Follower configuration
0.05
16
5
15.90
0.00
14
10
15.95
0.05
12
T=25ºC
15
2.0
0.10
Vid=0.1V
RI=10kΩ to Vcc/2
20
16.00
0.15
6
8
10
Output Voltage (V)
Figure 17. Slew rate vs. supply voltage
Slew rate (V/µs)
Output voltage (V)
Figure 16. Output voltage vs. input voltage close to the
rail at VCC = 16 V
15.80
4
30
0
16
15.85
2
Figure 15. Output high voltage (drop from VCC+) vs.
supply voltage
30
Vid=0.1V
RI=10kΩ to Vcc/2
Vcc=16V
-100
0
4
6
8
10
12
Supply Voltage (V)
14
16
Input voltage (V)
DS10192 - Rev 6
page 12/29
TSX711, TSX711A, TSX712
Electrical characteristic curves
Figure 18. Negative slew rate at VCC = 16 V
Figure 19. Positive slew rate at VCC = 16 V
6
6
Vcc=16V
Vicm=Vcc/2
RI=10kΩ
CI=100pF
4
Signal Amplitude (V)
2
T=-40ºC
0
T=25ºC
T=125ºC
0
T=-40ºC
0
2
4
6
8 10
Time (µs)
12
14
16
-6
-2
18
Signal Amplitude (V)
Output Voltage (V)
Time (µs)
10
Figure 22. Recovery behavior after a positive step on the
input
-0.08
Vcc=±8V
-6
-0.12
Vin
-8
Gain=101
RI=10kΩ
CI=100pF
T=25ºC
-0.16
10
20
Time (µs)
30
-0.20
40
0.16
0.12
4
0.08
Vcc=±1.35V
2
0.04
0
0.00
0
10
20
Time (µs)
30
-0.04
40
0
Phase
-30
-60
30
-90
T=-40ºC
20
10
-150
Vcc=2.7V
Vicm=1.35V
RI=10kΩ
CI=100pF
Gain=101
0
-10
-120
T=25ºC
-180
-210
T=125ºC
-20
0
18
Gain
Gain (dB)
-0.04
Vcc=±1.35V
16
Vcc=±8V
40
Input voltage (V)
Output Voltage (V)
6
50
-4
Gain=101
RI=10kΩ
CI=100pF
T=25ºC
60
0.00
-2
14
Figure 23. Bode diagram at VCC = 2.7 V
0.04
0
12
0.20
-2
-10
15
2
6
8 10
Time (µs)
Vin
-0.05
5
4
8
0.00
-0.10
0
2
10
Vcc=16V
Vicm=8V
RI=10kΩ
CI=100pF
T=25ºC
0.05
0
Figure 21. Recovery behavior after a negative step on the
input
0.10
DS10192 - Rev 6
Vcc=16V
Vicm=Vcc/2
RI=10kΩ
CI=100pF
-4
Figure 20. Response to a small input voltage step
-10
-10
T=25ºC
-2
-4
-6
-2
T=125ºC
Input voltage (V)
-2
2
Phase(°)
Signal Amplitude (V)
4
1k
10k
100k
1M
-240
10M
Frequency (Hz)
page 13/29
TSX711, TSX711A, TSX712
Electrical characteristic curves
Figure 25. Power supply rejection ratio (PSRR) vs.
frequency
Figure 24. Bode diagram at VCC = 16 V
60
0
Phase
50
120
-30
100
40
-60
PSRR+
Gain
80
T=-40ºC
20
10
-150
Vcc=16V
Vicm=8V
RI=10kΩ
CI=100pF
Gain=101
0
-10
-120
T=25ºC
PSRR (dB)
-90
Phase(°)
Gain (dB)
30
-180
60
Vcc=16V
Vicm=8V
Gain=101
RI=10kΩ
CI=100pF
Vosc=20mVpp
T=25ºC
40
20
-210
PSRR-
T=125ºC
-20
1k
10k
100k
-240
10M
1M
0
10
Frequency (Hz)
Figure 26. Output overshoot vs. capacitive load
100
Vcc=2.7V
50
25
0
10
100
Cload (pF)
THD + N (%)
THD + N (%)
10k
0.1
RI=2kΩ
DS10192 - Rev 6
1
100k
Frequency (Hz)
1M
10M
1
Vcc=16V
Vicm=8V
Gain=1
Vin=10Vpp
BW=80kHz
T=25ºC
0.01
1E-4
10
Figure 29. THD + N vs. output voltage
1
1E-3
100
0.1
1k
1000
Figure 28. THD + N vs. frequency
0.1
1M
Vcc=16V
Vicm=8V
Gain=1
Vosc=30mVRMS
T=25ºC
1000
Vcc=16V
125
75
100k
10000
Vicm=Vcc/2
RI=10kΩ
Vin=100mVpp
Gain=1
T=25ºC
Output impedance (Ω)
Overshoot (%)
150
1k
10k
Frequency (Hz)
Figure 27. Output impedance vs. frequency in closed loop
configuration
200
175
100
RI=100kΩ
100
RI=10kΩ
1000
Frequency (Hz)
RI=10kΩ
0.01
1E-3
10000
RI=2kΩ
Vcc=16V
Vicm=8V
Gain=1
f=1kHz
BW=22kHz
T=25ºC
1E-4
0.01
RI=100kΩ
0.1
1
Output voltage (Vpp)
10
page 14/29
TSX711, TSX711A, TSX712
Electrical characteristic curves
Figure 31. 0.1 to 10Hz noise
6
140
120
Vcc=16V
Vicm=Vcc/2
T=25ºC
100
4
Input voltage noise (µV)
Equivalent Input Noise Voltage (nV/√ Hz)
Figure 30. Noise vs. frequency
80
60
40
2
0
-2
-4
20
0
10
Vcc=16V
Vicm=8V
T=25ºC
100
1k
Frequency (Hz)
-6
0
10k
2
4
Time (s)
6
8
10
Figure 32. Channel separation (TSX712)
140
Channel separation (dB)
120
100
80
60
40
20
0
10
Vcc=16V
Vicm=8V
Gain=1
Vin=2Vpp
T=25ºC
100
1k
10k
100k
1M
Frequency (Hz)
DS10192 - Rev 6
page 15/29
TSX711, TSX711A, TSX712
Application information
5
Application information
5.1
Operating voltages
The TSX711, TSX711A, and TSX712 devices can operate from 2.7 to 16 V. The parameters are fully specified for
4 V, 10 V, and 16 V power supplies. However, the parameters are very stable in the full VCC range. Additionally,
the main specifications are guaranteed in extended temperature ranges from -40 to 125 °C.
5.2
Input pin voltage ranges
The TSX711, TSX711A, and TSX712 devices have internal ESD diode protection on the inputs. These diodes are
connected between the input and each supply rail to protect the input MOSFETs from electrical discharge.
If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become conductive and excessive
current can flow through them. Without limitation this overcurrent can damage the device.
In this case, it is important to limit the current to 10 mA, by adding resistance on the input pin, as described in
Figure 33. Input current limitation.
Figure 33. Input current limitation
16 V
R
Vin
5.3
-
+
+
-
Vout
Rail-to-rail input
The TSX711, TSX711A, and TSX712 devices have a rail-to-rail input, and the input common mode range is
extended from (VCC -) - 0.1 V to (VCC+) + 0.1 V.
5.4
Rail-to-rail output
The operational amplifier output levels can go close to the rails: to a maximum of 40 mV above and below the rail
when connected to a 10 kΩ resistive load to VCC/2.
5.5
Input offset voltage drift overtemperature
The maximum input voltage drift variation overtemperature is defined as the offset variation related to the offset
value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and
the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be
compensated during production at application level. The maximum input voltage drift overtemperature enables the
system designer to anticipate the effect of temperature variations.
The maximum input voltage drift overtemperature is computed using Equation 1.
Equation 1
∆V io
V ( T ) – V io ( 25 °C)
= ma x io
∆T
T – 25 °C
Where T = -40 °C and 125 °C.
The TSX711, TSX711A, and TSX712 datasheet maximum values are guaranteed by measurements on a
representative sample size ensuring a Cpk (process capability index) greater than 1.3.
DS10192 - Rev 6
page 16/29
TSX711, TSX711A, TSX712
Long term input offset voltage drift
5.6
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
•
Voltage acceleration, by changing the applied voltage
•
Temperature acceleration, by changing the die temperature (below the maximum junction temperature
allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2.
Equation 2
A FV = e
β . ( VS – VU )
Where:
AFV is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3.
Equation 3
A FT = e
E
1
1
-----a- .
–
k
TU TS
Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate
k is the Boltzmann constant (8.6173 x 10-5 eV.K-1)
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die undertemperature stress (K)
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature
acceleration factor (Equation 4).
Equation 4
A F = A FT × A FV
AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can
then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress
duration.
Equation 5
Months = A F × 1000 h × 12 months / ( 24 h × 365.25 days )
To evaluate the op amp reliability, a follower stress condition is used where VCC is defined as a function of the
maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules).
The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement
conditions (see Equation 6).
Equation 6
V CC = maxV op with V icm = V CC / 2
The long term drift parameter (ΔVio), estimating the reliability performance of the product, is obtained using the
ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation
7).
Equation 7
DS10192 - Rev 6
page 17/29
TSX711, TSX711A, TSX712
High values of input differential voltage
∆V io =
V io dr ift
( month s )
Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.
5.7
High values of input differential voltage
In a closed loop configuration, which represents the typical use of an op amp, the input differential voltage is low
(close to Vio). However, some specific conditions can lead to higher input differential values, such as:
•
•
•
operation in an output saturation state
operation at speeds higher than the device bandwidth, with output voltage dynamics limited by slew rate
use of the amplifier in a comparator configuration, hence in open loop.
Use of the TSX711, TSX711A, or TSX712 in comparator configuration, especially combined with high temperature
and long duration can create a permanent drift of Vio.
5.7.1
Input stage protection
In order to protect the input stage against large differential voltage, the TSX71x, have internal back to back
protection diodes between both inputs.
In order to limit the current flowing through these diodes, 1 kΩ serial resistances are placed in series with these
diodes, as described in Figure 34.
Figure 34. Differential input protection
IN+
1 kΩ
1 kΩ
IN-
A maximum differential voltage of 18 V is allowed, as mentioned by Table 1, so a bit less than 18 mA maximum
current can flow through the diodes, which represent a safe condition for such diodes.
DS10192 - Rev 6
page 18/29
TSX711, TSX711A, TSX712
High values of input differential voltage
The protection diodes are made with PNP transistor as described by Figure 35.
Figure 35. Differential input protection (PNP)
IN+
1 kΩ
1 kΩ
IN-
As a result, the amount of current flowing into the diodes, when a large differential input voltage is applied, is not
symmetrical (different current on IN+ and IN- pins).
Indeed, when the differential input voltage becomes high enough to have one transistor in active region (forward
biased base-emitter junction), the second one is off (as its base-emitter junction is reversed biased). The current
is flowing from the input pin with the highest voltage directly to GND (Vcc-) through the resistor and the transistor.
Only a small part of it is flowing to the input pin with the lowest voltage thanks to the gain (beta) of the transistor.
The following example explains how the current can flow. Let’s consider the TSX711 used as a comparator mode
as described by Figure 36. TSX711 in comparator mode (the 10 kΩ resistors are added at application level).
Figure 36. TSX711 in comparator mode
2.5 V
10 kΩ
+
TSX711
4.5 V
DS10192 - Rev 6
10 kΩ
-
page 19/29
TSX711, TSX711A, TSX712
Capacitive load
The TSX711 input can be described by Figure 37. TSX711 input in comparator mode.
Figure 37. TSX711 input in comparator mode
lib+
2.5 V
10 kΩ
1 kΩ
4.5 V
lib-
10 kΩ
As the differential voltage on input pins becomes higher than the forward voltage of the emitter-base junction (~
0.7 V), the PNP transistor is forward active. The current drawn on input pin IN- is:
Iib −
Iib − =
4.5V − 2.5V − Vbe
2V − Vbe
≈
≈ 120µA
10kΩ + 1kΩ + 10kΩ/ β + 1
11kΩ
and Iib + = β + 1 , is in the range of the µA.
So, when it is used in the nonlinear region, the current on the input pins can be different from the pin IN+ and pin
IN-. And this current is directly linked to the differential voltage applied on the input pins and the serial resistance
added in the input path.
5.8
Capacitive load
Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain
peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that
with a gain peaking higher than 2.3 dB an op amp might become unstable.
Generally, the unity gain configuration is the worst case for stability and the ability to drive large capacitive loads.
Figure 38. Stability criteria with a serial resistor at different supply voltage shows the serial resistor that must be
added to the output, to make a system stable. Figure 39. Test configuration for Riso shows the test configuration
using an isolation resistor, Riso.
Figure 38. Stability criteria with a serial resistor at different supply voltage
1000
Vcc=16V
Riso (Ω)
Stable
Vcc=2.7V
100
10
100 p
DS10192 - Rev 6
Unstable
Vicm=Vcc/2
Rl=10kΩ
Gain=1
T=25°C
1n
Cload (F)
10 n
100 n
page 20/29
TSX711, TSX711A, TSX712
PCB layout recommendations
Figure 39. Test configuration for Riso
V CC+
Riso
VIN
+
Cload
V CC-
5.9
VOUT
10 kΩ
PCB layout recommendations
Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier, load, and power
supply. The power and ground traces are critical as they must provide adequate energy and grounding for all
circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic
inductance.
In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that connects the
bottom and top layer ground planes together in many locations is often used.
The copper traces that connect the output pins to the load and supply pins should be as wide as possible to
minimize trace resistance.
5.10
Optimized application recommendation
It is recommended to place a 22 nF capacitor as close as possible to the supply pin. A good decoupling helps to
reduce electromagnetic interference impact.
5.11
5.11.1
Application examples
Oxygen sensor
The electrochemical sensor creates a current proportional to the concentration of the gas being measured. This
current is converted into voltage thanks to R resistance. This voltage is then amplified by the TSX711, TSX711A,
or the TSX712 (see Figure 40. Oxygen sensor principle schematic).
Figure 40. Oxygen sensor principle schematic
R1
R2
VCC
I
O2_ sensor
+
+
Vout
-
The output voltage is calculated using Equation 8:
Equation 8
V ou t = ( I × R – V io ) ×
DS10192 - Rev 6
R2
+1
R1
page 21/29
TSX711, TSX711A, TSX712
Application examples
As the current delivered by the O2 sensor is extremely low, the impact of the Vio can become significant with a
traditional operational amplifier. The use of a precision amplifier like the TSX711, TSX711A, TSX712 is perfect for
this application.
In addition, using the TSX711, TSX711A, TSX712 for the O2 sensor application ensures that the measurement of
O2 concentration is stable, even at different temperatures, thanks to a small ΔVio/ΔT.
5.11.2
Low-side current sensing
Power management mechanisms are found in most electronic systems. Current sensing is useful for protecting
applications. The low-side current sensing method consists of placing a sense resistor between the load and the
circuit ground. The resulting voltage drop is amplified using the TSX711, TSX711A, or TSX712 (see
Figure 41. Low-side current sensing schematic).
Figure 41. Low-side current sensing schematic
C1
Rg1
I
Rf1
In
Rshunt
Rg2
Ip
5V
- +
+ -
Vout
Rf2
Vout can be expressed as follows:
Equation 9
V ou t = R shun t × I 1 –
R g2
R g2 + R f2
1+
R g2 × R f2
R f1
R f1
R f1
+ Ip
– l n × R f1 – V io 1 +
× 1+
R g2 + R f2
R g1
R g1
R g1
Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, Equation 9 can be simplified as follows:
Equation 10
V out = R shunt × I
Rf
Rf
– V io 1 +
+ R f × I io
Rg
Rg
The main advantage of using a precision amplifier like the TSX711, TSX711A, or TSX712, for a low-side current
sensing, is that the errors due to Vio and Iio are extremely low and may be neglected.
Therefore, for the same accuracy, the shunt resistor can be chosen with a lower value, resulting in lower power
dissipation, lower drop in the ground path, and lower cost.
Particular attention must be paid on the matching and precision of Rg1, Rg2, Rf1, and Rf2, to maximize the
accuracy of the measurement.
Taking into consideration the resistor inaccuracies, the maximum and minimum output voltage of the operational
amplifier can be calculated respectively using Equation 11 and Equation 12.
Equation 11
Maximum Vout = Rshunt × I ×
Rf
Rf
× ( 1 + ε rs + 2ε r ) + Vi o × 1 +
+ Rf × li o
Rg
Rg
Equation 12
DS10192 - Rev 6
page 22/29
TSX711, TSX711A, TSX712
Application examples
Minimum Vout = Rshunt × I ×
Rf
Rf
× (1 – ε rs – 2ε r ) – Vi o × 1 +
+ Rf × lio
Rg
Rg
Where:
•
εrs is the shunt resistor inaccuracy (example, 1 % )
•
εr is the inaccuracy of the Rf and Rg resistors (example, 0.1 %)
DS10192 - Rev 6
page 23/29
TSX711, TSX711A, TSX712
Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
6.1
SOT23-5 package information
Figure 42. SOT23-5 package outline
Table 6. SOT23-5 mechanical data
Dimensions
Millimeters
Ref.
A
Min.
Typ.
Max.
Min.
Typ.
Max.
0.90
1.20
1.45
0.035
0.047
0.057
A1
DS10192 - Rev 6
Inches
0.15
0.006
A2
0.90
1.05
1.30
0.035
0.041
0.051
B
0.35
0.40
0.50
0.014
0.016
0.020
C
0.09
0.15
0.20
0.004
0.006
0.008
D
2.80
2.90
3.00
0.110
0.114
0.118
D1
1.90
0.075
e
0.95
0.037
E
2.60
2.80
3.00
0.102
0.110
0.118
F
1.50
1.60
1.75
0.059
0.063
0.069
L
0.10
0.35
0.60
0.004
0.014
0.024
K
0 degrees
10 degrees
0 degrees
10 degrees
page 24/29
TSX711, TSX711A, TSX712
MiniSO8 package information
6.2
MiniSO8 package information
Figure 43. MiniSO8 package outline
Table 7. MiniSO8 package mechanical data
Dimensions
Millimeters
Ref.
Min.
Typ.
A
Max.
Min.
Typ.
1.1
A1
0
A2
0.75
b
Max.
0.043
0.15
0
0.95
0.030
0.22
0.40
0.009
0.016
c
0.08
0.23
0.003
0.009
D
2.80
3.00
3.20
0.11
0.118
0.126
E
4.65
4.90
5.15
0.183
0.193
0.203
E1
2.80
3.00
3.10
0.11
0.118
0.122
e
L
0.85
0.65
0.40
0.60
0.0006
0.033
0.80
0.016
0.024
0.95
0.037
L2
0.25
0.010
ccc
0°
0.037
0.026
L1
k
DS10192 - Rev 6
Inches
8°
0.10
0°
0.031
8°
0.004
page 25/29
TSX711, TSX711A, TSX712
SO8 package information
6.3
SO8 package information
Figure 44. SO8 package outline
Table 8. SO8 package mechanical data
Dimensions
Millimeters
Ref.
Min.
Typ.
A
Max.
Min.
Typ.
1.75
0.25
Max.
0.069
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.010
D
4.80
4.90
5.00
0.189
0.193
0.197
E
5.80
6.00
6.20
0.228
0.236
0.244
E1
3.80
3.90
4.00
0.150
0.154
0.157
e
0.004
0.010
0.049
1.27
0.050
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
L1
k
ccc
DS10192 - Rev 6
Inches
1.04
0°
0.040
8°
0.10
0°
8°
0.004
page 26/29
TSX711, TSX711A, TSX712
Ordering information
7
Ordering information
Table 9. Order codes
Order code
Temperature range
TSX711ILT
(1)
TSX711AIYLT
Packaging
(1)
TSX712IDT
TSX712IST
-40 to 125 °C
K195
SΟΤ23-5
K197
(automotive grade)
-40 to 125 °C
Marking
K29
-40 to 125 °C
TSX711AILT
TSX711IYLT
Package
SO8
Tape and reel
K198
TSX712
MiniSO8
K211
TSX712IYDT (1)
-40 to 125 °C
SO8
TSX712Y
TSX712IYST (1)
(automotive grade)
MiniSO8
K212
1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC
Q001 & Q 002 or equivalent.
DS10192 - Rev 6
page 27/29
TSX711, TSX711A, TSX712
Revision history
Table 10. Document revision history
Date
Revision
Changes
27-Feb-2014
1
Initial release
19-Mar-2014
2
Table 1: updated ESD data for MM (machine model)
Table 3: updated Iout (Isink) values.
25-Jul-2014
3
Table 3, Table 4, and Table 5: updated Vio values, updated ΔVio/ΔT.
Table 5: updated VOL values
Table 6: updated “inches” dimensions
TSX711 datasheet merged with TSX712 datasheet.
26-Jan-2016
4
Reworked the following sections: Cover image, Related products, Description, Section
1: "Package pin connections", Section 2: "Absolute maximum ratings and operating
conditions", Section 3: "Electrical characteristics", Section 4: "Electrical characteristic
curves", Section 5.1: "Operating voltages", Section 5.2: "Input pin voltage ranges",
Section 5.3: "Rail-to-rail input", Section 5.4: "Rail-to-rail output", Section 5.5: "Input
offset voltage drift over temperature", Section 5.7: "High values of input differential
voltage", Section 5.11.1: "Oxygen sensor", Section 5.11.2: "Low-side current sensing",
Section 7: "Ordering information".
Added: Section 6.2: "MiniSO8 package information" and Section 6.3: "SO8 package
information".
Added part number TSX711A
DS10192 - Rev 6
21-Mar-2017
5
Table 9: "Order codes": updated footnotes with respect to TSX711IYLT, TSX711AIYLT,
TSX712IYDT, and TSX712IYST.
22-Sep-2020
6
Added new Section 5.7.1 Input stage protection.
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TSX711, TSX711A, TSX712
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DS10192 - Rev 6
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