TSX7191, TSX7191A
Low-power, precision, rail-to-rail, 9.0 MHz, 16 V operational
amplifier
Datasheet - production data
Description
The TSX7191, TSX7191A single, operational
amplifier (op amp) offers high precision
functioning with low input offset voltage down to a
maximum of 200 µV at 25 °C. In addition, its railto-rail input and output functionality allows this
product to be used on full range input and output
without limitation. This is particularly useful for a
low-voltage supply such as 2.7 V that the
TSX7191, TSX7191A is able to operate with.
Features
Low input offset voltage: 200 µV max.
Rail-to-rail input and output
Low current consumption: 850 µA max.
Gain bandwidth product: 9 MHz
Low supply voltage: 2.7 - 16 V
Stable when used with Gain ≥ 10
Low input bias current: 50 pA max.
High ESD tolerance: 4 kV HBM
Extended temp. range: -40 °C to +125 °C
Automotive qualification
Related products
See the TSX711 for lower speeds with
similar precision
See the TSX561 for low-power features
See the TSX631 for micro-power features
See the TSX921 for higher speeds
Thus, the TSX7191, TSX7191A has the great
advantage of offering a large span of supply
voltages, ranging from 2.7 V to 16 V. It can be
used in multiple applications with a unique
reference.
Low input bias current performance makes the
TSX7191, TSX7191A perfect when used for
signal conditioning in sensor interface
applications. In addition, low-side and high-side
current measurements can be easily made
thanks to rail-to-rail functionality. The TSX7191,
TSX7191A is a decompensated amplifier and
must be used with a gain greater than 10 to
ensure stability.
High ESD tolerance (4 kV HBM) and a wide
temperature range are also good arguments to
use the TSX7191, TSX7191A in the automotive
market segment.
Applications
Battery-powered instrumentation
Instrumentation amplifier
Active filtering
High-impedance sensor interface
Current sensing (high and low side)
March 2017
DocID026747 Rev 3
This is information on a product in full production.
1/25
www.st.com
Contents
TSX7191, TSX7191A
Contents
1
Package pin connections................................................................ 3
2
Absolute maximum ratings and operating conditions ................. 4
3
4
Electrical characteristics ................................................................ 5
Application information ................................................................ 16
5
4.1
Operating voltages .......................................................................... 16
4.2
Input pin voltage ranges .................................................................. 16
4.3
Rail-to-rail input ............................................................................... 16
4.4
Rail-to-rail output ............................................................................. 16
4.5
Input offset voltage drift over temperature ....................................... 17
4.6
Long term input offset voltage drift .................................................. 17
4.7
High values of input differential voltage ........................................... 18
4.8
Capacitive load................................................................................ 19
4.9
PCB layout recommendations ......................................................... 20
4.10
Optimized application recommendation .......................................... 20
Package information ..................................................................... 21
5.1
SOT23-5 package information ........................................................ 22
6
Ordering information..................................................................... 23
7
Revision history ............................................................................ 24
2/25
DocID026747 Rev 3
TSX7191, TSX7191A
1
Package pin connections
Package pin connections
Figure 1: Pin connections (top view)
DocID026747 Rev 3
3/25
Absolute maximum ratings and operating
conditions
2
TSX7191, TSX7191A
Absolute maximum ratings and operating conditions
Table 1: Absolute maximum ratings (AMR)
Symbol
Parameter
VCC
Supply voltage (1)
Vid
Differential input voltage (2)
Vin
Input voltage
Input current
Iin
(3)
Value
Unit
18
V
±VCC
mV
VCC- - 0.2 to VCC++ 0.2
V
10
mA
-65 to +150
°C
Tstg
Storage temperature
Rthja
Thermal resistance junction to ambient (4) (5)
250
°C/W
Maximum junction temperature
150
°C
Tj
HBM: human body model
MM: machine model
ESD
(6)
4000
(7)
CDM: charged device model
100
(8)
Latch-up immunity
V
1500
200
mA
Notes:
(1)All
voltage values, except the differential voltage are with respect to the network ground terminal.
(2)Differential
voltages are the non-inverting input terminal with respect to the inverting input terminal. See Section
4.7 for the precautions to follow when using the TSX711 with a high differential input voltage.
(3)Input
(4)R
th
current must be limited by a resistor in series with the inputs.
are typical values.
(5)Short-circuits
can cause excessive heating and destructive dissipation.
(6)According
to JEDEC standard JESD22-A114F.
(7)According
to JEDEC standard JESD22-A115A.
(8)According
to ANSI/ESD STM5.3.1
Table 2: Operating conditions
Symbol
4/25
Parameter
VCC
Supply voltage
Vicm
Common mode input voltage range
Toper
Operating free air temperature range
Value
2.7 to 16
DocID026747 Rev 3
VCC- - 0.1 to VCC+ + 0.1
-40 to +125
Unit
V
°C
TSX7191, TSX7191A
3
Electrical characteristics
Electrical characteristics
Table 3: Electrical characteristics at VCC+ = +4 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and
RL > 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Vio
ΔVio/ΔT
ΔVio
Iib
Parameter
Input offset voltage
Long term input offset
voltage drift (2)
Input bias current (1)
Input offset current
RIN
Input resistance
CIN
Input capacitance
Avd
Typ.
(1)
Common mode rejection
ratio 20 log (ΔVic/ΔVio)
Large signal voltage gain
High level output voltage
(voltage drop from VCC+)
200
Tmin < Top < +85 °C
365
Tmin < Top < +125 °C
450
TSX7191A, Vicm = VCC/2
100
Tmin < Top < +85 °C
265
Tmin < Top < +125 °C
350
2.5
1
Vout = VCC/2
1
Tmin < Top < Tmax
μV
µV/°C
nV
month
1
Tmin < Top < Tmax
84
Tmin < Top < Tmax
83
Vicm = -0.1 to 2 V, Vout = VCC/2
100
Tmin < Top < Tmax
94
RL= 2 kΩ, Vout = 0.3 to 3.7 V
110
Tmin < Top < Tmax
96
RL= 10 kΩ, Vout = 0.2 to 3.8 V
110
Tmin < Top < Tmax
96
TΩ
12.5
pF
102
122
DocID026747 Rev 3
dB
136
140
28
50
60
6
15
20
23
Tmin < Top < Tmax
Tmin < Top < Tmax
pA
1
Tmin < Top < Tmax
RL= 10 kΩ tο VCC/2
50
200
Vicm = -0.1 to 4.1 V, Vout = VCC/2
RL= 10 kΩ tο VCC/2
50
200
Vout = VCC/2
RL= 2 kΩ tο VCC/2
Low level output voltage
Unit
---------------------------
T = 25 °C
Tmin < Top < Tmax
VOL
Max.
TSX7191, Vicm = VCC/2
RL= 2 kΩ to VCC/2
VOH
Min.
Input offset voltage drift (1)
Iio
CMRR
Conditions
50
mV
60
5
15
20
5/25
Electrical characteristics
Symbol
Parameter
Isink
Iout
Isource
ICC
TSX7191, TSX7191A
Supply current per amplifier
Conditions
Min.
Typ.
Vout = VCC
35
45
Tmin < Top < Tmax
20
Vout = 0 V
35
Tmin < Top < Tmax
20
No load, Vout = VCC/2
RL = 10 kΩ, CL = 100 pF
ɸm
Phase margin
Gain = 10, RL = 10 kΩ,
CL = 100 pF
SRn
Negative slew rate
SRp
en
THD+N
Positive slew rate
570
Unit
mA
45
Tmin < Top < Tmax
Gain bandwidth product
GBP
Max.
800
μA
900
5
Av = 10, Vout = 3 VPP, 10 % to
90 %
1.3
Tmin < Top < Tmax
1.0
Av = 10, Vout = 3 VPP, 10 % to
90 %
1.5
Tmin < Top < Tmax
1.1
7.7
MHz
42
Degrees
2.3
V/μs
2.5
f = 1 kHz
22
Equivalent input noise
voltage
f = 10 kHz
19
Total harmonic distortion +
noise
f =1 kHz, Av = 10, RL= 10 kΩ,
BW = 22 kHz, Vout = 3VPP
nV
-----------Hz
0.003
Notes:
(1)Maximum
values are guaranteed by design.
(2)Typical
value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.6).
6/25
DocID026747 Rev 3
%
TSX7191, TSX7191A
Electrical characteristics
Table 4: Electrical characteristics at VCC+ = +10 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and
RL > 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Vio
ΔVio/ΔT
ΔVio
Iib
Parameter
Conditions
Input offset voltage
Input offset voltage drift
Input bias current (1)
Input offset current
RIN
Input resistance
CIN
Input capacitance
(1)
Avd
Common mode rejection
ratio 20 log (ΔVic/ΔVio)
Large signal voltage gain
200
Tmin < Top < +85 °C
365
Tmin < Top < +125 °C
450
TSX7191A, Vicm = VCC/2
100
Tmin < Top < +85 °C
265
Tmin < Top < +125 °C
350
2.5
T = 25 °C
25
Vout = VCC/2
1
Tmin < Top < Tmax
Vout = VCC/2
1
Tmin < Top < Tmax
High level output voltage
(voltage drop from VCC+)
90
Tmin < Top < Tmax
86
Vicm = -0.1 to 8 V, Vout = VCC/2
105
Tmin < Top < Tmax
95
RL= 2 kΩ, Vout = 0.3 to 9.7 V
110
Tmin < Top < Tmax
100
RL= 10 kΩ, Vout = 0.2 to 9.8 V
110
Tmin < Top < Tmax
100
Iout
Isource
50
50
pA
12.5
pF
102
117
dB
140
Tmin < Top < Tmax
70
80
RL= 10 kΩ tο VCC/2
10
30
40
42
Tmin < Top < Tmax
70
mV
80
RL= 10 kΩ tο VCC/2
9
30
40
Vout = VCC
50
Tmin < Top < Tmax
40
Vout = 0 V
50
Tmin < Top < Tmax
40
DocID026747 Rev 3
nV
month
TΩ
Tmin < Top < Tmax
Isink
μV/°C
1
45
RL= 2 kΩ tο VCC/2
Low level output voltage
μV
200
Tmin < Top < Tmax
VOL
Unit
---------------------------
200
RL= 2 kΩ tο VCC/2
VOH
Max.
TSX7191, Vicm = VCC/2
Vicm = -0.1 to 10.1 V, Vout = VCC/2
CMRR
Typ.
(1)
Long term input offset
voltage drift (2)
Iio
Min.
70
69
mA
7/25
Electrical characteristics
Symbol
Parameter
ICC
Supply current per amplifier
TSX7191, TSX7191A
Conditions
Min.
No load, Vout = VCC/2
ɸm
Phase margin
G = 10, RL = 10 kΩ, CL = 100 pF
SRn
Negative slew rate
Av = 10, Vout = 8 VPP, 10 % to
90 %
1.3
Tmin < Top < Tmax
1.0
Av = 10, Vout = 8 VPP, 10 % to
90 %
1.5
Tmin < Top < Tmax
1.1
en
THD+N
Positive slew rate
630
850
Unit
μA
1000
RL = 10 kΩ, CL = 100 pF
SRp
Max.
Tmin < Top < Tmax
Gain bandwidth product
GBP
Typ.
5
9
MHz
48
Degrees
2.3
V/μs
2.5
f = 1 kHz
22
Equivalent input noise
voltage
f = 10 kHz
19
Total harmonic distortion +
noise
f = 1 kHz, Av = 10, RL= 10 kΩ,
BW = 22 kHz, Vout = 9 VPP
nV
-----------Hz
0.0001
Notes:
(1)Maximum
values are guaranteed by design.
(2)Typical
value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.6).
8/25
DocID026747 Rev 3
%
TSX7191, TSX7191A
Electrical characteristics
Table 5: Electrical characteristics at VCC+ = +16 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and
RL > 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Vio
ΔVio/ΔT
ΔVio
Iib
Parameter
Conditions
Input offset voltage
Input offset voltage drift
Input bias current (1)
Input offset current
RIN
Input resistance
CIN
Input capacitance
(1)
SVRR
Avd
Common mode rejection
ratio 20 log (ΔVicm/ΔVio)
Supply voltage rejection
ratio 20 log (ΔVcc/ΔVio)
Large signal voltage gain
200
Tmin < Top < +85 °C
365
Tmin < Top < +125 °C
450
TSX7191A, Vicm = VCC/2
100
Tmin < Top < +85 °C
265
Tmin < Top < +125 °C
350
2.5
T = 25 °C
High level output voltage
(voltage drop from VCC+)
1
Tmin < Top < Tmax
1
Tmin < Top < Tmax
94
90
Vicm = -0.1 to 14 V, Vout = VCC/2
110
Tmin < Top < Tmax
96
Vcc = 4 to 16 V
100
Tmin < Top < Tmax
90
RL= 2 kΩ, Vout = 0.3 to 15.7 V
110
Tmin < Top < Tmax
100
RL= 10 kΩ, Vout = 0.2 to 15.8 V
110
Tmin < Top < Tmax
100
Low level output voltage
Tmin < Top < Tmax
DocID026747 Rev 3
pA
12.5
pF
113
116
131
dB
146
149
100
130
150
16
40
50
70
Tmin < Top < Tmax
RL= 10 kΩ
50
TΩ
Tmin < Top < Tmax
VOL
50
1
Tmin < Top < Tmax
RL= 2 kΩ
μV/°C
200
Tmin < Top < Tmax
RL= 10 kΩ
μV
nV
month
200
Vout = VCC/2
Unit
---------------------------
500
Vout = VCC/2
RL= 2 kΩ
VOH
Max.
TSX7191, Vicm = VCC/2
Vicm = -0.1 to 16.1 V, Vout = VCC/2
CMRR
Typ.
(1)
Long term input offset
voltage drift (2)
Iio
Min.
130
mV
150
15
40
50
9/25
Electrical characteristics
Symbol
Parameter
Isink
Iout
Isource
ICC
TSX7191, TSX7191A
Supply current per amplifier
Conditions
Min.
Typ.
Vout = VCC
50
71
Tmin < Top < Tmax
45
Vout = 0 V
50
Tmin < Top < Tmax
45
No load, Vout = VCC/2
660
ɸm
Phase margin
G = 10, RL = 10 kΩ, CL = 100 pF
SRn
Negative slew rate
Av = 10, Vout = 10 VPP, 10 % to
90 %
1.5
Tmin < Top < Tmax
1.1
Av = 10, Vout = 10 VPP, 10 % to
90 %
1.5
Tmin < Top < Tmax
1.1
en
THD+N
Positive slew rate
900
μA
1000
RL = 10 kΩ, CL = 100 pF
SRp
Unit
mA
68
Tmin < Top < Tmax
Gain bandwidth product
GBP
Max.
5
8.5
MHz
51
Degrees
2.4
V/μs
2.5
f = 1 kHz
22
Equivalent input noise
voltage
f = 10 kHz
19
Total harmonic distortion +
Noise
f = 1 kHz, Av = 10, RL= 10 kΩ,
BW = 22 kHz, Vout = 10 VPP
nV
-----------Hz
0.0001
Notes:
(1)Maximum
values are guaranteed by design.
(2)Typical
value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.6).
10/25
DocID026747 Rev 3
%
TSX7191, TSX7191A
Electrical characteristics
Figure 2: Supply current vs. supply voltage
Figure 3: Input offset voltage distribution at VCC = 16 V
Figure 4: Input offset voltage distribution at VCC = 4 V
Figure 5: Input offset voltage vs. temperature at
VCC = 16 V
600
Vio limit
Input offset voltage (µV)
400
200
0
-200
-400
-600
-40
Figure 6: Input offset voltage drift population
Vcc=16V
Vicm=8V
-20
0
20
40
60
Temperature (°C)
80
100
120
Figure 7: Input offset voltage vs. supply voltage at
VICM = 0 V
DocID026747 Rev 3
11/25
Electrical characteristics
TSX7191, TSX7191A
Figure 8: Input offset voltage vs. common mode voltage
at VCC = 2.7 V
Figure 9: Input offset voltage vs. common mode voltage
at VCC = 16 V
Figure 10: Output current vs. output voltage at
VCC = 2.7 V
Figure 11: Output current vs. output voltage at
VCC = 16 V
Figure 12: Output low voltage vs. supply voltage
Figure 13: Output high voltage (drop from VCC+) vs.
supply voltage
12/25
DocID026747 Rev 3
TSX7191, TSX7191A
Electrical characteristics
Figure 15: Slew rate vs. supply voltage
Figure 14: Output voltage vs. input voltage close to the
rail at VCC = 16 V
3.0
16.00
15.95
2.0
15.90
15.80
Slew rate (V/µs)
Output voltage (V)
15.85
15.75
0.20
0.15
0.10
Vcc=16V
Gain=10
0.05
1.0
0.0
T=125°C
T=25°C
T=-40°C
Vicm=Vcc/2
Vload=Vcc/2
Gain=10
Rl=10kΩ
Cl=100pF
-1.0
-2.0
1.600
-3.0
4
Input voltage (V)
2
0.2
T=25°C
0
0.0
-2
T=125°C
-0.2
0.8
6
0.6
4
0.4
2
-0.2
-4
Vcc=16V
-0.4
Vicm=Vcc/2
-0.6
Gain=11
Rl=10k Ω
-0.8
Cl=100pF
-1.0
8
-8
-0.8
-8
-1.0
-10
4
Time (µs)
6
8
-10
0
4
6
Time (µs)
8
10
4
Time (µs)
6
10
0.20
Gain=101
Rl=10kΩ
0.16
Cl=100pF
T=25°C
0.12
8
Vin
-100
12
Output voltage (mV)
-50
2
2
50
0
-5
T=-40°C
Figure 19: Recovery behavior after a negative step on
the input
100
Vcc=16V
Vicm=8V
Rl=10k Ω
Cl=100pF
Gain=10
T=25°C
0
T=25°C
-6
0
10
5
0.0
-2
-0.6
2
0.2
T=125°C
0
-6
Figure 18: Response to a small input voltage step
Input voltage (mV)
1.0
8
-0.4
0
16
10
-4
-10
14
Input Voltage (V)
4
Output Voltage (V)
Vcc=16V
0.8
Vicm=Vcc/2
Gain=11
0.6
Rl=10kΩ
0.4
Cl=100pF
T=-40°C
Output Voltage (V)
Output Voltage (V)
6
Input Voltage (V)
1.0
8
8
10
12
Supply Voltage (V)
Figure 17: Positive slew rate at VCC = 16 V
Figure 16: Negative slew rate at VCC = 16 V
10
6
6
Vcc=±8V
4
0.08
Vcc=±1.35V
2
0.04
0
0.00
-2
-10
DocID026747 Rev 3
0
10
20
Time (µs)
30
Input voltage (V)
1.595
1.590
1.585
1.580
1.575
0.020
0.015
0.010
0.005
0.000
0.00
-0.04
40
13/25
Electrical characteristics
TSX7191, TSX7191A
2
0.04
0
0.00
Figure 21: Bode diagram at VCC = 2.7 V
50
300
40
240
Gain
-0.04
Vcc=±1.35V
-4
-0.08
Vcc=±8V
-6
-0.12
Gain=101
Rl=10kΩ
Cl=100pF
T=25°C
Vin
-8
-10
-10
0
10
20
Time (µs)
0
0
Vcc=2.7V
Vicm=1.35V
Rl=10kΩ
Cl=100pF
Gain=101
-30
-60
-120
-180
T=125°C
-40
1k
10k
100k
-240
10M
1M
Figure 23: Power supply rejection ratio (PSRR) vs.
frequency
100
300
40
240
+
PSRR
Gain
30
T=25°C
80
180
60
Phase
0
0
Vcc=16V
Vicm=8V
Rl=10kΩ
Cl=100pF
Gain=101
-10
-20
-30
-60
-120
60
40
20
-180
T=125°C
-40
1k
PSRR (dB)
120
T=-40°C
10
Phase (°)
20
10k
100k
1M
-240
10M
0
10
Vcc=16V
Vicm=8V
Gain=10
Rl=10kΩ
Cl=100pF
Vosc=20mVPP
T=25°C
100
Frequency (Hz)
Figure 24: Output overshoot vs. capacitive load
Unstable
1000
Rf=9.1kΩ
50
Rf=91kΩ
25
0
10
1k
Frequency (Hz)
10k
100k
10000
Vcc=16V
Vicm=Vcc/2
Rl=10kΩ
Vin=10mVpp
Gain=10
T=25°C
Output impedance(Ω)
75
-
PSRR
Figure 25: Output impedance vs. frequency in closed
loop configuration
100
Overshoot (%)
60
Phase
Frequency (Hz)
50
Gain (dB)
120
-20
-0.16
Figure 22: Bode diagram at VCC = 16 V
14/25
180
T=-40°C
10
-10
-0.20
40
30
T=25°C
20
Gain (dB)
Output Voltage (V)
-2
Input voltage (V)
30
Phase (°)
Figure 20: Recovery behavior after a positive step on
the input
100
Cload (pF)
1000
Vicm=Vcc/2
Gain=1
Vosc=30mVRMS
T=25°C
100
Vcc=16V
10
Vcc=2.7V
1
0.1
1k
DocID026747 Rev 3
10k
100k
Frequency (Hz)
1M
10M
TSX7191, TSX7191A
Electrical characteristics
Figure 26: THD + N vs. frequency
Figure 27: THD + N vs. output voltage
1
1
Rl=2kΩ
0.1
Rl=2kΩ
Rl=10kΩ
0.01
THD + N (%)
THD + N (%)
0.1
Vcc=16V
Vicm=8V
Gain=10
Vout=10Vpp
BW=80kHz
T=25°C
Rl=100kΩ
1000
Frequency (Hz)
0.1
1
Output Voltage (Vpp)
10
Figure 29: 0.1 to 10Hz noise
6
120
Vcc=16V
Vicm=Vcc/2
T=25°C
100
80
60
40
Vcc=16V
4 Vicm=8V
T=25°C
Input voltage noise (µV)
Equivalent Input Noise Voltage (nV/√ Hz)
Vcc=16V
Vicm=8V
Gain=10
f=1kHz
BW=22kHz
T=25°C
1E-4
0.01
10000
Figure 28: Noise vs. frequency
2
0
-2
-4
20
0
10
Rl=100kΩ
0.01
1E-3
1E-3
100
Rl=10kΩ
100
1k
Frequency (Hz)
10k
-6
0
2
4
6
8
10
Time (s)
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Application information
TSX7191, TSX7191A
4
Application information
4.1
Operating voltages
The TSX7191, TSX7191A device can operate from 2.7 to 16 V. The parameters are fully
specified for 4 V, 10 V, and 16 V power supplies. However, the parameters are very stable
in the full VCC range. Additionally, the main specifications are guaranteed in extended
temperature ranges from -40 to +125 °C.
4.2
Input pin voltage ranges
The TSX7191, TSX7191A device has internal ESD diode protection on the inputs. These
diodes are connected between the input and each supply rail to protect the input MOSFETs
from electrical discharge.
If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become
conductive and excessive current can flow through them. Without limitation this over
current can damage the device.
In this case, it is important to limit the current to 10 mA, by adding resistance on the input
pin, as described in Figure 30.
Figure 30: Input current limitation
9R2
R2
Vin
4.3
Vcc
R1
Rail-to-rail input
The TSX7191, TSX7191A device has a rail-to-rail input, and the input common mode range
is extended from VCC- - 0.1 V to VCC+ + 0.1 V.
4.4
Rail-to-rail output
The operational amplifier output levels can go close to the rails: to a maximum of 30 mV
above and below the rail when connected to a 10 kΩ resistive load to V CC/2.
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4.5
Application information
Input offset voltage drift over temperature
The maximum input voltage drift variation over temperature is defined as the offset
variation related to the offset value measured at 25 °C. The operational amplifier is one of
the main circuits of the signal conditioning chain, and the amplifier input offset is a major
contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated
during production at application level. The maximum input voltage drift over temperature
enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
Equation 1
∆Vio
V T – Vio 25 °C
= max io
∆T
T – 25 °C
Where T = -40 °C and 125 °C.
The TSX7191, TSX7191A datasheet maximum value is guaranteed by measurements on a
representative sample size ensuring a Cpk (process capability index) greater than 1.3.
4.6
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
Voltage acceleration, by changing the applied voltage
Temperature acceleration, by changing the die temperature (below the maximum
junction temperature allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2.
Equation 2
AFV = e
β . V S – VU
Where:
AFV is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in
Equation 3.
Equation 3
AFT = e
Ea
1
1
------ .
–
k
TU TS
Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate
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Application information
TSX7191, TSX7191A
k is the Boltzmann constant (8.6173 x 10-5 eV.K-1)
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die under temperature stress (K)
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and
the temperature acceleration factor (Equation 4).
Equation 4
AF = AFT × AFV
AF is calculated using the temperature and voltage defined in the mission profile of the
product. The AF value can then be used in Equation 5 to calculate the number of months of
use equivalent to 1000 hours of reliable stress duration.
Equation 5
Months = AF × 1000 h × 12 months / 24 h × 365.25 days
To evaluate the op amp reliability, a follower stress condition is used where VCC is defined
as a function of the maximum operating voltage and the absolute maximum rating (as
recommended by JEDEC rules).
The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at
different measurement conditions (see Equation 6).
Equation 6
VCC = maxVop with Vicm = VCC 2
The long term drift parameter (ΔVio), estimating the reliability performance of the product, is
obtained using the ratio of the Vio (input offset voltage value) drift over the square root of
the calculated number of months (Equation 7).
Equation 7
∆Vio =
Vio dr ift
month s
Where Vio drift is the measured drift value in the specified test conditions after 1000 h
stress duration.
4.7
High values of input differential voltage
In a closed loop configuration, which represents the typical use of an op amp, the input
differential voltage is low (close to Vio). However, some specific conditions can lead to
higher input differential values, such as:
operation in an output saturation state
operation at speeds higher than the device bandwidth, with output voltage dynamics
limited by slew rate.
use of the amplifier in a comparator configuration, hence in open loop
Use of the TSX7191, TSX7191A in comparator configuration, especially combined with
high temperature and long duration can create a permanent drift of V io.
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TSX7191, TSX7191A
4.8
Application information
Capacitive load
Driving large capacitive loads can cause stability problems. Increasing the load
capacitance produces gain peaking in the frequency response, with overshoot and ringing
in the step response. It is usually considered that with a gain peaking higher than 2.3 dB an
op amp might become unstable.
Generally, the unity gain configuration is the worst case for stability and the ability to drive
large capacitive loads.
Figure 31 shows the serial resistor that must be added to the output, to make a system
stable. Figure 32 shows the test configuration using an isolation resistor, Riso.
Figure 31: Stability criteria with a serial resistor at different supply voltages
Figure 32: Test configuration for Riso
100kΩ
Vcc+
11kΩ
Riso
Vout
Vin
Vcc-
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Cl
10kΩ
19/25
Application information
4.9
TSX7191, TSX7191A
PCB layout recommendations
Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier,
load, and power supply. The power and ground traces are critical as they must provide
adequate energy and grounding for all circuits. The best practice is to use short and wide
PCB traces to minimize voltage drops and parasitic inductance.
In addition, to minimize parasitic impedance over the entire surface, a multi-via technique
that connects the bottom and top layer ground planes together in many locations is often
used.
The copper traces that connect the output pins to the load and supply pins should be as
wide as possible to minimize trace resistance.
4.10
Optimized application recommendation
It is recommended to place a 22 nF capacitor as close as possible to the supply pin. A
good decoupling will help to reduce electromagnetic interference impact.
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5
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID026747 Rev 3
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Package information
5.1
TSX7191, TSX7191A
SOT23-5 package information
Figure 33: SOT23-5 package outline
Table 6: SOT23-5 mechanical data
Dimensions
Ref.
A
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
0.90
1.20
1.45
0.035
0.047
0.057
A1
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Inches
0.15
0.006
A2
0.90
1.05
1.30
0.035
0.041
0.051
B
0.35
0.40
0.50
0.014
0.016
0.020
C
0.09
0.15
0.20
0.004
0.006
0.008
D
2.80
2.90
3.00
0.110
0.114
0.118
D1
1.90
0.075
e
0.95
0.037
E
2.60
2.80
3.00
0.102
0.110
0.118
F
1.50
1.60
1.75
0.059
0.063
0.069
L
0.10
0.35
0.60
0.004
0.014
0.024
K
0 degrees
10 degrees
0 degrees
DocID026747 Rev 3
10 degrees
TSX7191, TSX7191A
6
Ordering information
Ordering information
Table 7: Order codes
Order code
Temperature
range
Package
Packaging
TSX7191ILT
K34
TSX7191AILT
TSX7191IYLT
Marking
(1)
-40 to +125 °C
SΟΤ23-5
TSX7191AIYLT (1)
Tape and reel
K196
K199
K200
Notes:
(1)Qualification
and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001
& Q 002 or equivalent are on-going.
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Revision history
7
TSX7191, TSX7191A
Revision history
Table 8: Document revision history
24/25
Date
Revision
Changes
29-Sep-2014
1
Initial release
06-Jan-2015
2
Features: updated "stable when used with gain"
feature.
Applications: removed "DAC buffer"
Electrical characteristics: replaced Figure 14
17-Mar-2017
3
Added part number TSX7191A
DocID026747 Rev 3
TSX7191, TSX7191A
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