TSX7192IYDT

TSX7192 Low-power, precision, rail-to-rail, 9.0 MHz, 16 V operational amplifiers Datasheet - production data Description The TSX7192 dual, operational amplifier (op amp) offers high precision functioning with low input offset voltage down to a maximum of 200 µV at 25 °C. In addition, its rail-to-rail input and output functionality allows this product to be used on full range input and output without limitation. This is particularly useful for a lowvoltage supply such as 2.7 V that the TSX7192 is able to operate with. Features • • • • • • • • • • Low input offset voltage: 200 µV max. Rail-to-rail input and output Low current consumption: 850 µA max. Gain bandwidth product: 9 MHz Low supply voltage: 2.7 to 16 V Stable when used with Gain ≥ 10 Low input bias current: 50 pA max. High ESD tolerance: 4 kV HBM Extended temp. range: -40 °C to 125 °C Automotive qualification Related products • • • • • See the TSX7191 for single op amp version See the TSX712 for lower speeds with similar precision See the TSX562 for low-power features See the TSX632 for micro-power features See the TSX922 for higher speeds Thus, the TSX7192 has the great advantage of offering a large span of supply voltages, ranging from 2.7 V to 16 V. It can be used in multiple applications with a unique reference. Low input bias current performance makes the TSX7192 perfect when used for signal conditioning in sensor interface applications. In addition, low-side and high-side current measurements can be easily made thanks to railto-rail functionality. The TSX7192 is a decompensated amplifier and must be used with a gain greater than 10 to ensure stability. High ESD tolerance (4 kV HBM) and a wide temperature range are also good arguments to use the TSX7192 in the automotive market segment. Applications • • • • • Battery-powered instrumentation Instrumentation amplifier Active filtering High-impedance sensor interface Current sensing (high and low side) March 2015 DocID027196 Rev 1 This is information on a product in full production. 1/25 www.st.com Contents TSX7192 Contents 1 Package pin connections................................................................ 3 2 Absolute maximum ratings and operating conditions ................. 4 3 4 Electrical characteristics ................................................................ 5 Application information ................................................................ 15 5 4.1 Operating voltages .......................................................................... 15 4.2 Input pin voltage ranges .................................................................. 15 4.3 Rail-to-rail input ............................................................................... 15 4.4 Rail-to-rail output ............................................................................. 15 4.5 Input offset voltage drift over temperature ....................................... 16 4.6 Long term input offset voltage drift .................................................. 16 4.7 High values of input differential voltage........................................... 17 4.8 Capacitive load................................................................................ 18 4.9 PCB layout recommendations ......................................................... 19 4.10 Optimized application recommendation .......................................... 19 Package information ..................................................................... 20 5.1 MiniSO8 package information ......................................................... 21 5.2 SO8 package information ................................................................ 22 6 Ordering information..................................................................... 23 7 Revision history ............................................................................ 24 2/25 DocID027196 Rev 1 TSX7192 1 Package pin connections Package pin connections Figure 1: Pin connections (top view) MiniSO8 and SO8 DocID027196 Rev 1 3/25 Absolute maximum ratings and operating conditions 2 TSX7192 Absolute maximum ratings and operating conditions Table 1: Absolute maximum ratings (AMR) Symbol VCC Parameter Supply voltage Vid Differential input voltage Vin Input voltage Iin Tstg Tj Input current Unit 18 V ±VCC mV (VCC-) - 0.2 to (VCC+) + 0.2 V 10 mA (2) (3) Storage temperature -65 to 150 °C Maximum junction temperature HBM: human body model ESD Value (1) MM: machine model 150 (4) 4000 (5) CDM: charged device model 100 (6) V 1500 Latch-up immunity 200 mA Notes: (1) All voltage values, except the differential voltage are with respect to the network ground terminal. (2) Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. See Section 4.7 for precautions to follow when using the TSX7192 with high differential input voltage. (3) (4) (5) (6) Input current must be limited by a resistor in series with the inputs. According to JEDEC standard JESD22-A114F. According to JEDEC standard JESD22-A115A. According to ANSI/ESD STM5.3.1. Table 2: Operating conditions Symbol 4/25 Parameter VCC Supply voltage Vicm Common mode input voltage range Toper Operating free air temperature range Value 2.7 to 16 DocID027196 Rev 1 (VCC- ) - 0.1 to (VCC+) + 0.1 -40 to 125 Unit V °C TSX7192 3 Electrical characteristics Electrical characteristics Table 3: Electrical characteristics at VCC+ = 4 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL > 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Vio ΔVio/ΔT ΔVio Iib Parameter Input offset voltage Input offset voltage drift Input bias current (1) Input offset current RIN Input resistance CIN Input capacitance Avd Min. 200 Tmin < Top < 85 °C 365 Tmin < Top < 125 °C 450 2.5 Common mode rejection ratio 20 log (ΔVic/ΔVio) Large signal voltage gain High level output voltage (voltage drop from VCC+) 1 Vout = VCC/2 1 Vout = VCC/2 1 Tmin < Top < Tmax Iout Isource ICC Supply current per amplifier Vicm = -0.1 to 4.1 V, Vout = VCC/2 80 Tmin < Top < Tmax 78 Vicm = -0.1 to 2 V, Vout = VCC/2 91 Tmin < Top < Tmax 86 RL= 2 kΩ, Vout = 0.3 to 3.7 V 110 Tmin < Top < Tmax 96 RL= 10 kΩ, Vout = 0.2 to 3.8 V 110 Tmin < Top < Tmax 96 pF 98 103 dB 136 140 50 60 6 15 20 23 Tmin < Top < Tmax 50 mV 60 RL= 10 kΩ tο VCC/2 5 15 20 Vout = VCC 25 Tmin < Top < Tmax 15 Vout = 0 V 35 Tmin < Top < Tmax 20 DocID027196 Rev 1 pA 12.5 28 RL= 10 kΩ tο VCC/2 Tmin < Top < Tmax 50 TΩ Tmin < Top < Tmax No load, Vout = VCC/2 50 1 Tmin < Top < Tmax Isink µV/°C 200 RL= 2 kΩ tο VCC/2 Low level output voltage μV nV month 200 Tmin < Top < Tmax VOL Unit --------------------------- T = 25 °C Tmin < Top < Tmax (1) Max. T = 25 °C RL= 2 kΩ to VCC/2 VOH Typ. (1) Long term input offset (2) voltage drift Iio CMRR Conditions 37 mA 45 570 800 900 μA 5/25 Electrical characteristics Symbol TSX7192 Parameter Conditions Gain bandwidth product RL = 10 kΩ, CL = 100 pF ɸm Phase margin Gain = 10, RL = 10 kΩ, CL = 100 pF SRn Negative slew rate GBP SRp en THD+N Positive slew rate Min. Typ. 5 7.7 MHz 42 Degrees Av = 10, Vout = 3 VPP, 10 % to 90 % 1.3 Tmin < Top < Tmax 1.0 Av = 10, Vout = 3 VPP, 10 % to 90 % 1.5 Tmin < Top < Tmax 1.1 Max. Unit 2.3 V/μs 2.5 f = 1 kHz 22 Equivalent input noise voltage f = 10 kHz 19 Total harmonic distortion + noise f =1 kHz, Av = 10, RL= 10 kΩ, BW = 22 kHz, Vout = 3VPP nV -----------Hz 0.003 % Notes: (1) Maximum values are guaranteed by design. (2) Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.6). Table 4: Electrical characteristics at VCC+ = 10 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL > 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Vio ΔVio/ΔT ΔVio Iib Parameter Input offset voltage Input offset voltage drift Input bias current (1) Input offset current RIN Input resistance CIN Input capacitance Avd 6/25 Min. Typ. 200 Tmin < Top < 85 °C 365 Tmin < Top < 125 °C 450 2.5 Common mode rejection ratio 20 log (ΔVic/ΔVio) Large signal voltage gain Unit μV μV/°C nV month --------------------------- T = 25 °C 25 Vout = VCC/2 1 Tmin < Top < Tmax (1) Max. T = 25 °C (1) Long term input offset (2) voltage drift Iio CMRR Conditions 200 Vout = VCC/2 1 Tmin < Top < Tmax 50 pA 200 Vicm = -0.1 to 10.1 V, Vout = VCC/2 88 Tmin < Top < Tmax 84 Vicm = -0.1 to 8 V, Vout = VCC/2 98 Tmin < Top < Tmax 92 RL= 2 kΩ, Vout = 0.3 to 9.7 V 110 Tmin < Top < Tmax 100 DocID027196 Rev 1 50 1 TΩ 12.5 pF 100 106 140 dB TSX7192 Electrical characteristics Symbol Avd Parameter Large signal voltage gain Conditions Min. RL= 10 kΩ, Vout = 0.2 to 9.8 V 110 Tmin < Top < Tmax 100 RL= 2 kΩ tο VCC/2 VOH High level output voltage (voltage drop from VCC+) Typ. 45 Tmin < Top < Tmax RL= 10 kΩ tο VCC/2 10 Iout Isource ICC Supply current per amplifier 42 Tmin < Top < Tmax RL= 10 kΩ tο VCC/2 9 Vout = VCC 30 Tmin < Top < Tmax 15 Vout = 0 V 50 Tmin < Top < Tmax 40 No load, Vout = VCC/2 850 1000 G = 10, RL = 10 kΩ, CL = 100 pF SRn Negative slew rate Av = 10, Vout = 8 VPP, 10 % to 90 % 1.3 Tmin < Top < Tmax 1.0 Av = 10, Vout = 8 VPP, 10 % to 90 % 1.5 Tmin < Top < Tmax 1.1 THD+N mA 69 Tmin < Top < Tmax Phase margin en 30 39 630 ɸm Positive slew rate mV 40 RL = 10 kΩ, CL = 100 pF SRp 70 80 Gain bandwidth product GBP 30 40 Tmin < Top < Tmax Isink 70 80 RL= 2 kΩ tο VCC/2 Low level output voltage Unit dB Tmin < Top < Tmax VOL Max. 5 μA 9 MHz 48 Degrees 2.3 V/μs 2.5 f = 1 kHz 22 Equivalent input noise voltage f = 10 kHz 19 Total harmonic distortion + noise f = 1 kHz, Av = 10, RL= 10 kΩ, BW = 22 kHz, Vout = 9 VPP 0.0001 nV -----------Hz % Notes: (1) Maximum values are guaranteed by design. (2) Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.6). DocID027196 Rev 1 7/25 Electrical characteristics TSX7192 Table 5: Electrical characteristics at VCC+ = 16 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL > 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Vio ΔVio/ΔT ΔVio Parameter Input offset voltage Input offset voltage drift (1) Input bias current Iio Input offset current RIN Input resistance CIN Input capacitance SVRR Avd Min. 200 Tmin < Top < 85 °C 365 Tmin < Top < 125 °C 450 2.5 T = 25 °C Vout = VCC/2 1 Vout = VCC/2 1 Tmin < Top < Tmax Common mode rejection ratio 20 log (ΔVicm/ΔVio) Tmin < Top < Tmax 90 Vicm = -0.1 to 14 V, Vout = VCC/2 100 Tmin < Top < Tmax 90 Supply voltage rejection ratio 20 log (ΔVcc/ΔVio) Vcc = 4 to 16 V 100 Tmin < Top < Tmax 90 RL= 2 kΩ, Vout = 0.3 to 15.7 V 110 Tmin < Top < Tmax 100 RL= 10 kΩ, Vout = 0.2 to 15.8 V 110 Tmin < Top < Tmax 100 TΩ 12.5 pF 107 107 131 Iout Isource ICC 8/25 Supply current per amplifier 149 Tmin < Top < Tmax 16 70 130 mV 150 RL= 10 kΩ 15 40 50 Vout = VCC 30 Tmin < Top < Tmax 15 Vout = 0 V 50 Tmin < Top < Tmax 45 DocID027196 Rev 1 40 50 Tmin < Top < Tmax Tmin < Top < Tmax 130 150 RL= 10 kΩ No load, Vout = VCC/2 dB 146 Tmin < Top < Tmax Isink pA 1 100 RL= 2 kΩ Low level output voltage 50 200 Tmin < Top < Tmax VOL μV/°C 50 200 94 High level output voltage (voltage drop from VCC+) μV nV month 500 Vicm = -0.1 to 16.1 V, Vout = VCC/2 Large signal voltage gain Unit --------------------------- Tmin < Top < Tmax (1) Max. T = 25 °C RL= 2 kΩ VOH Typ. (1) Long term input offset (2) voltage drift Iib CMRR Conditions 40 mA 68 660 900 1000 μA TSX7192 Symbol Electrical characteristics Parameter Conditions Min. Typ. 5 8.5 MHz 51 Degrees Gain bandwidth product RL = 10 kΩ, CL = 100 pF ɸm Phase margin G = 10, RL = 10 kΩ, CL = 100 pF SRn Negative slew rate Av = 10, Vout = 10 VPP, 10 % to 90 % 1.5 Tmin < Top < Tmax 1.1 Av = 10, Vout = 10 VPP, 10 % to 90 % 1.5 Tmin < Top < Tmax 1.1 GBP SRp en THD+N Positive slew rate Max. Unit 2.4 V/μs 2.5 f = 1 kHz 22 Equivalent input noise voltage f = 10 kHz 19 Total harmonic distortion + Noise f = 1 kHz, Av = 10, RL= 10 kΩ, BW = 22 kHz, Vout = 10 VPP 0.0001 nV -----------Hz % Notes: (1) Maximum values are guaranteed by design. (2) Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.6). DocID027196 Rev 1 9/25 Electrical characteristics TSX7192 Figure 2: Supply current vs. supply voltage Figure 3: Input offset voltage distribution at VCC = 16 V 20 800 Vcc=16V Vicm=8V T=25°C 15 600 Population (%) Supply Current (µA) Vicm=Vcc/2 T=-40°C 400 T=25°C T=125°C 10 200 0 5 0 10 8 6 Supply Voltage (V) 4 2 12 0 -300 16 14 -200 -150 -100 Input offset voltage (µV) 10 5 150 200 250 300 200 0 -200 -400 -150 -100 -50 0 50 100 150 200 250 -600 -40 300 Vcc=16V Vicm=8V -20 0 Input offset voltage (µV) 20 40 60 Temperature (°C) 80 100 120 Figure 7: Input offset voltage vs. supply voltage at VICM = 0 V Figure 6: Input offset voltage drift population 40 600 Vcc=16V Vicm=8V T=25°C Vicm=0V 400 Input Offset Voltage (µV) 35 30 Population (%) 100 Vio limit 400 15 -200 50 600 Vcc=4V Vicm=2V T=25°C -250 0 Figure 5: Input offset voltage vs. temperature at VCC = 16 V 20 0 -300 -50 Input offset voltage (µV) Figure 4: Input offset voltage distribution at VCC = 4 V Population (%) -250 25 20 15 10 200 0 -200 T=-40°C T=25°C T=125°C -400 5 -600 0 -4 -3 -2 -1 0 1 2 3 4 ∆Vio/∆T (µV/ºC) 10/25 DocID027196 Rev 1 4 6 8 10 12 Supply voltage (V) 14 16 TSX7192 Electrical characteristics Figure 8: Input offset voltage vs. common mode voltage at VCC = 2.7 V Figure 9: Input offset voltage vs. common mode voltage at VCC = 16 V 600 600 Vcc=2.7V 200 0 -200 T=125°C T=25°C T=-40°C 200 0 -200 -600 0.0 0.5 1.0 1.5 2.0 Input Common Mode Voltage (V) 2.5 0 2 30.0 15.0 50 Output Current (mA) Sink 75 Vid=-1V 7.5 T=-40°C 0.0 T=25°C T=125°C -7.5 -15.0 -22.5 Source Vid=1V Vcc=2.7V -30.0 0.0 0.5 1.0 1.5 2.0 Output Voltage (V) 2.5 Figure 12: Output low voltage vs. supply voltage 0 14 16 T=25°C T=125°C T=-40°C -25 -50 -75 Source Vid=1V Vcc=16V -100 0 2 4 6 8 10 Output Voltage (V) 12 14 16 Figure 13: Output high voltage (drop from VCC+) vs. supply voltage 30 Vid=-0.1V Rl=10kΩ to Vcc/2 Output voltage (from Vcc+) (mV) Output voltage (mV) 4 6 8 10 12 Input Common Mode Voltage (V) 25 30 T=-40°C T=25°C 20 T=125°C 15 10 5 0 T=-40°C 100 Sink 22.5 Vid=-1V 25 T=25°C Figure 11: Output current vs. output voltage at VCC = 16 V Figure 10: Output current vs. output voltage at VCC = 2.7 V Output Current (mA) T=125°C -400 -400 -600 Vcc=16V 400 Input Offset Voltage (µV) Input Offset Voltage (µV) 400 4 6 8 10 12 Supply Voltage (V) 14 16 25 Vid=0.1V Rl=10kΩ to Vcc/2 T=-40°C T=25°C 20 T=125°C 15 10 5 0 DocID027196 Rev 1 4 6 8 10 12 Supply Voltage (V) 14 16 11/25 Electrical characteristics TSX7192 Figure 14: Output voltage vs. input voltage close to the rail at VCC = 16 V Figure 15: Slew rate vs. supply voltage 3.0 16.00 15.95 2.0 15.90 15.80 Slew rate (V/µs) Output voltage (V) 15.85 15.75 0.20 0.15 0.10 Vcc=16V Gain=10 0.05 1.0 0.0 T=25°C T=-40°C Vicm=Vcc/2 Vload=Vcc/2 Gain=10 Rl=10kΩ Cl=100pF T=125°C -1.0 -2.0 1.600 -3.0 2 0.2 T=25°C 0 0.0 -2 T=125°C -0.2 1.0 8 0.8 6 0.6 4 0.4 2 -0.6 -6 -8 -0.8 -8 -1.0 -10 4 Time (µs) 6 8 10 -10 0 12/25 4 6 Time (µs) 8 10 4 Time (µs) 6 10 0.20 Gain=101 Rl=10kΩ 0.16 Cl=100pF T=25°C 0.12 8 Vin -100 12 Output voltage (mV) -50 2 2 50 0 -5 T=-40°C Vcc=16V -0.4 Vicm=Vcc/2 -0.6 Gain=11 Rl=10k Ω -0.8 Cl=100pF -1.0 8 Figure 19: Recovery behavior after a negative step on the input 100 Vcc=16V Vicm=8V Rl=10k Ω Cl=100pF Gain=10 T=25°C 0 T=25°C 0 Figure 18: Response to a small input voltage step 5 -0.2 -4 -6 2 0.0 -2 -0.4 0 0.2 T=125°C 0 -4 -10 Input voltage (mV) 10 Input Voltage (V) T=-40°C 4 Output Voltage (V) Output Voltage (V) 6 Output Voltage (V) 8 Input Voltage (V) 1.0 Vcc=16V 0.8 Vicm=Vcc/2 Gain=11 0.6 Rl=10kΩ 0.4 Cl=100pF 16 Figure 17: Positive slew rate at VCC = 16 V Figure 16: Negative slew rate at VCC = 16 V 10 14 12 10 8 Supply Voltage (V) 6 4 Input voltage (V) 6 Vcc=±8V 4 0.08 Vcc=±1.35V 2 0.04 0 0.00 -2 -10 DocID027196 Rev 1 0 10 20 Time (µs) 30 -0.04 40 Input voltage (V) 1.595 1.590 1.585 1.580 1.575 0.020 0.015 0.010 0.005 0.000 0.00 TSX7192 Electrical characteristics Figure 20: Recovery behavior after a positive step on the input 0.04 300 50 240 40 0 0.00 Gain -4 -0.08 Vcc=±8V -6 -0.12 Gain=101 Rl=10kΩ Cl=100pF T=25°C Vin -8 -10 -10 0 10 20 Time (µs) 10 0 0 Vcc=2.7V Vicm=1.35V Rl=10kΩ Cl=100pF Gain=101 -30 -60 -120 -180 T=125°C -240 10M -40 1k 10k 100k 1M Frequency (Hz) Figure 23: Power supply rejection ratio (PSRR) vs. frequency 100 300 50 240 40 + PSRR Gain 30 T=25°C 80 180 60 Phase 0 0 Vcc=16V Vicm=8V Rl=10kΩ Cl=100pF Gain=101 -10 -20 -30 -60 -120 60 40 20 -180 T=125°C -240 10M -40 1k PSRR (dB) T=-40°C 10 Phase (°) 120 20 100k 10k 1M 0 10 Vcc=16V Vicm=8V Gain=10 Rl=10kΩ Cl=100pF Vosc=20mVPP T=25°C 100 Frequency (Hz) Figure 24: Output overshoot vs. capacitive load Unstable 1000 Rf=9.1kΩ 50 Rf=91kΩ 25 0 10 1k Frequency (Hz) 10k 100k 10000 Vcc=16V Vicm=Vcc/2 Rl=10kΩ Vin=10mVpp Gain=10 T=25°C Output impedance(Ω) 75 - PSRR Figure 25: Output impedance vs. frequency in closed loop configuration 100 Overshoot (%) 60 Phase -20 -0.16 Figure 22: Bode diagram at VCC = 16 V Gain (dB) 120 T=-40°C -10 -0.20 40 30 180 20 Gain (dB) Output Voltage (V) -0.04 Vcc=±1.35V Input voltage (V) 30 -2 T=25°C Phase (°) 2 Figure 21: Bode diagram at VCC = 2.7 V 100 Cload (pF) 1000 Vicm=Vcc/2 Gain=1 Vosc=30mVRMS T=25°C 100 Vcc=16V 10 Vcc=2.7V 1 0.1 1k DocID027196 Rev 1 10k 100k Frequency (Hz) 1M 10M 13/25 Electrical characteristics TSX7192 Figure 26: THD + N vs. frequency Figure 27: THD + N vs. output voltage 1 1 Rl=2kΩ 0.1 Rl=2kΩ Rl=10kΩ 0.01 THD + N (%) THD + N (%) 0.1 Vcc=16V Vicm=8V Gain=10 Vout=10Vpp BW=80kHz T=25°C Rl=100kΩ Figure 28: Noise vs. frequency 6 Vcc=16V Vicm=Vcc/2 T=25°C 100 80 60 40 Vcc=16V 4 Vicm=8V T=25°C Input voltage noise (µV) Equivalent Input Noise Voltage (nV/√ Hz) 14/25 10 1 0.1 Output Voltage (Vpp) Figure 29: 0.1 to 10Hz noise 120 2 0 -2 -4 20 0 10 Vcc=16V Vicm=8V Gain=10 f=1kHz BW=22kHz T=25°C 1E-4 0.01 10000 1000 Frequency (Hz) Rl=100kΩ 0.01 1E-3 1E-3 100 Rl=10kΩ 100 1k Frequency (Hz) 10k -6 0 2 4 6 Time (s) DocID027196 Rev 1 8 10 TSX7192 Application information 4 Application information 4.1 Operating voltages The TSX7192 device can operate from 2.7 to 16 V. The parameters are fully specified for 4 V, 10 V, and 16 V power supplies. However, the parameters are very stable in the full VCC range. Additionally, the main specifications are guaranteed in extended temperature ranges from -40 to +125 °C. 4.2 Input pin voltage ranges The TSX7192 device has internal ESD diode protection on the inputs. These diodes are connected between the input and each supply rail to protect the input MOSFETs from electrical discharge. If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become conductive and excessive current can flow through them. Without limitation this over current can damage the device. In this case, it is important to limit the current to 10 mA, by adding resistance on the input pin, as described in Figure 30. Figure 30: Input current limitation 9R2 R2 Vin 4.3 Vcc R1 Rail-to-rail input The TSX7192 device has a rail-to-rail input, and the input common mode range is extended from VCC- - 0.1 V to VCC+ + 0.1 V. 4.4 Rail-to-rail output The operational amplifier output levels can go close to the rails: to a maximum of 40 mV above and below the rail when connected to a 10 kΩ resistive load to VCC/2. DocID027196 Rev 1 15/25 Application information 4.5 TSX7192 Input offset voltage drift over temperature The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations. The maximum input voltage drift over temperature is computed using Equation 1. Equation 1 ∆V io V ( T ) – V io ( 25 °C ) = ma x io ∆T T – 25 °C Where T = -40 °C and 125 °C. The TSX7192 datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a Cpk (process capability index) greater than 1.3. 4.6 Long term input offset voltage drift To evaluate product reliability, two types of stress acceleration are used: • • Voltage acceleration, by changing the applied voltage Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature. The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2. Equation 2 A FV = e β . ( VS – VU ) Where: AFV is the voltage acceleration factor β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1) VS is the stress voltage used for the accelerated test VU is the voltage used for the application The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3. Equation 3 A FT = e Ea 1 1 ------ . – k TU TS Where: AFT is the temperature acceleration factor Ea is the activation energy of the technology based on the failure rate 16/25 DocID027196 Rev 1 TSX7192 Application information -5 -1 k is the Boltzmann constant (8.6173 x 10 eV.K ) TU is the temperature of the die when VU is used (K) TS is the temperature of the die under temperature stress (K) The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature acceleration factor (Equation 4). Equation 4 A F = A FT × A FV AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress duration. Equation 5 Months = A F × 1000 h × 12 months / ( 24 h × 365.25 days ) To evaluate the op amp reliability, a follower stress condition is used where VCC is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules). The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions (see Equation 6). Equation 6 V CC = maxV op with V icm = V CC / 2 The long term drift parameter (ΔVio), estimating the reliability performance of the product, is obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation 7). Equation 7 ∆V io = V io dr ift ( month s ) Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration. 4.7 High values of input differential voltage In a closed loop configuration, which represents the typical use of an op amp, the input differential voltage is low (close to Vio). However, some specific conditions can lead to higher input differential values, such as: • • • operation in an output saturation state operation at speeds higher than the device bandwidth, with output voltage dynamics limited by slew rate. use of the amplifier in a comparator configuration, hence in open loop Use of the TSX7191 in comparator configuration, especially combined with high temperature and long duration can create a permanent drift of Vio. DocID027196 Rev 1 17/25 Application information 4.8 TSX7192 Capacitive load Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that with a gain peaking higher than 2.3 dB an op amp might become unstable. Generally, the unity gain configuration is the worst case for stability and the ability to drive large capacitive loads. Figure 31 shows the serial resistor that must be added to the output, to make a system stable. Figure 32 shows the test configuration using an isolation resistor, Riso. Figure 31: Stability criteria with a serial resistor at different supply voltages Figure 32: Test configuration for Riso 100kΩ Vcc+ 11kΩ Riso Vout Vin Vcc- 18/25 DocID027196 Rev 1 Cl 10kΩ TSX7192 4.9 Application information PCB layout recommendations Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier, load, and power supply. The power and ground traces are critical as they must provide adequate energy and grounding for all circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic inductance. In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is often used. The copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance. 4.10 Optimized application recommendation It is recommended to place a 22 nF capacitor as close as possible to the supply pin. A good decoupling will help to reduce electromagnetic interference impact. DocID027196 Rev 1 19/25 Package information 5 TSX7192 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 20/25 DocID027196 Rev 1 TSX7192 5.1 Package information MiniSO8 package information Figure 33: MiniSO8 package outline Table 6: MiniSO8 package mechanical data Dimensions Millimeters Ref. Min. Typ. A Inches Max. Min. Typ. 1.1 A1 0 A2 0.75 b Max. 0.043 0.15 0 0.95 0.030 0.22 0.40 0.009 0.016 c 0.08 0.23 0.003 0.009 D 2.80 3.00 3.20 0.11 0.118 0.126 E 4.65 4.90 5.15 0.183 0.193 0.203 E1 2.80 3.00 3.10 0.11 0.118 0.122 0.80 0.016 e L 0.85 0.65 0.40 0.60 0.006 0.033 0.026 0.024 L1 0.95 0.037 L2 0.25 0.010 k ccc 0° 0.037 8° 0.10 DocID027196 Rev 1 0° 0.031 8° 0.004 21/25 Package information 5.2 TSX7192 SO8 package information Figure 34: SO8 package outline Table 7: SO8 package mechanical data Dimensions Millimeters Ref. Min. Typ. A Max. Min. Typ. 1.75 0.25 Max. 0.069 A1 0.10 A2 1.25 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.010 D 4.80 4.90 5.00 0.189 0.193 0.197 E 5.80 6.00 6.20 0.228 0.236 0.244 E1 3.80 3.90 4.00 0.150 0.154 0.157 e 0.004 0.010 0.049 1.27 0.050 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 L1 k ccc 22/25 Inches 1.04 1° 0.040 8° 0.10 DocID027196 Rev 1 1° 8° 0.004 TSX7192 6 Ordering information Ordering information Table 8: Order codes Order code TSX7192IDT Temperature range -40 to +125 °C TSX7192IST TSX7192IYDT (1) TSX7192IYST (1) -40 to +125 °C, automotive grade Package Packaging SO8 MiniSO8 SO8 MiniSO8 Marking TSX7192 Tape and reel K210 TSX7192Y K213 Notes: (1) Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent are on-going. DocID027196 Rev 1 23/25 Revision history 7 TSX7192 Revision history Table 9: Document revision history 24/25 Date Revision 06-Mar-2015 1 Changes Initial release DocID027196 Rev 1 TSX7192 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID027196 Rev 1 25/25