TSZ122IQ2T

TSZ121, TSZ122, TSZ124 Datasheet Very high accuracy (5 µV) zero drift micropower 5 V operational amplifiers Features Single (TSZ121) SC70-5 SOT23-5 • Dual (TSZ122) DFN8 2x2 MiniSO8 SO8 Quad (TSZ124) QFN16 3x3 TSSOP14 Maturity status link TSZ121 TSZ122 TSZ124 Related products TSV711 TSV731 TSZ181 TSZ182 Continuous-time precision amplifiers Zero drift 3 MHz amplifiers • • • • • • • Very high accuracy and stability: offset voltage 5 µV max at 25 °C, 8 µV over full temperature range (-40 °C to 125 °C) Rail-to-rail input and output Low supply voltage: 1.8 - 5.5 V Low power consumption: 40 µA max. at 5 V Gain bandwidth product: 400 kHz High tolerance to ESD: 4 kV HBM Extended temperature range: -40 to 125 °C Micro-packages: SC70-5, DFN8 2x2, and QFN16 3x3 Applications • • • • Battery-powered applications Portable devices Signal conditioning Medical instrumentation Description The TSZ12x series of high precision operational amplifiers offer very low input offset voltages with virtually zero drift. TSZ121 is the single version, TSZ122 the dual version, and TSZ124 the quad version, with pinouts compatible with industry standards. The TSZ12x series offers rail-to-rail input and output, excellent speed/power consumption ratio, and 400 kHz gain bandwidth product, while consuming less than 40 µA at 5 V. The devices also feature an ultra-low input bias current. These features make the TSZ12x family ideal for sensor interfaces, battery-powered applications and portable applications. Benefits Higher accuracy without calibration Accuracy virtually unaffected by temperature change DS9216 - Rev 11 - April 2022 For further information contact your local STMicroelectronics sales office. www.st.com TSZ121, TSZ122, TSZ124 Package pin connections 1 Package pin connections Figure 1. Pin connections for each package (top view) 1. DS9216 - Rev 11 SC70-5 SOT23-5 DFN8 2x2 MiniSO8 and SO8 QFN16 3x3 TSSOP14 The exposed pads of the DFN8 2x2 and the QFN16 3x3 can be connected to VCC- or left floating. page 2/37 TSZ121, TSZ122, TSZ124 Absolute maximum ratings and operating conditions 2 Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings (AMR) Symbol Parameter VCC Supply voltage (1) Vid Differential input voltage (2) Value 6 ±VCC Vin Input voltage (3) (VCC-) - 0.2 to (VCC+) + 0.2 Iin Input current (4) 10 Tstg Tj Storage temperature mA °C 150 Thermal resistance junction to ambient (5) (6) SC70-5 205 SOT23-5 250 DFN8 2x2 57 MiniSO8 190 SO8 125 QFN16 3x3 39 TSSOP14 100 HBM: human body model (7) ESD V -65 to 150 Maximum junction temperature Rthja Unit °C/W 4 kV MM: machine model (8) 300 V CDM: charged device model (9) 1.5 kV Latch-up immunity 200 mA 1. All voltage values, except the differential voltage are with respect to the network ground terminal. 2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal. 3. Vcc - Vin must not exceed 6 V, Vin must not exceed 6 V 4. Input current must be limited by a resistor in series with the inputs. 5. Rth are typical values. 6. Short-circuits can cause excessive heating and destructive dissipation. 7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin combinations with other pins floating. 8. Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin combinations with other pins floating. 9. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to ground. Table 2. Operating conditions Symbol DS9216 - Rev 11 Parameter VCC Supply voltage Vicm Common mode input voltage range Toper Operating free air temperature range Value 1.8 to 5.5 (VCC -) - 0.1 to (VCC +) + 0.1 -40 to 125 Unit V °C page 3/37 TSZ121, TSZ122, TSZ124 Electrical characteristics 3 Electrical characteristics Table 3. Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. 1 5 Unit DC performance Vio ΔVio/ΔT Iib Input offset voltage Input offset voltage drift (1) Input bias current (Vout = VCC/2) T = 25 °C -40 °C < T < 125 °C 8 -40 °C < T < 125 °C 10 30 T = 25 °C 50 200 (2) 300 (2) -40 °C < T < 125 °C T = 25 °C 100 Iio Input offset current (Vout = VCC/2) Common mode rejection ratio, 20 log (ΔVicm/ΔVio), Vic = 0 V to VCC, Vout = VCC/2, RL > 1 MΩ T = 25 °C 110 CMR -40 °C < T < 125 °C 110 Avd Large signal voltage gain, Vout = 0.5 V to (VCC - 0.5 V) T = 25 °C 118 -40 °C < T < 125 °C 110 VOH High-level output voltage VOL Low-level output voltage Isink (Vout = VCC) Iout Isource (Vout = 0 V) ICC 400 (2) nV/°C pA 600 (2) -40 °C < T < 125 °C 122 dB 135 T = 25 °C 30 -40 °C < T < 125 °C 70 T = 25 °C 30 -40 °C < T < 125 °C 70 T = 25 °C 7 -40 °C < T < 125 °C 6 T = 25 °C 5 -40 °C < T < 125 °C 4 Supply current (per amplifier, Vout = T = 25 °C VCC/2, RL > 1 MΩ) -40 °C < T < 125 °C μV mV 8 mA 7 28 40 40 μA AC performance GBP Gain bandwidth product 400 Fu Unity gain frequency 300 ɸm Phase margin Gm Gain margin SR (3) Slew rate RL = 10 kΩ, CL = 100 pF kHz 55 Degrees 17 dB 0.17 V/μs To 0.1 %, Vin = 1 Vp-p, RL = 10 kΩ, CL = 100 pF 50 μs f = 1 kHz 60 f = 10 kHz 60 ts Setting time en Equivalent input noise voltage ∫en Low-frequency peak-to-peak input noise Bandwidth, f = 0.1 to 10 Hz 1.1 µVpp Cs Channel separation f = 100 Hz 120 dB tinit Initialization time T = 25 °C 50 -40 °C < T < 125 °C 100 DS9216 - Rev 11 nV/√Hz μs page 4/37 TSZ121, TSZ122, TSZ124 Electrical characteristics 1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature. 2. Guaranteed by design 3. Slew rate value is calculated as the average between positive and negative slew rates. Table 4. Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. 1 5 Unit DC performance Vio ΔVio/ΔT Iib Input offset voltage Input offset voltage drift (1) Input bias current (Vout = VCC/2) T = 25 °C -40 °C < T < 125 °C -40 °C < T < 125 °C 10 T = 25 °C 60 T = 25 °C 120 Input offset current (Vout = VCC/2) Common mode rejection ratio, 20 log (ΔVicm/ΔVio), Vic = 0 V to VCC, Vout = VCC/2, RL > 1 MΩ T = 25 °C 115 CMR -40 °C < T < 125 °C 115 Avd Large signal voltage gain, Vout = 0.5 V to (VCC - 0.5 V) T = 25 °C 118 -40 °C < T < 125 °C 110 VOH High-level output voltage Low-level output voltage Isink (Vout = VCC) Iout Isource (Vout = 0 V) ICC 30 200 400 (2) pA 600 (2) -40 °C < T < 125 °C 128 dB 135 T = 25 °C 30 -40 °C < T < 125 °C 70 T = 25 °C 30 -40 °C < T < 125 °C mV 70 T = 25 °C 15 -40 °C < T < 125 °C 12 T = 25 °C 14 -40 °C < T < 125 °C 10 Supply current (per amplifier, Vout = T = 25 °C VCC/2, RL > 1 MΩ) -40 °C < T < 125 °C nV/°C (2) 300 (2) -40 °C < T < 125 °C Iio VOL μV 8 18 mA 16 29 40 40 μA AC performance GBP Gain bandwidth product 400 Fu Unity gain frequency 300 ɸm Phase margin Gm Gain margin SR (3) Slew rate RL = 10 kΩ, CL = 100 pF kHz 56 Degrees 19 dB 0.19 V/μs To 0.1 %, Vin = 1 Vp-p, RL = 10 kΩ, CL = 100 pF 50 μs f = 1 kHz 40 f = 10 kHz 40 ts Setting time en Equivalent input noise voltage ∫en Low-frequency peak-to-peak input noise Bandwidth, f = 0.1 to 10 Hz 0.8 µVpp Cs Channel separation f = 100 Hz 120 dB DS9216 - Rev 11 nV/√Hz page 5/37 TSZ121, TSZ122, TSZ124 Electrical characteristics Symbol tinit Parameter Initialization time Conditions Min. Typ. T = 25 °C 50 -40 °C < T < 125 °C 100 Max. Unit μs 1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature. 2. Guaranteed by design 3. Slew rate value is calculated as the average between positive and negative slew rates. Table 5. Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. 1 5 Unit DC performance Vio ΔVio/ΔT Iib Input offset voltage Input offset voltage drift (1) Input bias current (Vout = VCC/2) T = 25 °C -40 °C < T < 125 °C -40 °C < T < 125 °C 10 T = 25 °C 70 T = 25 °C 140 Input offset current (Vout = VCC/2) Common mode rejection ratio, 20 log (ΔVicm/ΔVio), Vic = 0 V to VCC, Vout = VCC/2, RL > 1 MΩ T = 25 °C 115 CMR -40 °C < T < 125 °C 115 Supply voltage rejection ratio, 20 log (ΔVCC/ΔVio), VCC = 1.8 V to 5.5 V, Vout = VCC/2, RL > 1 MΩ T = 25 °C 120 SVR -40 °C < T < 125 °C 120 Avd Large signal voltage gain, Vout = 0.5 V to (VCC - 0.5 V) T = 25 °C 120 -40 °C < T < 125 °C 110 VOH VOL EMI rejection rate = -20 log (VRFpeak/ΔVio) High-level output voltage Low-level output voltage Isink (Vout = VCC) Iout Isource (Vout = 0 V) ICC 30 200 400 (2) pA 600 (2) -40 °C < T < 125 °C 136 140 135 VRF = 100 mVp, f = 400 MHz 84 VRF = 100 mVp, f = 900 MHz 87 VRF = 100 mVp, f = 1800 MHz 90 VRF = 100 mVp, f = 2400 MHz 91 dB T = 25 °C 30 -40 °C < T < 125 °C 70 T = 25 °C 30 -40 °C < T < 125 °C 70 T = 25 °C 15 -40 °C < T < 125 °C 14 T = 25 °C 14 -40 °C < T < 125 °C 12 Supply current (per amplifier, Vout = T = 25 °C VCC/2, RL > 1 MΩ) -40 °C < T < 125 °C nV/°C (2) 300 (2) -40 °C < T < 125 °C Iio EMIRR (3) μV 8 mV 18 mA 17 31 40 40 μA AC performance GBP Fu Gain bandwidth product Unity gain frequency DS9216 - Rev 11 400 RL = 10 kΩ, CL = 100 pF 300 kHz page 6/37 TSZ121, TSZ122, TSZ124 Electrical characteristics Symbol ɸm Parameter Conditions Phase margin Gm Gain margin SR (4) Slew rate Min. Typ. Max. Unit 53 Degrees 19 dB 0.19 V/μs To 0.1 %, Vin = 100 mVp-p, RL = 10 kΩ, CL = 100 pF 10 μs f = 1 kHz 37 f = 10 kHz 37 RL = 10 kΩ, CL = 100 pF ts Setting time en Equivalent input noise voltage ∫en Low-frequency peak-to-peak input noise Bandwidth, f = 0.1 to 10 Hz 0.75 µVpp Cs Channel separation f = 100 Hz 120 dB tinit Initialization time T = 25 °C 50 -40 °C < T < 125 °C 100 nV/√Hz μs 1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature. 2. Guaranteed by design 3. Tested on SC70-5 package 4. Slew rate value is calculated as the average between positive and negative slew rates. DS9216 - Rev 11 page 7/37 TSZ121, TSZ122, TSZ124 Electrical characteristic curves 4 Electrical characteristic curves Figure 3. Input offset voltage distribution at VCC = 5 V Figure 2. Supply current vs. supply voltage 40 60 T=-40°C 30 40 25 T=125°C 20 15 20 10 VICM=VCC/2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Supply voltage (V) Figure 4. Input offset voltage distribution at VCC = 3.3 V 0 -5 -4 -3 -2 -1 0 1 2 3 4 5 Input offset voltage (µV) Figure 5. Input offset voltage distribution at VCC = 1.8 V 60 60 T=25°C Vcc=3.3V, Vicm=1.65V 50 T=25°C Vcc=1.8V, Vicm=0.6V 50 40 Population 40 Population 30 10 5 30 20 10 30 20 10 0 -5 -4 -3 -2 -1 0 1 2 3 4 0 5 -5 Input offset voltage (µV) Figure 6. Vio temperature co-efficient distribution (-40 °C to 25 °C) 50 -4 -3 -2 -1 0 1 2 3 4 5 Input offset voltage (µV) Figure 7. Vio temperature co-efficient distribution (25 °C to 125 °C) 60 60 T=-40°C to 25°C Vcc=5V, Vicm=2.5V 50 T=25°C to 125°C Vcc=5V, Vicm=2.5V 40 Population 40 Population T=25°C Vcc=5V, Vicm=2.5V 50 T=25°C Population Supply Current (µA) 35 30 20 30 20 10 10 0 0 -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 0.025 0.030 -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 0.025 0.030 Input offset voltage drift [µV/°C] DS9216 - Rev 11 Input offset voltage drift [µV/°C] page 8/37 TSZ121, TSZ122, TSZ124 Electrical characteristic curves Figure 8. Input offset voltage vs. supply voltage Figure 9. Input offset voltage vs. input common-mode at VCC = 1.8 V 5 5 4 4 3 1 0 -1 T=25°C T=-40°C -2 1 T=-40°C 0 -1 T=25°C -2 -3 -3 Vicm=Vcc/2 -4 -5 2.0 2.3 2.5 2.8 3.0 3.3 3.5 3.8 4.0 4.3 4.5 4.8 -4 0.0 0.2 0.4 0.6 Vio (µV) T=25°C T=-40°C Vcc=2.7V 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 5 4 3 3 2 1 0 -1 -2 -3 -3 -4 -5 1.4 1.6 1.8 T=25°C T=-40°C Vcc=5.5V 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 Vicm (V) Figure 13. VOH vs. supply voltage Figure 12. Input offset voltage vs. temperature 20 8 Output swing (mV from Vcc+) 10 Limit for TSZ121 6 Input offset voltage (µV) 1.2 T=125°C Vicm (V) 4 2 0 -2 -4 -6 -8 Vcc=5V, Vicm=2.5V -20 0 20 40 60 Temperature (°C) DS9216 - Rev 11 1.0 Figure 11. Input offset voltage vs. input common-mode at VCC = 5.5 V T=125°C -10 -40 0.8 Vicm (V) Figure 10. Input offset voltage vs. input common-mode at VCC = 2.7 V 5 4 3 3 2 1 0 -1 -2 -3 -3 -4 -5 Vcc=1.8V -5 5.0 Vcc(V) Vio (µV) T=125°C 2 Vio (µV) Vio (µV) 3 T=125°C 2 80 100 120 18 15 13 10 8 T=25°C T=125°C T=-40°C 5 3 Rl=10kΩ Vicm=Vcc/2 0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 Vcc (V) page 9/37 TSZ121, TSZ122, TSZ124 Electrical characteristic curves Figure 14. VOL vs. supply voltage Figure 15. Output current vs. output voltage at VCC = 1.8 V 30 18 20 15 13 T=125°C 10 T=25°C 8 T=-40°C 5 Output Current (mA) Output swing (mV from Vcc-) 20 T=-40°C 10 T=125°C 0 T=25°C -10 3 Rl=10kΩ Vicm=Vcc/2 -30 0.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 T=-40°C Vcc=1.8V 0.3 0.5 Vcc (V) Figure 16. Output current vs. output voltage at VCC = 5.5 V 0.8 1.0 1.3 Output Voltage (V) 1.5 1.8 Figure 17. Input bias current vs. common mode at VCC = 5 V 30 100 T=-40°C 20 T=25°C 75 50 T=125°C 10 IiBp 25 IiB (pA) Output Current (mA) T=125°C -20 0 0 -10 T=25°C T=125°C Figure 18. Input bias current vs. common mode at VCC = 1.8 V Vcc=5V T=25°C Figure 19. Input bias current vs. temperature at VCC = 5 V 100 75 75 50 50 IiB (pA) IiBp -25 IiBn Vcc=1.8V T=25°C -75 0.3 0 -25 -50 -50 0.0 IiBp 25 0 DS9216 - Rev 11 IiBn -100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Common Mode Voltage (V) 100 -100 -25 -75 T=-40°C Vcc=5.5V -30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) 25 0 -50 -20 IiB (pA) T=25°C 0.5 0.8 1.0 1.3 1.5 Common Mode Voltage (V) 1.8 IiBn -75 -100 Vcc=5V -25 0 25 50 75 Temperature (°C) 100 125 page 10/37 TSZ121, TSZ122, TSZ124 Electrical characteristic curves Figure 20. Bode diagram at VCC = 1.8 V Figure 21. Bode diagram at VCC = 2.7 V 250 250 T=125°C 50 0 0 -50 Phase 1 10 0 -50 Phase -150 Vcc=1.8V, Vicm=0.9V, G=-100 Rl=10kΩ, Cl=100pF, Vrl=Vcc/2 -40 -250 1000 100 -100 1 10 Frequency (kHz) 0 100 50 0 -50 Phase 1 10 Phase 60 Gain 40 20 0 -20 0.01 0.1 Figure 24. Positive slew rate vs. supply voltage -20 1000 100 0.0 0.2 T=-40°C T=25°C T=125°C 0.1 Rl=10kΩ, Cl=100pF Vin: from 0.3V to Vcc-0.3V SR calculated from 10% to 90% 2.0 2.5 3.0 3.5 4.0 4.5 Supply Voltage (V) 5.0 5.5 Negative Slew Rate (V/µs) Positive Slew Rate (V/µs) 10 Figure 25. Negative slew rate vs. supply voltage 0.3 DS9216 - Rev 11 1 Frequency (kHz) Frequency (kHz) 0.0 0 Vcc=5V, Vicm=2.5V, Rl=10k Ω, Cl=100pF -200 -250 1000 40 20 -150 100 80 60 -100 Vcc=5.5V, Vicm=2.75V, G=-100 Rl=10kΩ, Cl=100pF, Vrl=Vcc/2 -40 100 80 150 Gain (dB) Gain (dB) T=25°C 100 200 Phase (°) Gain T=-40°C -20 -250 1000 100 Figure 23. Open loop gain vs. frequency 250 40 T=125°C -200 Frequency (kHz) Figure 22. Bode diagram at VCC = 5.5 V 20 -150 Vcc=2.7V, Vicm=1.35V, G=-100 Rl=10kΩ, Cl=100pF, Vrl=Vcc/2 -40 -200 50 0 -20 -100 100 T=25°C T=125°C Phase (°) -20 150 Phase (°) T=25°C 20 100 200 Gain T=-40°C 150 Gain (dB) T=-40°C 20 Gain (dB) 200 Gain Phase (°) 40 40 T=125°C -0.1 T=-40°C T=25°C -0.2 Rl=10kΩ, Cl=100pF Vin: from Vcc-0.3V to 0.3V SR calculated from 10% to 90% -0.3 2.0 2.5 3.0 3.5 4.0 4.5 Supply Voltage (V) 5.0 5.5 page 11/37 TSZ121, TSZ122, TSZ124 Electrical characteristic curves Figure 26. 0.1 Hz to 10 Hz noise Figure 27. Noise vs. frequency Equivalent Input Voltage Noise (nV/√Hz) 55 50 noise density (nV/√Hz) 45 40 35 30 25 20 15 Vcc = 5.5V Vicm=Vcc/2 T=25°C 10 100m Noise 0.1Hz_10Hz equivalent to 0.75 µVpp 1 Frequency (Hz) 180 160 120 100 80 20 Vcc=5.5V 100 1k Frequency (Hz) 35 160 30 Overshoot (%) Vicm=Vcc/2 Vcc=5.5V 100 60 125°C 25°C 25 20 15 10 40 20 10k Figure 29. Output overshoot vs. load capacitance 180 80 Vcc=1.8V 40 40 120 Vcc=3.3V 60 200 140 Vicm=Vcc/2 Tamb=25°C 140 10 Figure 28. Noise vs. frequency and temperature Equivalent Input Voltage Noise (nV/√Hz) 200 Vcc=5.5V 100mVpp Rl=10kΩ 5 -40°C 100 1k Frequency (Hz) 0 10 10k Figure 30. Small signal 100 Load capacitance (pF) 1000 Figure 31. Large signal 0.10 Output Voltage (V) Output Voltage (V) 2.00 0.05 0.00 Vcc = 5.5V Rl=10kΩ Cl=100pF T=25°C -0.05 -0.10 -10 DS9216 - Rev 11 0 10 20 Time (µs) 0.00 Vcc = 5.5V Rl=10kΩ Cl=100pF T=25°C -2.00 30 -100 0 100 200 300 Time (µs) 400 500 600 page 12/37 TSZ121, TSZ122, TSZ124 Electrical characteristic curves Figure 32. Positive overvoltage recovery at VCC = 1.8 V Figure 33. Positive overvoltage recovery at VCC = 5 V 1.0 1.0 0.00 0.00 0.5 0.0 -0.10 -1.0 Vcc=1.8V, Vicm=0.9V, G=101 Rl=10kΩ, Cl=100pF -2.0 0 50µ -0.10 -1.5 -0.15 Vcc=5.5V, Vicm=2.75V, G=101 Rl=10kΩ, Cl=100pF -2.5 -0.20 -100µ -50µ Vout -1.0 -2.0 -0.15 -1.5 -0.05 -0.5 Vin (V) -0.5 Vin (V) Vout Vout (V) -0.05 0.0 Vout (V) Vin Vin 0.5 -3.0 100µ 150µ 200µ 250µ 300µ 350µ 400µ -0.20 -100µ -50µ 0 50µ 100µ 150µ 200µ 250µ 300µ 350µ 400µ Time (s) Time (s) Figure 34. Negative overvoltage recovery at VCC = 1.8 V Figure 35. Negative overvoltage recovery at VCC = 5 V 0.5 Vout 3.0 0.20 0.15 2.5 0.15 0.10 2.0 0.0 0.00 -0.05 -0.5 Vcc=1.8V, Vicm=0.9V, G=101 Rl=10kΩ, Cl=100pF -1.0 -100µ -50µ 0 50µ Vout (V) 0.05 Vin (V) Vout (V) Vin 0.20 1.0 0.00 0.5 -0.05 0.0 -0.10 -0.15 -0.5 -0.20 -1.0 100µ 150µ 200µ 250µ 300µ 350µ 400µ Vcc=5.5V, Vicm=2.75V, G=101 Rl=10kΩ , Cl=100pF -0.15 -0.20 -100µ -50µ 0 50µ 100µ 150µ 200µ 250µ 300µ 350µ 400µ Time (s) Time (s) Figure 36. PSRR vs. frequency Figure 37. Output impedance vs. frequency 2000 1800 +PSRR Output Impedance (Ω) -80 PSRR (dB) 0.05 -0.10 -100 -60 -PSRR -40 -20 Vcc=5.5V, Vicm=2.75V, G=1 Rl=10kΩ, Cl=100pF, Vripple=100mVpp 0 10 100 1000 10000 Frequency (Hz) DS9216 - Rev 11 1.5 0.10 Vout Vin Vin (V) 1.0 100000 1600 1400 Vcc=2.7V to 5.5V Osc level=30mVRMS G=1 Ta=25°C 1200 1000 800 600 400 200 1000000 100 1k 10k 100k Frequency (Hz) 1M page 13/37 TSZ121, TSZ122, TSZ124 Application information 5 Application information 5.1 Operation theory The TSZ121, TSZ122, and TSZ124 are high precision CMOS devices. They achieve a low offset drift and no 1/f noise thanks to their chopper architecture. Chopper-stabilized amps constantly correct low-frequency errors across the inputs of the amplifier. Chopper-stabilized amplifiers can be explained with respect to: • • 5.1.1 Time domain Frequency domain Time domain The basis of the chopper amplifier is realized in two steps. These steps are synchronized thanks to a clock running at 400 kHz. Figure 38. Block diagram in the time domain (step 1) Chop 1 Chop 2 Vinp Vinn A2(f) A1(f) Filter Vo ut Figure 39. Block diagram in the time domain (step 2) Chop 1 Chop 2 Vinp Vinn A1(f) A2 (f) Filter Vo ut Figure 38. Block diagram in the time domain (step 1) shows step 1, the first clock cycle, where Vio is amplified in the normal way. Figure 39. Block diagram in the time domain (step 2) shows step 2, the second clock cycle, where Chop1 and Chop2 swap paths. At this time, the Vio is amplified in a reverse way as compared to step 1. At the end of these two steps, the average Vio is close to zero. The A2(f) amplifier has a small impact on the Vio because the Vio is expressed as the input offset and is consequently divided by A1(f). In the time domain, the offset part of the output signal before filtering is shown in Figure 40. Vio cancellation principle. Figure 40. Vio cancellation principle Step 1 Step 1 S tep 1 Vio Time Vio Step 2 DS9216 - Rev 11 Step 2 S tep 2 page 14/37 TSZ121, TSZ122, TSZ124 Operating voltages The low pass filter averages the output value resulting in the cancellation of the Vio offset. The 1/f noise can be considered as an offset in low frequency and it is canceled like the Vio, thanks to the chopper technique. 5.1.2 Frequency domain The frequency domain gives a more accurate vision of chopper-stabilized amplifier architecture. Figure 41. Block diagram in the frequency domain Vinn Chop1 A(f) Vi np Chop2 A(f) Filter Vout Vos + Vn 1 2 3 4 The modulation technique transposes the signal to a higher frequency where there is no 1/f noise, and demodulate it back after amplification. 1. According to Figure 41. Block diagram in the frequency domain, the input signal Vin is modulated once (Chop1) so all the input signal is transposed to the high frequency domain. 2. The amplifier adds its own error (Vio (output offset voltage) + the noise Vn (1/f noise)) to this modulated signal. 3. This signal is then demodulated (Chop2), but since the noise and the offset are modulated only once, they are transposed to the high frequency, leaving the output signal of the amplifier without any offset and low frequency noise. Consequently, the input signal is amplified with a very low offset and 1/f noise. 4. To get rid of the high frequency part of the output signal (which is useless) a low pass filter is implemented. To further suppress the remaining ripple down to a desired level, another low pass filter may be added externally on the output of the TSZ121, TSZ122, or TSZ124 device. 5.2 Operating voltages TSZ121, TSZ122, and TSZ124 devices can operate from 1.8 to 5.5 V. The parameters are fully specified for 1.8 V, 3.3 V, and 5 V power supplies. However, the parameters are very stable in the full VCC range and several characterization curves show the TSZ121, TSZ122, and TSZ124 device characteristics at 1.8 V and 5.5 V. Additionally, the main specifications are guaranteed in extended temperature ranges from -40 to 125 ° C. 5.3 Input pin voltage ranges TSZ121, TSZ122, and TSZ124 devices have internal ESD diode protection on the inputs. These diodes are connected between the input and each supply rail to protect the input MOSFETs from electrical discharge. If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become conductive and excessive current can flow through them. Without limitation this over current can damage the device. In this case, it is important to limit the current to 10 mA, by adding resistance on the input pin, as described in Figure 42. Input current limitation. DS9216 - Rev 11 page 15/37 TSZ121, TSZ122, TSZ124 Rail-to-rail input Figure 42. Input current limitation TSZ121, TSZ122, TSZ124 5V R Vin 5.4 - + + - Vout Rail-to-rail input TSZ121, TSZ122, and TSZ124 devices have a rail-to-rail input, and the input common mode range is extended from (VCC -) - 0.1 V to (VCC+) + 0.1 V. 5.5 Input offset voltage drift over temperature The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations. The maximum input voltage drift over temperature is computed using Equation 1. Equation 1 ∆V io V ( T ) – V io ( 25 °C) = ma x io ∆T T – 25 °C Where T = -40 °C and 125 °C. The TSZ121, TSZ122, and TSZ124 datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a Cpk (process capability index) greater than 1.3. 5.6 Rail-to-rail output The operational amplifier output levels can go close to the rails: to a maximum of 30 mV above and below the rail when connected to a 10 kΩ resistive load to VCC/2. 5.7 Capacitive load Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that with a gain peaking higher than 2.3 dB an op amp might become unstable. Generally, the unity gain configuration is the worst case for stability and the ability to drive large capacitive loads. Figure 43. Stability criteria with a serial resistor at VDD = 5 V and Figure 44. Stability criteria with a serial resistor at VDD = 1.8 V show the serial resistor that must be added to the output, to make a system stable. Figure 45. Test configuration for Riso shows the test configuration using an isolation resistor, Riso. DS9216 - Rev 11 page 16/37 TSZ121, TSZ122, TSZ124 PCB layout recommendations Figure 44. Stability criteria with a serial resistor at VDD = 1.8 V Figure 43. Stability criteria with a serial resistor at VDD = 5 V Figure 45. Test configuration for Riso +VCC Riso VIN + -VCC 5.8 Cload VOUT 10 kΩ PCB layout recommendations Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier, load, and power supply. The power and ground traces are critical as they must provide adequate energy and grounding for all circuits. Good practice is to use short and wide PCB traces to minimize voltage drops and parasitic inductance. In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is often used. The copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance. 5.9 Optimized application recommendation TSZ121, TSZ122, and TSZ124 devices are based on chopper architecture. As they are switched devices, it is strongly recommended to place a 0.1 µF capacitor as close as possible to the supply pins. A good decoupling has several advantages for an application. First, it helps to reduce electromagnetic interference. Due to the modulation of the chopper, the decoupling capacitance also helps to reject the small ripple that may appear on the output. TSZ121, TSZ122, and TSZ124 devices have been optimized for use with 10 kΩ in the feedback loop. With this, or a higher value of resistance, these devices offer the best performance. 5.10 EMI rejection ration (EMIRR) The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF signal rectification. The TSZ121, TSZ122, and TSZ124 have been specially designed to minimize susceptibility to EMIRR and show an extremely good sensitivity. Figure 46. EMIRR on IN+ pin shows the EMIRR IN+ of the TSZ121, TSZ122, and TSZ124 measured from 10 MHz up to 2.4 GHz. DS9216 - Rev 11 page 17/37 TSZ121, TSZ122, TSZ124 Application examples Figure 46. EMIRR on IN+ pin 120 EMIRR In+(dB) 100 80 60 40 20 0 10 Vcc=5.5V, G=1 Prf=-10dBm 100 1000 Frequency (MHz) 5.11 5.11.1 Application examples Oxygen sensor The electrochemical sensor creates a current proportional to the concentration of the gas being measured. This current is converted into voltage thanks to R resistance. This voltage is then amplified by TSZ121, TSZ122, and TSZ124 devices (see Figure 47. Oxygen sensor principle schematic). Figure 47. Oxygen sensor principle schematic R1 R2 VCC I - O2_ sensor + + Vout - TSZ121, TSZ122, TSZ124 The output voltage is calculated using Equation 2: Equation 2 V ou t = ( I × R – V io ) × R2 +1 R1 As the current delivered by the O2 sensor is extremely low, the impact of the Vio can become significant with a traditional operational amplifier. The use of the chopper amplifier of the TSZ121, TSZ122, or TSZ124 is perfect for this application. In addition, using TSZ121, TSZ122, or TSZ124 devices for the O2 sensor application ensures that the measurement of O2 concentration is stable even at different temperature thanks to a very good ΔVio/ΔT. 5.11.2 Precision instrumentation amplifier The instrumentation amplifier uses three op amps. The circuit, shown in Figure 48. Precision instrumentation amplifier schematic, exhibits high input impedance, so that the source impedance of the connected sensor has no impact on the amplification. DS9216 - Rev 11 page 18/37 TSZ121, TSZ122, TSZ124 Application examples Figure 48. Precision instrumentation amplifier schematic TSZ12x V1 R2 + - R4 Rf + Rg TSZ12x Vout Rf R1 + V2 R3 TSZ12x The gain is set by tuning the Rg resistor. With R1 = R2 and R3 = R4, the output is given by Section 5.11.2 Equation 3. Equation 3 Vout = V2 − V1 R4 2Rf R2 ⋅ Rg + 1 The matching of R1, R2 and R3, R4 is important to ensure a good common mode rejection ratio (CMR). 5.11.3 Low-side current sensing Power management mechanisms are found in most electronic systems. Current sensing is useful for protecting applications. The low-side current sensing method consists of placing a sense resistor between the load and the circuit ground. The resulting voltage drop is amplified using TSZ121, TSZ122, and TSZ124 devices (see Figure 49. Low-side current sensing schematic). Figure 49. Low-side current sensing schematic C1 Rg1 I Rf1 In Rshunt Rg2 Ip 5V - + + - Vout TSZ121, TSZ122, TSZ124 Rf2 Vout can be expressed as follows: Equation 4 V ou t = R shun t × I 1 – R g2 R g2 + R f2 1+ R g2 × R f2 R f1 R f1 R f1 + Ip – l n × R f1 – V io 1 + × 1+ R g2 + R f2 R g1 R g1 R g1 Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, Equation 4 can be simplified as follows: Equation 5 V out = R shunt × I Rf Rf – V io 1 + + R f × I io Rg Rg The main advantage of using the chopper of the TSZ121, TSZ122, and TSZ124, for a low-side current sensing, is that the errors due to Vio and Iio are extremely low and may be neglected. DS9216 - Rev 11 page 19/37 TSZ121, TSZ122, TSZ124 Application examples Therefore, for the same accuracy, the shunt resistor can be chosen with a lower value, resulting in lower power dissipation, lower drop in the ground path, and lower cost. Particular attention must be paid on the matching and precision of Rg1, Rg2, Rf1, and Rf2, to maximize the accuracy of the measurement. DS9216 - Rev 11 page 20/37 TSZ121, TSZ122, TSZ124 Package information 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS9216 - Rev 11 page 21/37 TSZ121, TSZ122, TSZ124 SC70-5 (or SOT323-5) package information 6.1 SC70-5 (or SOT323-5) package information Figure 50. SC70-5 (or SOT323-5) package outline SIDE VIEW DIMENSIONS IN MM GAUGE PLANE COPLANAR LEADS SEATING PLANE TOP VIEW Table 6. SC70-5 (or SOT323-5) mechanical data Dimensions Millimeters Ref. Min. A Typ. 0.80 A1 DS9216 - Rev 11 Inches Max. Min. 1.10 0.032 Typ. 0.043 0.10 A2 0.80 b 0.90 Max. 0.004 1.00 0.032 0.035 0.15 0.30 0.006 0.012 c 0.10 0.22 0.004 0.009 D 1.80 2.00 2.20 0.071 0.079 0.087 E 1.80 2.10 2.40 0.071 0.083 0.094 E1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65 0.025 e1 1.30 0.051 L 0.26 < 0° 0.36 0.46 0.010 8° 0° 0.014 0.039 0.018 8° page 22/37 TSZ121, TSZ122, TSZ124 SOT23-5 package information 6.2 SOT23-5 package information Figure 51. SOT23-5 package outline Table 7. SOT23-5 mechanical data Dimensions Millimeters Ref. A Min. Typ. Max. Min. Typ. Max. 0.90 1.20 1.45 0.035 0.047 0.057 A1 DS9216 - Rev 11 Inches 0.15 0.006 A2 0.90 1.05 1.30 0.035 0.041 0.051 B 0.35 0.40 0.50 0.014 0.016 0.020 C 0.09 0.15 0.20 0.004 0.006 0.008 D 2.80 2.90 3.00 0.110 0.114 0.118 D1 1.90 0.075 e 0.95 0.037 E 2.60 2.80 3.00 0.102 0.110 0.118 F 1.50 1.60 1.75 0.059 0.063 0.069 L 0.10 0.35 0.60 0.004 0.014 0.024 K 0 degrees 10 degrees 0 degrees 10 degrees page 23/37 TSZ121, TSZ122, TSZ124 DFN8 2 x 2 package information 6.3 DFN8 2 x 2 package information Figure 52. DFN8 2 x 2 package outline Table 8. DFN8 2 x 2 mechanical data Dimensions Millimeters Ref. A Min. Typ. Max. Min. Typ. Max. 0.51 0.55 0.60 0.020 0.022 0.024 A1 0.05 A3 0.002 0.15 0.006 b 0.18 0.25 0.30 0.007 0.010 0.012 D 1.85 2.00 2.15 0.073 0.079 0.085 D2 1.45 1.60 1.70 0.057 0.063 0.067 E 1.85 2.00 2.15 0.073 0.079 0.085 E2 0.75 0.90 1.00 0.030 0.035 0.039 e L ddd DS9216 - Rev 11 Inches 0.50 0.225 0.325 0.020 0.425 0.08 0.009 0.013 0.017 0.003 page 24/37 TSZ121, TSZ122, TSZ124 DFN8 2 x 2 package information Figure 53. DFN8 2 x 2 recommended footprint DS9216 - Rev 11 page 25/37 TSZ121, TSZ122, TSZ124 MiniSO8 package information 6.4 MiniSO8 package information Figure 54. MiniSO8 package outline Table 9. MiniSO8 package mechanical data Dimensions Millimeters Ref. Min. Typ. A Max. Min. Typ. 1.1 A1 0 A2 0.75 b Max. 0.043 0.15 0 0.95 0.030 0.22 0.40 0.009 0.016 c 0.08 0.23 0.003 0.009 D 2.80 3.00 3.20 0.11 0.118 0.126 E 4.65 4.90 5.15 0.183 0.193 0.203 E1 2.80 3.00 3.10 0.11 0.118 0.122 e L 0.85 0.65 0.40 0.60 0.0006 0.033 0.80 0.016 0.024 0.95 0.037 L2 0.25 0.010 ccc 0° 0.037 0.026 L1 k DS9216 - Rev 11 Inches 8° 0.10 0° 0.031 8° 0.004 page 26/37 TSZ121, TSZ122, TSZ124 SO8 package information 6.5 SO8 package information Figure 55. SO8 package outline Table 10. SO8 package mechanical data Dimensions Millimeters Ref. Min. Typ. A Max. Min. Typ. 1.75 0.25 Max. 0.069 A1 0.10 A2 1.25 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.010 D 4.80 4.90 5.00 0.189 0.193 0.197 E 5.80 6.00 6.20 0.228 0.236 0.244 E1 3.80 3.90 4.00 0.150 0.154 0.157 e 0.004 0.010 0.049 1.27 0.050 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 L1 k ccc DS9216 - Rev 11 Inches 1.04 0° 0.040 8° 0.10 0° 8° 0.004 page 27/37 TSZ121, TSZ122, TSZ124 QFN16 3x3 package information 6.6 QFN16 3x3 package information Figure 56. QFN16 3x3 package outline DS9216 - Rev 11 page 28/37 TSZ121, TSZ122, TSZ124 QFN16 3x3 package information Table 11. QFN16 3x3 mechanical data Dimensions Millimeters Ref. Inches Min. Typ. Max. Min. Typ. Max. A 0.80 0.90 1.00 0.031 0.035 0.039 A1 0 0.05 0 A3 0.20 b 0.18 D 2.90 D2 1.50 E 2.90 E2 1.50 e L 3.00 3.00 0.008 0.30 0.007 3.10 0.114 1.80 0.059 3.10 0.114 1.80 0.059 0.50 0.30 0.002 0.012 0.118 0.122 0.071 0.118 0.122 0.071 0.020 0.50 0.012 0.020 Figure 57. QFN16 3x3 recommended footprint DS9216 - Rev 11 page 29/37 TSZ121, TSZ122, TSZ124 TSSOP14 package information 6.7 TSSOP14 package information Figure 58. TSSOP14 package outline aaa Table 12. TSSOP14 package mechanical data Dimensions Millimeters Ref. Min. Typ. A Max. Min. Typ. 1.20 A1 0.05 A2 0.80 b Max. 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.90 5.00 5.10 0.193 0.197 0.201 E 6.20 6.40 6.60 0.244 0.252 0.260 E1 4.30 4.40 4.50 0.169 0.173 0.176 e L k aaa 1.00 0.65 0.45 L1 DS9216 - Rev 11 Inches 0.60 0.0256 0.75 0.018 1.00 0° 0.024 0.030 0.039 8° 0.10 0° 8° 0.004 page 30/37 TSZ121, TSZ122, TSZ124 Ordering information 7 Ordering information Table 13. Order codes Order code Temperature range Package Packaging Marking TSZ121ICT SC70-5 K44 TSZ121ILT SΟΤ23-5 K143 TSZ122IQ2T DFN8 2x2 K33 MiniSO8 K208 TSZ122IDT SO8 TSZ122I TSZ124IQ4T QFN16 3x3 -40 to 125 °C TSZ122IST TSZ124IPT TSSOP14 K193 Tape and reel TSZ124I TSZ121IYCT (1) SC70-5 K4J TSZ121IYLT (1) SΟΤ23-5 K192 SO8 K192D TSZ122IYST (1) MiniSO8 K192 TSZ124IYPT (1) TSSOP14 TSZ124IY TSZ122IYDT (1) -40 to 125 °C automotive grade 1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q002 or equivalent. For qualification status detail, check "Maturity status link" on first page ("Quality & Reliability" tab on www.st.com). DS9216 - Rev 11 page 31/37 TSZ121, TSZ122, TSZ124 Revision history Table 14. Document revision history Date Revision 16-Aug-2012 1 Changes Initial release. Added dual and quad products (TSZ122 and TSZ124 respectively) Updated title Added following packages: DFN8 2x2, MiniSO8, QFN16 3x3, TSSOP14 Updated Features Added Benefits and Related products Updated Description Updated Table 1 (Rthja, ESD) 25-Apr-2013 2 Updated Table 3 (Vio, ∆Vio/∆T, CMR, Avd, ICC, en, and Cs) Updated Table 4 (Vio, ∆Vio/∆T, CMR, ICC, en, and Cs) Updated Table 5 (Vio, ∆Vio/∆T, CMR, SVR, EMIRR, ICC, ts, en, and Cs) Updated curves of Section 3: Electrical characteristics Added Section 4.7: Capacitive load Small update Section 4.9: Optimized application recommendation (capacitor) Added Section 4.10: EMI rejection ration (EMIRR) Updated Table 10: Order codes Added SO8 package for commercial part number TSZ122IDT Related products: added hyperlinks for TSV71x and TSV73x products Table 1: updated CDM information 11-Sep-2013 3 Figure 6, Figure 7: updated X-axes titles Figure 12: updated X-axis and Y-axis titles Figure 19: updated title Figure 26: updated X-axis (logarithmic scale) Figure 27 and Figure 28: updated Y-axis titles Table 1: updated ESD information 23-May-2014 4 Table 5: added footnote 3 Table 10: Order codes: added automotive qualification footnotes 1 and 2; updated marking of TSZ122IST. Updated disclaimer Updated document layout 09-May-2016 5 07-Feb-2017 6 Table 3, Table 4, and Table 5: added parameter "Low-frequency peak-to-peak input noise" (∫en). Figure 26: "0.1 Hz to 10 Hz noise": updated legend (0.75 μVpp instead of 0.2 μVpp) 12-Apr-2017 7 Updated footnote related to TSZ122IYDT in Table 13: "Order codes". Minor changes throughout the document. 18-May-2017 8 Updated package outline drawing and mechanical data in Section 6.2: SOT23-5 package information. 12-Nov-2018 9 Updated Figure 43. Stability criteria with a serial resistor at VDD = 5 V and Figure 44. Stability criteria with a serial resistor at VDD = 1.8 V 26-Feb-2019 10 Updated Figure 43. Stability criteria with a serial resistor at VDD = 5 V and Figure 44. Stability criteria with a serial resistor at VDD = 1.8 V 07-Apr-2022 11 Added new TSZ121IYCT order code and updated footnote in Table 13. Order codes. DS9216 - Rev 11 Table 13: "Order codes": added new automotive grade order code TSZ122IYD, updated footnotes of other automotive grade order codes. page 32/37 TSZ121, TSZ122, TSZ124 Contents Contents 1 Package pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.1 6 7 Operation theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 Time domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.2 Frequency domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 Input pin voltage ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 Rail-to-rail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5 Input offset voltage drift over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.7 Capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.8 PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.9 Optimized application recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.10 EMI rejection ration (EMIRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.11 Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.11.1 Oxygen sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.11.2 Precision instrumentation amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.11.3 Low-side current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6.1 SC70-5 (or SOT323-5) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 SOT23-5 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3 DFN8 2 x 2 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4 MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.5 SO8 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6 QFN16 3x3 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.7 TSSOP14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 DS9216 - Rev 11 page 33/37 TSZ121, TSZ122, TSZ124 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Absolute maximum ratings (AMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SC70-5 (or SOT323-5) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOT23-5 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFN8 2 x 2 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MiniSO8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QFN16 3x3 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSSOP14 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS9216 - Rev 11 . 3 . 3 . 4 . 5 . 6 22 23 24 26 27 29 30 31 32 page 34/37 TSZ121, TSZ122, TSZ124 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. DS9216 - Rev 11 Pin connections for each package (top view) . . . . . . . . . . Supply current vs. supply voltage . . . . . . . . . . . . . . . . . . Input offset voltage distribution at VCC = 5 V . . . . . . . . . . . Input offset voltage distribution at VCC = 3.3 V . . . . . . . . . Input offset voltage distribution at VCC = 1.8 V . . . . . . . . . Vio temperature co-efficient distribution (-40 °C to 25 °C) . . Vio temperature co-efficient distribution (25 °C to 125 °C) . Input offset voltage vs. supply voltage . . . . . . . . . . . . . . . Input offset voltage vs. input common-mode at VCC = 1.8 V Input offset voltage vs. input common-mode at VCC = 2.7 V Input offset voltage vs. input common-mode at VCC = 5.5 V Input offset voltage vs. temperature. . . . . . . . . . . . . . . . . VOH vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . VOL vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Output current vs. output voltage at VCC = 1.8 V . . . . . . . . Output current vs. output voltage at VCC = 5.5 V . . . . . . . . Input bias current vs. common mode at VCC = 5 V. . . . . . . Input bias current vs. common mode at VCC = 1.8 V . . . . . Input bias current vs. temperature at VCC = 5 V . . . . . . . . Bode diagram at VCC = 1.8 V . . . . . . . . . . . . . . . . . . . . . Bode diagram at VCC = 2.7 V . . . . . . . . . . . . . . . . . . . . . Bode diagram at VCC = 5.5 V . . . . . . . . . . . . . . . . . . . . . Open loop gain vs. frequency . . . . . . . . . . . . . . . . . . . . . Positive slew rate vs. supply voltage . . . . . . . . . . . . . . . . Negative slew rate vs. supply voltage . . . . . . . . . . . . . . . 0.1 Hz to 10 Hz noise . . . . . . . . . . . . . . . . . . . . . . . . . . Noise vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . Noise vs. frequency and temperature . . . . . . . . . . . . . . . Output overshoot vs. load capacitance . . . . . . . . . . . . . . Small signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Large signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Positive overvoltage recovery at VCC = 1.8 V . . . . . . . . . . Positive overvoltage recovery at VCC = 5 V . . . . . . . . . . . Negative overvoltage recovery at VCC = 1.8 V . . . . . . . . . Negative overvoltage recovery at VCC = 5 V . . . . . . . . . . . PSRR vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . Output impedance vs. frequency. . . . . . . . . . . . . . . . . . . Block diagram in the time domain (step 1) . . . . . . . . . . . . Block diagram in the time domain (step 2) . . . . . . . . . . . . Vio cancellation principle . . . . . . . . . . . . . . . . . . . . . . . . Block diagram in the frequency domain . . . . . . . . . . . . . . Input current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . Stability criteria with a serial resistor at VDD = 5 V . . . . . . . Stability criteria with a serial resistor at VDD = 1.8 V. . . . . . Test configuration for Riso . . . . . . . . . . . . . . . . . . . . . . . EMIRR on IN+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxygen sensor principle schematic . . . . . . . . . . . . . . . . . Precision instrumentation amplifier schematic. . . . . . . . . . Low-side current sensing schematic . . . . . . . . . . . . . . . . SC70-5 (or SOT323-5) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 8 . 8 . 8 . 8 . 8 . 8 . 9 . 9 . 9 . 9 . 9 . 9 10 10 10 10 10 10 11 11 11 11 11 11 12 12 12 12 12 12 13 13 13 13 13 13 14 14 14 15 16 17 17 17 18 18 19 19 22 page 35/37 TSZ121, TSZ122, TSZ124 List of figures Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. DS9216 - Rev 11 SOT23-5 package outline . . . . . . . DFN8 2 x 2 package outline . . . . . . DFN8 2 x 2 recommended footprint . MiniSO8 package outline . . . . . . . . SO8 package outline . . . . . . . . . . . QFN16 3x3 package outline . . . . . . QFN16 3x3 recommended footprint. TSSOP14 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 24 25 26 27 28 29 30 page 36/37 TSZ121, TSZ122, TSZ124 IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS9216 - Rev 11 page 37/37