TSZ181H, TSZ182H
Datasheet
Automotive-grade, very high accuracy (25 µV), high bandwidth (3 MHz), high
temperature (150 °C), zero-drift operational amplifiers
Features
•
•
SOT23-5
SO8
•
•
•
•
•
•
•
AEC-Q100 qualified
Very high accuracy and stability:
–
25 µV max. offset voltage at 25 °C
–
44 µV offset voltage over full temperature range
Rail-to-rail input and output
Low supply voltage: 2.2 - 5.5 V
Low power consumption: 1 mA max. at 5 V
Gain bandwidth product: 3 MHz
Extended temperature range: -40 to 150 °C
Micropackage: SOT23-5, SO8
Benefits:
–
Higher accuracy without calibration
–
Accuracy virtually unaffected by temperature change
Applications
Maturity status link
TSZ181H, TSZ182H
Related products
TSZ181, TSZ182
For - 40/125 °C
range
•
•
•
•
High accuracy signal conditioning
Current measurement
Sensor signal conditioning
Automotive
Description
The TSZ181H and TSZ182H are a single and dual operational amplifier, featuring
very low offset voltages with virtually zero-drift versus temperature changes. The
TSZ181H and TSZ182H offer rail-to-rail input and output, excellent speed/power
consumption ratio, and 3 MHz gain bandwidth product, while consuming just 1 mA at
5 V. The device operates over an extended range of -40 to +150°C and features an
ultra-low input bias current. These features make the TSZ181H and TSZ182H ideal
for high-accuracy high-bandwidth sensor interfaces for automotive environment.
DS13229 - Rev 2 - December 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
TSZ181H, TSZ182H
Package pin connections
1
Package pin connections
Figure 1. Pin connections (top view)
SOT23-5 (TSZ181H)
DS13229 - Rev 2
SO8 (TSZ182H)
page 2/26
TSZ181H, TSZ182H
Absolute maximum ratings and operation conditions
2
Absolute maximum ratings and operation conditions
Table 1. Absolute maximum ratings
Symbol
Parameter
VCC
Supply voltage (1)
Vid
Differential input voltage (2)
Vin
Input voltage
Iin
Input current (4)
(3)
Value
Unit
6
V
± VCC
V
(VCC-)-0.2 to (VCC+)+0.2
V
10
mA
Tstg
Storage temperature
-65 to 150
°C
Tj
Junction temperature
160
°C
Rth-ja
ESD
Thermal resistance junction to ambient (5)(6)
SO8
125
SOT23-5
250
Human body model (HBM) (7)
Charged device model (CDM)
4
(8)
1.5
°C/W
kV
1. All voltage values, except differential voltage, are with respect to network ground terminal.
2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
3. VCC - Vin must not exceed 6 V, Vin must not exceed 6 V.
4. Input current must be limited by a resistor in series with the inputs.
5. Rth are typical values.
6. Short-circuits can cause excessive heating and destructive dissipation.
7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin
combinations with other pins floating.
8. Charged device model: all pins plus packages are charged together to the specified voltage and then discharged directly to
ground.
Table 2. Operating conditions
Symbol
DS13229 - Rev 2
Parameter
Value
Unit
2.2 to 5.5
V
VCC
Supply voltage
Vicm
Common mode voltage on input pins
(VCC-)-0.1 to (VCC+)+0.1
V
T
Operating free-air temperature range
-40 to 150
°C
page 3/26
TSZ181H, TSZ182H
Electrical characteristics
3
Electrical characteristics
Table 3. Electrical characteristics (VCC+ = 2.2 V, VCC- = 0 V, Vicm = VCC/2, T = 25 °C, RL=10 kΩ connected to
VCC/2, unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
3.5
35
Unit
DC performance
VIO
|∆VIO/∆T|
T=25 °C
Input offset voltage
Input offset voltage drift(1)
IIB
Input bias current(2)(VOUT=VCC/2)
IIO
current(2)
CMR1
Avd
VOH
VOL
Input offset
(VOUT=VCC/2)
54
Tmin < T < Tmax
0.15
T = 25 °C
30
Tmin < T < Tmax
T = 25 °C
60
Tmin < T < Tmax
96
Tmin < T < Tmax
90
Large signal voltage gain,
T=25 °C
112
VOUT =0.5 V to (VCC - 0.5 V)
Tmin < T < Tmax
98
High-level output voltage,
T=25 °C
VOH = VCC - VOUT
Tmin < T < Tmax
Low-level output voltage
IOUT
Isource (VOUT =0 V)
10
4
2.37
3.5
Tmin < T < Tmax
1.9
Tmin < T < Tmax
40
30
mV
70
T = 25 °C
VOUT = VCC/2, RL>1 MΩ
dB
70
Tmin < T < Tmax
T = 25 °C
pA
130
Tmin < T < Tmax
Supply current per channel,
400
115
15
T = 25 °C
T = 25 °C
µV/°C
600
T = 25 °C
Common-mode rejection
µV
200
400
Vic = 0 V to VCC, VOUT =VCC/2, RL>1 MΩ
ratio(3),
Isink (VOUT = VCC)
ICC
Tmin < T < Tmax
6
4
0.7
mA
1
1.2
AC performance
GBP
T = 25 °C
1.6
RL = 10 kΩ, CL = 100 pF
Tmin < T < Tmax
1.1
Φm
Phase margin
Gm
Gain margin
SR
Slew rate (4)
ts
Settling time
en
Equivalent input noise voltage density
en-pp
Cs
DS13229 - Rev 2
Gain bandwidth product,
RL = 10 kΩ, CL=100 pF
T=25 °C
Tmin < T < Tmax
3
2.3
MHz
59
degrees
16
dB
4.6
2.5
V/µs
To 0.1%, Vin = 0.8 Vpp
500
ns
f = 1 kHz
50
f =10 kHz
50
Voltage noise
f = 0.1 to 10 Hz
0.6
µVpp
Channel separation
f = 1 kHz
120
dB
nV/√Hz
page 4/26
TSZ181H, TSZ182H
Electrical characteristics
Symbol
tinit
Parameter
Initialization time, G = 100(5)
Conditions
Min.
Typ.
T = 25 °C
60
Tmin < T < Tmax
100
Max.
Unit
µs
1. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the
same temperature.
2. Guaranteed by design.
3. CMR is defined as 20xLOG(∆Vicm/∆Vio).
4. Slew rate value is calculated as the average between positive and negative slew rates.
5. Initialization time is defined as the delay between the moment when supply voltage exceeds 2.2 V and output voltage
stabilization.
DS13229 - Rev 2
page 5/26
TSZ181H, TSZ182H
Electrical characteristics
Table 4. Electrical characteristics (VCC+ = 3.3 V, VCC- = 0 V, Vicm = VCC/2, T = 25 °C, RL=10 kΩ connected to
VCC/2, unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
2
30
Unit
DC performance
VIO
|∆VIO/∆T|
IIB
IIO
CMR1
T = 25 °C
Input offset voltage
Input offset voltage drift(1)
Input bias current (VOUT=VCC/2)
Input offset current
(2)
(VOUT=VCC/2)
Tmin < T < Tmax
49
Tmin < T < Tmax
0.15
T = 25 °C
Tmin < T < Tmax
Tmin < T < Tmax
T = 25 °C
104
Vic=0 V to VCC, VOUT =VCC/2, RL>1 MΩ
Tmin < T < Tmax
100
Common-mode rejection ratio(3),
Vic = 0 to VCC-1.8 V
VOUT =VCC/2, RL>1 MΩ
Tmin < T < Tmax,
VOH
VOL
VOUT =0.5 V to (VCC -0.5 V)
Tmin < T < Tmax
110
High-level output voltage,
T = 25 °C
VOH = VCC - VOUT
Tmin < T < Tmax
Isource (VOUT =0 V)
120
132
104
120
IOUT
138
16
11
Tmin < T < Tmax
10
Tmin < T < Tmax
7.1
Supply current per channel,
T = 25 °C
VOUT = VCC /2, RL>1 MΩ
Tmin < T < Tmax
30
mV
70
T = 25 °C
Tmin < T < Tmax
40
70
T = 25 °C
T = 25 °C
pA
dB
T = 25 °C
Isink (VOUT = VCC)
ICC
106
Large signal voltage gain,
Low-level output voltage
400
600
Common-mode rejection ratio (3),
Vic = 0 to VCC-2 V
Avd
60
µV/°C
200
400
T = 25 °C
T = 25 °C,
CMR2
30
µV
6
15
11
mA
3.8
0.7
1
1.2
AC performance
GBP
T = 25 °C
RL=10 kΩ, CL=100 pF
Tmin < T < Tmax
Φm
Phase margin
Gm
Gain margin
SR
Slew rate(4)
ts
Settling time
en
Equivalent input noise voltage density
en-pp
Cs
DS13229 - Rev 2
Gain bandwidth product,
2
2.8
1.5
RL = 10 kΩ, CL = 100 pF
T = 25 °C
2.6
Tmin < T < Tmax
2.1
MHz
56
degrees
15
dB
4.5
V/µs
To 0.1%, Vin = 1.2 Vpp
550
ns
f=1 kHz
40
f = 10 kHz
40
Voltage noise
f = 0.1 to 10 Hz
0.5
µVpp
Channel separation
f=1 kHz
120
dB
nV/√Hz
page 6/26
TSZ181H, TSZ182H
Electrical characteristics
Symbol
tint
Parameter
Initialization time, G=100 (5)
Conditions
Min.
Typ.
T = 25 °C
60
Tmin < T < Tmax
100
Max.
Unit
µs
1. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the
same temperature.
2. Guaranteed by design.
3. CMR is defined as 20xLOG(∆Vicm/∆Vio).
4. Slew rate value is calculated as the average between positive and negative slew rates.
5. Initialization time is defined as the delay between the moment when supply voltage exceeds 2.2 V and output voltage
stabilization.
DS13229 - Rev 2
page 7/26
TSZ181H, TSZ182H
Electrical characteristics
Table 5. Electrical characteristics (VCC+ = 5 V, VCC- = 0 V, Vicm=VCC/2, T = 25 °C, RL=10 kΩ connected to
VCC/2, unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
1
25
Unit
DC performance
VIO
|∆VIO/∆T|
IIB
IIO
CMR1
T = 25 °C
Input offset voltage
Input offset voltage drift(1)
Input bias current (2) (VOUT=VCC/2)
Input offset current
(2)
(VOUT=VCC/2)
Common-mode rejection
ratio(3),
Vic=0 V to VCC, VOUT =VCC/2, RL>1 MΩ
Tmin < T < Tmax
44
Tmin < T < Tmax
0.15
T = 25 °C
Tmin < T < Tmax
CMR2
Common-mode rejection
Vic=0 V to VCC , VOUT =VCC/2, RL>1 MΩ
Tmin < T < Tmax
108
Tmin < T < Tmax
106
Vic = 0 to VCC-1.8 V
Tmin < T < Tmax,
Avd
EMIRR
VOH
VOL
105
VCC=2.2 to 5.5 V, Vic=0 V, RL>1 MΩ
Tmin < T < Tmax
104
Large signal voltage gain,
T=25 °C
120
VOUT =0.5 V to (VCC - 0.5 V)
Tmin < T < Tmax
110
126
136
123
dB
144
VRF=100 mVp, f=400 MHz
52
VRF=100 mVp, f=900 MHz
52
VRF=100 mVp, f=1800 MHz
72
VRF=100 mVp, f=2400 MHz
85
High-level output voltage,
T=25 °C
18
VOH = VCC - VOUT
Tmin < T < Tmax
Low-level output voltage
IOUT
Isource (VOUT =0 V)
13
Tmin < T < Tmax
20
Tmin < T < Tmax
14
T = 25 °C
15
Tmin < T < Tmax
9
VOUT = VCC/2, RL>1 MΩ
Tmin < T < Tmax
30
mV
70
T = 25 °C
T = 25 °C
40
70
T = 25 °C
Supply current per channel,
pA
110
T = 25 °C
Isink (VOUT = VCC)
ICC
112
Supply voltage rejection ratio
EMI rejection ratio(5)
400
600
T = 25 °C
Vic = 0 to VCC-2 V
SVR1
60
µV/°C
200
400
T = 25 °C
T = 25 °C,
ratio(3),
30
µV
29
25
0.8
mA
1
1.2
AC performance
GBP
DS13229 - Rev 2
Gain bandwidth product,
RL=10 kΩ, CL=100 pF
Φm
Phase margin
Gm
Gain margin
SR
Slew rate(6)
T=25 °C
Tmin < T < Tmax
2
1.5
RL=10 kΩ, CL=100 pF
T=25 °C
3
2.9
MHz
56
Degrees
15
dB
4.7
V/µs
page 8/26
TSZ181H, TSZ182H
Electrical characteristics
Symbol
SR
Parameter
Slew
rate(6)
Conditions
Tmin < T < Tmax
Min.
Typ.
Max.
Unit
V/µs
2.4
To 0.1%, Vin=1.5 Vpp
600
ns
To 0.01%, Vin=1 Vpp
4
µs
f = 1 kHz
37
f = 10 kHz
37
Voltage noise
f=0.1 to 10 Hz
0.4
µVpp
Cs
Channel separation
f = 100 Hz
135
dB
tinit
Initialization time, G=100(7)
T = 25 °C
60
Tmin < T < Tmax
100
ts
Settling time
en
Equivalent input noise voltage density
en-pp
nV/√Hz
µs
1. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the
same temperature.
2. Guaranteed by design
3. CMR is defined as 20xLOG(∆Vicm/∆Vio).
4. SVR is defined as 20xLOG(∆Vcc/∆Vio).
5. EMIRR is defined as -20Log(VRF_Peak/∆Vio), tested on the MiniSO8 package, RF injection on the IN- pin.
6. Slew rate value is calculated as the average between positive and negative slew rates.
7. Initialization time is defined as the delay between the moment when supply voltage exceeds 2.2 V and output voltage
stabilization.
DS13229 - Rev 2
page 9/26
TSZ181H, TSZ182H
Electrical characteristics
DS13229 - Rev 2
Figure 2. Supply current vs supply voltage
Figure 3. Input offset voltage distribution at
VCC = 5 V
Figure 4. Input offset voltage distribution at
VCC = 3.3 V
Figure 5. Input offset voltage distribution at
VCC = 2.2 V
Figure 6. Input offset voltage distribution at
VCC = 5 V, T = 150 °C
Figure 7. Input offset voltage distribution at
VCC = 5 V, T = -40 °C
page 10/26
TSZ181H, TSZ182H
Electrical characteristics
DS13229 - Rev 2
Figure 8. Input offset voltage distribution at
VCC=2.2 V, T = 150 °C
Figure 9. Input offset voltage distribution at
VCC=2.2 V, T = -40 °C
Figure 10. Input offset voltage vs supply voltage
Figure 11. Input offset voltage vs input common
mode at VCC= 5 V
Figure 12. Input offset voltage vs input common
mode at VCC= 3.3 V
Figure 13. Input offset voltage vs input common
mode at VCC= 2.2 V
page 11/26
TSZ181H, TSZ182H
Electrical characteristics
DS13229 - Rev 2
Figure 14. Input offset voltage vs temperature
Figure 15. VOH vs supply voltage
Figure 16. VOL vs supply voltage
Figure 17. Output current vs output voltage at
VCC = 5 V
Figure 18. Output current vs. output voltage at
VCC = 2.2 V
Figure 19. Input bias current vs common-mode at
VCC = 5 V
page 12/26
TSZ181H, TSZ182H
Electrical characteristics
Figure 20. Input bias current vs. temperature at
VCC = 5 V
DS13229 - Rev 2
Figure 21. Output rail linearity
Figure 22. Bode diagram at VCC=5 V
Figure 23. Bode diagram at VCC=2.2 V
Figure 24. Bode diagram at VCC=3.3 V
Figure 25. Open loop gain vs frequency
page 13/26
TSZ181H, TSZ182H
Electrical characteristics
DS13229 - Rev 2
Figure 26. Positive slew rate vs supply voltage
Figure 27. Negative slew rate vs supply voltage
Figure 28. Noise 0.1 – 10 Hz vs time
Figure 29. Noise vs frequency
Figure 30. Output overshoot vs load capacitance
Figure 31. Small signal VCC = 5 V
page 14/26
TSZ181H, TSZ182H
Electrical characteristics
DS13229 - Rev 2
Figure 32. Small signal VCC = 2.2 V
Figure 33. Large signal VCC = 5 V
Figure 34. Large signal VCC = 2.2 V
Figure 35. Negative overvoltage recovery
VCC = 2.2 V
Figure 36. Positive overvoltage recovery VCC = 5 V
Figure 37. Output impedance vs frequency
page 15/26
TSZ181H, TSZ182H
Electrical characteristics
Figure 38. Settling time positive step (-2 V to 0 V)
Figure 39. Settling time negative step (2 V to 0 V)
at t=0
Figure 40. Settling time positive step (-0.8 V to 0 V)
Figure 41. Settling time negative step (0.8 V to 0 V)
0
Figure 42. Maximum output voltage vs frequency
DS13229 - Rev 2
Figure 43. Crosstalk vs frequency
page 16/26
TSZ181H, TSZ182H
Electrical characteristics
Figure 44. PSSR vs frequency
DS13229 - Rev 2
page 17/26
TSZ181H, TSZ182H
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
4.1
SO8 package information
Figure 45. SO8 package outline
Table 6. SO-8 mechanical data
Dim.
mm
Min.
Typ.
A
Max.
Min.
Typ.
1.75
0.25
Max.
0.069
A1
0.1
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.01
D
4.8
4.9
5
0.189
0.193
0.197
E
5.8
6
6.2
0.228
0.236
0.244
E1
3.8
3.9
4
0.15
0.154
0.157
e
0.004
0.01
0.049
1.27
0.05
h
0.25
0.5
0.01
0.02
L
0.4
1.27
0.016
0.05
L1
k
DS13229 - Rev 2
Inches
1.04
0
0.04
8°
1°
8°
page 18/26
TSZ181H, TSZ182H
SO8 package information
Dim.
ccc
DS13229 - Rev 2
mm
Min.
Typ.
Inches
Max.
0.1
Min.
Typ.
Max.
0.004
page 19/26
TSZ181H, TSZ182H
SOT23-5 package information
4.2
SOT23-5 package information
Figure 46. SOT23-5 package outline
Table 7. SOT23-5 mechanical data
Dimensions
Millimeters
Ref.
A
Min.
Typ.
Max.
Min.
Typ.
Max.
0.90
1.20
1.45
0.035
0.047
0.057
A1
DS13229 - Rev 2
Inches
0.15
0.006
A2
0.90
1.05
1.30
0.035
0.041
0.051
B
0.35
0.40
0.50
0.014
0.016
0.020
C
0.09
0.15
0.20
0.004
0.006
0.008
D
2.80
2.90
3.00
0.110
0.114
0.118
D1
1.90
0.075
e
0.95
0.037
E
2.60
2.80
3.00
0.102
0.110
0.118
F
1.50
1.60
1.75
0.059
0.063
0.069
L
0.10
0.35
0.60
0.004
0.014
0.024
K
0 degrees
10 degrees
0 degrees
10 degrees
page 20/26
TSZ181H, TSZ182H
Ordering information
5
Ordering information
Table 8. Ordering information
Order code
Package
TSZ182HYDT (1)
SO8
TSZ181HYLT (1)
SOT23-5
Packing
Tape and reel
Marking
TSZ182H
K229
1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 &
Q002 or equivalent.
DS13229 - Rev 2
page 21/26
TSZ181H, TSZ182H
Revision history
Table 9. Document revision history
Date
Version
20-Jan-2020
1
09-Dec-2020
DS13229 - Rev 2
2
Changes
Initial release.
Added new part number TSZ181H and new Section 4.2 SOT23-5 package
information
Updated package figure on the cover page, Figure 1 and new order code in
Table 8.
page 22/26
TSZ181H, TSZ182H
Contents
Contents
1
Package pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2
Absolute maximum ratings and operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5
4.1
SO8 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2
SOT23-5 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DS13229 - Rev 2
page 23/26
TSZ181H, TSZ182H
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics (VCC+ = 2.2 V, VCC- = 0 V, Vicm = VCC/2, T = 25 °C, RL=10 kΩ connected to VCC/2, unless
otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics (VCC+ = 3.3 V, VCC- = 0 V, Vicm = VCC/2, T = 25 °C, RL=10 kΩ connected to VCC/2, unless
otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics (VCC+ = 5 V, VCC- = 0 V, Vicm=VCC/2, T = 25 °C, RL=10 kΩ connected to VCC/2, unless
otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SOT23-5 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DS13229 - Rev 2
page 24/26
TSZ181H, TSZ182H
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
DS13229 - Rev 2
Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . .
Supply current vs supply voltage. . . . . . . . . . . . . . . . . .
Input offset voltage distribution at VCC = 5 V . . . . . . . . . .
Input offset voltage distribution at VCC = 3.3 V . . . . . . . .
Input offset voltage distribution at VCC = 2.2 V . . . . . . . .
Input offset voltage distribution at VCC = 5 V, T = 150 °C .
Input offset voltage distribution at VCC = 5 V, T = -40 °C .
Input offset voltage distribution at VCC=2.2 V, T = 150 °C .
Input offset voltage distribution at VCC=2.2 V, T = -40 °C .
Input offset voltage vs supply voltage . . . . . . . . . . . . . .
Input offset voltage vs input common mode at VCC= 5 V .
Input offset voltage vs input common mode at VCC= 3.3 V
Input offset voltage vs input common mode at VCC= 2.2 V
Input offset voltage vs temperature . . . . . . . . . . . . . . . .
VOH vs supply voltage . . . . . . . . . . . . . . . . . . . . . . . . .
VOL vs supply voltage . . . . . . . . . . . . . . . . . . . . . . . . .
Output current vs output voltage at VCC = 5 V. . . . . . . . .
Output current vs. output voltage at VCC = 2.2 V . . . . . . .
Input bias current vs common-mode at VCC = 5 V . . . . . .
Input bias current vs. temperature at VCC = 5 V . . . . . . .
Output rail linearity . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bode diagram at VCC=5 V . . . . . . . . . . . . . . . . . . . . . .
Bode diagram at VCC=2.2 V . . . . . . . . . . . . . . . . . . . . .
Bode diagram at VCC=3.3 V . . . . . . . . . . . . . . . . . . . . .
Open loop gain vs frequency . . . . . . . . . . . . . . . . . . . .
Positive slew rate vs supply voltage. . . . . . . . . . . . . . . .
Negative slew rate vs supply voltage . . . . . . . . . . . . . . .
Noise 0.1 – 10 Hz vs time . . . . . . . . . . . . . . . . . . . . . .
Noise vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output overshoot vs load capacitance . . . . . . . . . . . . . .
Small signal VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . .
Small signal VCC = 2.2 V . . . . . . . . . . . . . . . . . . . . . . .
Large signal VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . .
Large signal VCC = 2.2 V . . . . . . . . . . . . . . . . . . . . . . .
Negative overvoltage recovery VCC = 2.2 V . . . . . . . . . .
Positive overvoltage recovery VCC = 5 V . . . . . . . . . . . .
Output impedance vs frequency . . . . . . . . . . . . . . . . . .
Settling time positive step (-2 V to 0 V). . . . . . . . . . . . . .
Settling time negative step (2 V to 0 V) . . . . . . . . . . . . .
Settling time positive step (-0.8 V to 0 V) . . . . . . . . . . . .
Settling time negative step (0.8 V to 0 V) . . . . . . . . . . . .
Maximum output voltage vs frequency . . . . . . . . . . . . . .
Crosstalk vs frequency . . . . . . . . . . . . . . . . . . . . . . . .
PSSR vs frequency . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . .
SOT23-5 package outline . . . . . . . . . . . . . . . . . . . . . .
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. 2
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page 25/26
TSZ181H, TSZ182H
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service
names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
DS13229 - Rev 2
page 26/26
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湘ICP备2023018690号
