UA748M

UA748 PRECISION SINGLE OPERATIONAL AMPLIFIER s INPUT OFFSET VOLTAGE : 3mV max. OVER s FREQUENCY COMPENSATION WITH A s OPERATION FROM ±5V to ±15V s LOW POWER CONSUMPTION : s CONTINUOUS SHORT-CIRCUIT PROTECTION s OPERATION AS A COMPARATOR WITH DIFFERENTIAL INPUTS AS HIGH AS ±30V s NO LATCH-UP WHEN COMMON-MODE RANGE IS EXCEEDED s SAME PIN CONFIGURATION AS THE LM101A DESCRIPTION The UA748 is a general purpose operational amplifier built on a single silicon chip. The resulting close match and tight thermal coupling gives low offsets and temperature drift as well as fast recovery from thermal transients. s Short-circuit protection s Offset voltage null capability s Large common-mode and differential voltage ranges s Low power consumption s No latch-up The unity-gain compensation specified makes the circuit stable for all feedback configurations, even with capacitive loads. However, it is possible to optimize compensation for best high frequency performance at any gain. The low power dissipation permits high voltage operation and simplifies packaging in full-temperature range systems. PIN CONNECTIONS (top view) 1 - Offset null 1/frequency compensation 2 - Inverting input 3 - Non-inverting input 4 - VCC5 - Offset null 2 6 - Output 7 - VCC+ 8 - Frequency compensation D SO8 (Plastic Micropackage) TEMPERATURE SINGLE 30pF CAPACITOR (C1) 50mW AT ±15V N DIP8 (Plastic Package) ORDER CODE Package Part Number Temperature Range N UA748C 0°C, +70°C UA748I -40°C, +105°C UA748M -55°C, +125°C Example : UA748CN • • • D • • • N = Dual in Line Package (DIP) D = Small Outline Package (SO) - also available in Tape & Reel (DT) 1 2 3 4 8 7 6 5 December 2001 1/7 UA748 SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VCC Vid Vi Ptot Toper Tstg 1. Parameter Supply voltage Differential Input Voltage Input Voltage Power Dissipation Output Short-circuit Duration Operating Free-air Temperature Range Storage Temperature Range 1) UA748M UA748I ±22 ±30 ±15 500 Infinite UA748C Unit V V V mW -55 to +125 -40 to +105 -65 to +150 0 to +70 °C °C Power dissipation must be considered to ensure maximum junction temperature (Tj) is not exceeded. 2/7 UA748 ELECTRICAL CHARACTERISTICS VCC = ±15V, Tamb = +25°C, C1 = 30pF (unless otherwise specified) UA748I/M Symbol Parameter Min. Vio Input Offset Voltage (Rs ≤ 10kΩ) Tamb = +25°C Tmin ≤ Tamb ≤ Tmax Input Offset Current Tamb = +25°C Tmin ≤ Tamb ≤ Tmax Input Bias Current Tamb = +25°C Tmin ≤ Tamb ≤ Tmax Large Signal Voltage Gain (Vo = ±10V, RL = 2kΩ) Tamb = +25°C Tmin ≤ Tamb ≤ Tmax Supply Voltage Rejection Ratio (Rs ≤ 10kΩ) Tamb = +25°C Tmin ≤ Tamb ≤ Tmax Supply Current, no load Tamb = +25°C Tmin ≤ Tamb ≤ Tmax Input Common Mode Voltage Range (VCC = ±20V) Tamb = +25°C Tmin ≤ Tamb ≤ Tmax Common Mode Rejection Ratio (RS ≤ 10kΩ) Tamb = +25°C Tmin ≤ Tamb ≤ Tmax ±15 ±15 80 80 10 12 10 12 10 0.25 96 30 14 13 50 50 25 80 80 Typ. 0.7 Max. 2 3 10 20 75 10 25 15 70 70 3 3 ±15 ±15 70 70 10 12 10 12 10 0.25 96 30 14 13 50 Min. Typ. 2 Max. 7.5 10 50 70 250 300 mV UA748C Unit Iio 1.5 2 nA Iib 25 70 nA Avd 100 100 V/mV SVR 96 96 dB ICC 1.8 1.8 3 3 mA Vicm V CMR IOS dB mA Output short Circuit Current Output Voltage Swing (VCC = ±15V) Tamb = +25°C RL = 10kΩ RL = 2kΩ ±Vopp Tmin ≤ Tamb ≤ Tmax RL = 10kΩ RL = 2kΩ SR tr Kov Zi Ro GBP THD DIio DVio 1. V Slew Rate 1) Vi = ±10V, RL = 2kΩ, CL = 100pF, unity Gain Rise Time Vi = ±20mV, RL = 2kΩ, CL = 100pF, unity Gain Overshoot Vi = 20mV, RL = 2kΩ, CL = 100pF, unity Gain Input Impedance (VCC = ±15V) Output Resistance (VCC = ±15V) Gain Bandwith Product Vi =10mV, RL = 2kΩ, CL = 100pF, f =100kHz Total Harmonic Distortion f =1kHz, Av =20dB, RL =2kΩ, Vo =2Vpp, CL = 100pF Input Offset Current Drift 25°C ≤ Tmax Tmin ≤ Tamb ≤ Tmax Input Offset Voltage Drift Tmin ≤ Tamb ≤ Tmax 0.5 0.3 5 0.5 0.3 5 V/µs µs % MΩ Ω MHz % 300 600 30 pA/°C µV/°C 1.5 4 75 1.5 4 75 0.5 1 0.015 10 20 3 100 200 15 0.5 1 0.015 10 20 6 May be improved up to 10V/µs in inverting amplifier configuration. 3/7 UA748 4/7 UA748 SINGLE POLE COMPENSATION 5/7 UA748 PACKAGE MECHANICAL DATA 8 PINS - PLASTIC DIP Millimeters Dim. Min. A a1 B b b1 D E e e3 e4 F i L Z 0.51 1.15 0.356 0.204 7.95 2.54 7.62 7.62 6.6 5.08 3.81 1.52 Typ. 3.32 1.65 0.55 0.304 10.92 9.75 0.020 0.045 0.014 0.008 0.313 Max. Min. Inches Typ. 0.131 0.065 0.022 0.012 0.430 0.384 0.100 0.300 0.300 0260 0.200 0.150 0.060 Max. 3.18 0.125 6/7 UA748 PACKAGE MECHANICAL DATA 8 PINS - PLASTIC MICROPACKAGE (SO) L C a3 b1 c1 a2 s e3 E D M 8 5 F 1 4 Millimeters Dim. Min. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 0.1 0.65 0.35 0.19 0.25 4.8 5.8 1.27 3.81 3.8 0.4 4.0 1.27 0.6 8° (max.) 0.150 0.016 Typ. Max. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45° (typ.) 5.0 6.2 0.189 0.228 Min. 0.004 0.026 0.014 0.007 0.010 a1 b A Inches Typ. Max. 0.069 0.010 0.065 0.033 0.019 0.010 0.020 0.197 0.244 0.050 0.150 0.157 0.050 0.024 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States © http://www.st.com 7/7