UC3842

® U C2842A/3A/4A/5A UC3842A/3A/4A/5A HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER . . . . . . . . . TRIMMED OSCILLATOR DISCHARGE CURRENT CURRENT MODE OPERATION TO 500kHz AUTOMATIC FEED FORWARD COMPENSATION LATCHING PWM FOR CYCLE-BY-CYCLE CURRENT LIMITING INTERNALLY TRIMMED REFERENCE WITH UNDERVOLTAGE LOCKOUT HIGH CURRENT TOTEM POLE OUTPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS LOW START-UP CURRENT (< 0.5mA) DOUBLE PULSE SUPPRESSION Minidip S O8 DESCRIPTION TheUC384xA family ofcontrolICs providesthe necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include a trimmed oscillator for precise DUTY CYCLE CONTROL under voltage lockoutfeaturingstart-up current less than0.5mA,a precision reference trimmed for accuracy at the error amp input, logicto insure latched operation,a PWM comparatorwhich alsoprovidescurrent limit control, and a totem pole output stage designed to source or sink high peakcurrent. The outputstage, suitable for driving N-Channel MOSFETs, is low in the offstate. Differences between members of this family are the under-voltagelockout thresholds and maximum duty cycle ranges. The UC3842A and UC3844A have UVLO thresholds of 16V (on) and 10V (off), ideally suitedoff-lineapplicationsThecorrespondingthresholds for the UC3843A and UC3845A are 8.5 V and 7.9V. The UC3842A and UC3843A can operate to dutycycles approaching100%.A range of the zeroto < 50 % is obtainedby theUC3844Aand UC3845Aby the addition of an internal toggle flip flopwhich blanks the output off every otherclock cycle. BLOCK DIAGRAM (toggle flip flop used only in UC3844A and UC3845A) Vi 7 34V GROUND 5 UVLO S/R 5V REF INTERNAL BIAS VREF GOOD LOGIC RT/CT 4 OSC ERROR AMP. 2R R 1V T 8 VREF 5V 50mA 2.50V 6 OUTPUT VFB COMP CURRENT SENSE 2 1 3 + - S R CURRENT SENSE COMPARATOR PWM LATCH UC3842A D95IN331 March 1999 1/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A ABSOLUTE MAXIMUM RATINGS Symbol Vi Vi IO EO Parameter Supply Voltage (low impedance source) Supply Voltage (Ii < 30mA) Output Current Output Energy (capacitive load) Analog Inputs (pins 2, 3) Error Amplifier Output Sink Current Ptot Ptot Tstg TJ TL Power Dissipation at Tamb ≤ 25 °C (Minidip) Power Dissipation at Tamb ≤ 25 °C (SO8) Storage Temperature Range Junction Operating Temperature Lead Temperature (soldering 10s) Valu e 30 Self Limiting ±1 5 – 0.3 to 5.5 10 1.25 800 – 65 to 150 – 40 to 150 300 A µJ V mA W mW °C °C °C Un it V * All voltages are with respect to pin 5, all currents are positive into the specified terminal. PIN CONNECTION (top view) Minidip/SO8 COMP VFB ISENSE RT/CT 1 2 3 4 D95IN332 8 7 6 5 VREF Vi OUTPUT GROUND PIN FUNCTIONS No 1 2 3 4 5 6 7 8 Function COMP VFB ISENSE RT/CT GROUND OUTPUT VCC Vref Description This pin is the Error Amplifier output and is made available for loop compensation. This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and cpacitor CT to ground. Operation to 500kHz is possible. This pin is the combined control circuitry and power ground. This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sunk by this pin. This pin is the positive supply of the control IC. This is the reference output. It provides charging current for capacitor CT through resistor RT. ORDERING NUMBERS SO8 UC2842AD1; UC2843AD1; UC2844AD1; UC2845AD1; UC3842AD1 UC3843AD1 UC3844AD1 UC3845AD1 Minidip UC2842AN; UC2843AN; UC2844AN; UC2845AN; UC3842AN UC3843AN UC3844AN UC3845AN 2/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A THERMAL DATA Symbo l Rth j-amb Description Thermal Resistance Junction-ambient. max. Minid ip 100 SO 8 150 Unit °C/W ELECTRICAL CHARACTERISTICS ( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85°C for UC284XA; 0 < Tamb < 70°C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF) Symbo l Parameter T est Cond it ion s UC284XA UC384XA Min. T yp. Max. Min. Typ . Max. 4.95 5.00 5.05 4.90 5.00 5.10 2 3 0.2 4.9 50 5 -30 Tj = 25°C TA = Tlow to Thigh (peak to peak) 47 – – – 7.8 25 -30 47 – – – 7.8 5.1 4.82 50 5 25 20 25 2 3 0.2 5.18 20 25 Uni t REFERENCE SECTION VREF ∆V REF ∆V REF Output Voltage Line Regulation Load Regulation Tj = 25°C Io = 1mA 12V ≤ Vi ≤ 25V 1 ≤ Io ≤ 20mA (Note 2) Line, Load, Temperature 10Hz ≤ f ≤ 10KHz Tj = 25°C (note 2) Tamb = (note 2) 125°C, 1000Hrs V mV mV mV/°C V µV mV mA KHz % % V mA V µA dB MHz dB mA mA V 1.1 V ∆VREF/∆T Temperature Stability Total Output Variation eN Output Noise Voltage Long Term Stability ISC Output Short Circuit -100 -180 52 0.2 5 1.6 8.3 57 1 – – 8.8 -100 -180 52 0.2 5 1.6 8.3 57 1 – – 8.8 OSCILLATOR SECTION fOSC Frequency ∆fOSC/∆V ∆fOSC/∆T VOSC Idischg V2 Ib BW PSRR Io Io Frequency Change with Temp. Oscillator Voltage Swing Frequency Change with Volt. VCC = 12V to 25V Discharge Current (VOSC =2V) TJ = 25°C Input Voltage Input Bias Current AVOL Unity Gain Bandwidth Power Supply Rejec. Ratio Output Sink Current Output Source Current VOUT High VOUT Low VPIN1 = 2.5V VFB = 5V 2V ≤ Vo ≤ 4V TJ = 25°C 12V ≤ Vi ≤ 25V VPIN2 = 2.7V VPIN1 = 1.1V VPIN2 = 2.3V VPIN1 = 5V VPIN2 = 2.3V; R L = 15KΩ to Ground VPIN2 = 2.7V; R L = 15KΩ to Pin 8 (note 3 & 4) VPIN1 = 5V (note 3) 12 ≤ Vi ≤ 25V (note 3) ERROR AMP SECTION 2.45 2.50 2.55 2.42 2.50 2.58 -0.1 65 0.7 60 2 -0.5 5 90 1 70 12 -1 6.2 0.8 1.1 -1 65 0.7 60 2 -0.5 5 -0.1 90 1 70 12 -1 6.2 0.8 -2 CURRENT SENSE SECTION GV Gain V3 SVR Ib Maximum Input Signal Supply Voltage Rejection Input Bias Current Delay to Output 2.85 0.9 3 1 70 -2 150 3.15 2.85 1.1 -10 300 0.9 3 1 70 -2 150 3.15 1.1 -10 300 V/V V dB µA ns 3/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A ELECTRICAL CHARACTERISTICS (continued) Symbo l OUTPUT SECTION VOL VOH VOLS tr tf Output Low Level ISINK = 20mA ISINK = 200mA Output High Level ISOURCE = 20mA ISOURCE = 200mA UVLO Saturation Rise Time Fall Time Start Threshold VCC = 6V; ISINK = 1mA Tj = 25°C CL = 1nF (2) Tj = 25°C CL = 1nF (2) X842A/4A X843A/5A Min Operating Voltage After Turn-on PWM SECTION Maximum Duty Cycle X842A/3A X844A/5A Minimum Duty Cycle TOTAL STANDBY CURRENT Ist Ii V iz Start-up Current Vi = 6.5V for UCX843A/45A Vi = 14V for UCX842A/44A Operating Supply Current Zener Voltage VPIN2 = VPIN3 = 0V Ii = 25mA 30 0.3 0.3 12 36 0.5 0.5 17 30 0.3 0.3 12 36 0.5 0.5 17 mA mA mA V 94 47 96 48 100 50 0 94 47 96 48 100 50 0 % % % X842A/4A X843A/5A 15 7.8 9 7.0 13 12 0.1 1.6 13.5 13.5 0.7 50 50 16 8.4 10 7.6 1.2 150 150 17 9.0 11 8.2 14.5 7.8 8.5 7.0 0.4 2.2 13 12 0.1 1.6 13.5 13.5 0.7 50 50 16 8.4 10 7.6 1.2 150 150 17.5 9.0 11.5 8.2 0.4 2.2 V V V V V ns ns V V V V Parameter T est Cond itions UC284XA UC384XA Min . Typ . Max. Min. T yp. Max. Un it UNDER-VOLTAGE LOCKOUT SECTION N otes : 1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close to Tamb as possible. 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at trip point of latch with V PIN2 = 0. 4. Gain defined as : ∆ VPIN1 A= ; 0 ≤ VPIN3 ≤ 0.8 V ∆ VPIN3 5. Adjust Vi above the start threshold before setting at 15 V. 4/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A Figure 1: Open Loop Test Circuit. VREF 4.7KΩ 2N2222 100KΩ ERROR AMP. ADJUST 4.7KΩ 1KΩ ISENSE ADJUST 5KΩ COMP VFB ISENSE RT/CT RT VREF 1 2 8 7 Vi 0.1µF OUTPUT GROUND 1W 1KΩ OUTPUT A 0.1µF Vi UC3842A 3 4 6 5 CT D95IN343 GROUND High peak currents associatedwith capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5 KΩ potentiometerareusedto samplethe oscillator waveform and apply an adjustable ramp to pin 3. Figure 2: Oscillator Frequency vs Timing Resistance fo (Hz) D96IN362 Figure 3: Maximum Duty Cycle vs Timing Resistor fo (Hz) D96IN363 80 1M CT =4 70 pF 1nF 60 100K 2.2 nF 4.7 nF 40 10K 20 1K 300 1K 3K 10K 30K RT(Ω) 0 300 1K 3K 10K 30K RT(Ω) 5/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A Figure 4: Oscillator Discharge Current vs. Temperature. I dischg (mA) D95IN335 Figure 5: Error Amp Open-Loop Gain and Phase vs. Frequency. (dB) 80 D95IN337 φ 30 60 90 Vi=15V VOSC=2V 8.5 Gain 60 Vi=15V VO=2V to 4V RL=100K TA=25°C 8.0 40 Phase 20 120 150 180 f(Hz) 7.5 0 7.0 -55 -25 0 25 50 75 -20 10 100 TA(°C) 100 1K 10K 100K 1M Figure 6: Current Sense Input Threshold vs. Error Amp Output Voltage. Vth (V) 1.0 0.8 D95IN338 Figure 7: Reference Voltage Change vs. Source Current. 60 D95IN339 Vi=15V 50 Vi=15V TA=25°C 40 TA=-40°C TA=125°C TA=125°C 0.6 0.4 30 20 TA=-40°C 0.2 0.0 10 0 0 2 4 6 VO(V) 0 20 40 60 TA=25°C 80 100 Iref(mA) Figure 8: Reference Short Circuit Current vs. Temperature. ISC (mA) 100 90 80 70 60 50 -55 -25 0 25 50 75 Vi=15V RL≤0.1Ω D95IN340 100 TA(°C) 6/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A Figure 9: Output Saturation Voltage vs. Load Current. Vsat (V) D95IN341 Figure 10: Supply Current vs. Supply Voltage. Ii (mA) 20 D95IN342 Vi -1 -2 Source Saturation (Load to Ground) TA=25°C TA=-40°C Vi=15V 80µ s Pulsed Load 120Hz Rate 15 R T=10K C T=3.3nF V FB=0V I Sense=0V T A=25°C UCX843/45 2 1 0 0 TA=-40°C TA=25°C 10 5 Sink Saturation (Load to Vi) 200 400 600 GND 0 IO(mA) 0 10 UCX842/44 3 20 30 Vi(V) Figure 11: Output Waveform. Figure 12: Output Cross Conduction Vi =30V CL = 15pF TA = 25°C VO 20V/DIV 90% Vi =15V CL = 1.0nF TA = 25°C ICC 10% 50ns/DIV 100ns/DIV 100mA/DIV Figure 13: Oscillator and Output Waveforms. Vi 7 8 5V REG PWM RT CLOCK 4 OSCILLATOR ID CT 5 GND D95IN344 CT OUTPUT 6 OUTPUT LARGE RT/SMALL CT CT OUTPUT SMALL RT/LARGE CT 7/15 UC2842A/3A/4A/5A - UC3842A/3A/4A/5A Figure 14 : Error Amp Configuration. 2.5V 1mA + VFB COMP Zf D95IN345 Zi 2 1 - Figure 15 : Under Voltage Lockout. Vi 7 ON/OFF COMMAND TO REST OF IC ICC UC3842A UC3843A UC3844A UC3845A VON VOFF 16V 10V 8.4V 7.6V